1/* 2 * Copyright (C) 2006-2007 PA Semi, Inc 3 * 4 * Author: Egor Martovetsky <egor@pasemi.com> 5 * Maintained by: Olof Johansson <olof@lixom.net> 6 * 7 * Driver for the PWRficient onchip memory controllers 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 24#include <linux/module.h> 25#include <linux/init.h> 26#include <linux/pci.h> 27#include <linux/pci_ids.h> 28#include <linux/edac.h> 29#include "edac_core.h" 30 31#define MODULE_NAME "pasemi_edac" 32 33#define MCCFG_MCEN 0x300 34#define MCCFG_MCEN_MMC_EN 0x00000001 35#define MCCFG_ERRCOR 0x388 36#define MCCFG_ERRCOR_RNK_FAIL_DET_EN 0x00000100 37#define MCCFG_ERRCOR_ECC_GEN_EN 0x00000010 38#define MCCFG_ERRCOR_ECC_CRR_EN 0x00000001 39#define MCCFG_SCRUB 0x384 40#define MCCFG_SCRUB_RGLR_SCRB_EN 0x00000001 41#define MCDEBUG_ERRCTL1 0x728 42#define MCDEBUG_ERRCTL1_RFL_LOG_EN 0x00080000 43#define MCDEBUG_ERRCTL1_MBE_LOG_EN 0x00040000 44#define MCDEBUG_ERRCTL1_SBE_LOG_EN 0x00020000 45#define MCDEBUG_ERRSTA 0x730 46#define MCDEBUG_ERRSTA_RFL_STATUS 0x00000004 47#define MCDEBUG_ERRSTA_MBE_STATUS 0x00000002 48#define MCDEBUG_ERRSTA_SBE_STATUS 0x00000001 49#define MCDEBUG_ERRCNT1 0x734 50#define MCDEBUG_ERRCNT1_SBE_CNT_OVRFLO 0x00000080 51#define MCDEBUG_ERRLOG1A 0x738 52#define MCDEBUG_ERRLOG1A_MERR_TYPE_M 0x30000000 53#define MCDEBUG_ERRLOG1A_MERR_TYPE_NONE 0x00000000 54#define MCDEBUG_ERRLOG1A_MERR_TYPE_SBE 0x10000000 55#define MCDEBUG_ERRLOG1A_MERR_TYPE_MBE 0x20000000 56#define MCDEBUG_ERRLOG1A_MERR_TYPE_RFL 0x30000000 57#define MCDEBUG_ERRLOG1A_MERR_BA_M 0x00700000 58#define MCDEBUG_ERRLOG1A_MERR_BA_S 20 59#define MCDEBUG_ERRLOG1A_MERR_CS_M 0x00070000 60#define MCDEBUG_ERRLOG1A_MERR_CS_S 16 61#define MCDEBUG_ERRLOG1A_SYNDROME_M 0x0000ffff 62#define MCDRAM_RANKCFG 0x114 63#define MCDRAM_RANKCFG_EN 0x00000001 64#define MCDRAM_RANKCFG_TYPE_SIZE_M 0x000001c0 65#define MCDRAM_RANKCFG_TYPE_SIZE_S 6 66 67#define PASEMI_EDAC_NR_CSROWS 8 68#define PASEMI_EDAC_NR_CHANS 1 69#define PASEMI_EDAC_ERROR_GRAIN 64 70 71static int last_page_in_mmc; 72static int system_mmc_id; 73 74 75static u32 pasemi_edac_get_error_info(struct mem_ctl_info *mci) 76{ 77 struct pci_dev *pdev = to_pci_dev(mci->dev); 78 u32 tmp; 79 80 pci_read_config_dword(pdev, MCDEBUG_ERRSTA, 81 &tmp); 82 83 tmp &= (MCDEBUG_ERRSTA_RFL_STATUS | MCDEBUG_ERRSTA_MBE_STATUS 84 | MCDEBUG_ERRSTA_SBE_STATUS); 85 86 if (tmp) { 87 if (tmp & MCDEBUG_ERRSTA_SBE_STATUS) 88 pci_write_config_dword(pdev, MCDEBUG_ERRCNT1, 89 MCDEBUG_ERRCNT1_SBE_CNT_OVRFLO); 90 pci_write_config_dword(pdev, MCDEBUG_ERRSTA, tmp); 91 } 92 93 return tmp; 94} 95 96static void pasemi_edac_process_error_info(struct mem_ctl_info *mci, u32 errsta) 97{ 98 struct pci_dev *pdev = to_pci_dev(mci->dev); 99 u32 errlog1a; 100 u32 cs; 101 102 if (!errsta) 103 return; 104 105 pci_read_config_dword(pdev, MCDEBUG_ERRLOG1A, &errlog1a); 106 107 cs = (errlog1a & MCDEBUG_ERRLOG1A_MERR_CS_M) >> 108 MCDEBUG_ERRLOG1A_MERR_CS_S; 109 110 /* uncorrectable/multi-bit errors */ 111 if (errsta & (MCDEBUG_ERRSTA_MBE_STATUS | 112 MCDEBUG_ERRSTA_RFL_STATUS)) { 113 edac_mc_handle_ue(mci, mci->csrows[cs].first_page, 0, 114 cs, mci->ctl_name); 115 } 116 117 /* correctable/single-bit errors */ 118 if (errsta & MCDEBUG_ERRSTA_SBE_STATUS) { 119 edac_mc_handle_ce(mci, mci->csrows[cs].first_page, 0, 120 0, cs, 0, mci->ctl_name); 121 } 122} 123 124static void pasemi_edac_check(struct mem_ctl_info *mci) 125{ 126 u32 errsta; 127 128 errsta = pasemi_edac_get_error_info(mci); 129 if (errsta) 130 pasemi_edac_process_error_info(mci, errsta); 131} 132 133static int pasemi_edac_init_csrows(struct mem_ctl_info *mci, 134 struct pci_dev *pdev, 135 enum edac_type edac_mode) 136{ 137 struct csrow_info *csrow; 138 u32 rankcfg; 139 int index; 140 141 for (index = 0; index < mci->nr_csrows; index++) { 142 csrow = &mci->csrows[index]; 143 144 pci_read_config_dword(pdev, 145 MCDRAM_RANKCFG + (index * 12), 146 &rankcfg); 147 148 if (!(rankcfg & MCDRAM_RANKCFG_EN)) 149 continue; 150 151 switch ((rankcfg & MCDRAM_RANKCFG_TYPE_SIZE_M) >> 152 MCDRAM_RANKCFG_TYPE_SIZE_S) { 153 case 0: 154 csrow->nr_pages = 128 << (20 - PAGE_SHIFT); 155 break; 156 case 1: 157 csrow->nr_pages = 256 << (20 - PAGE_SHIFT); 158 break; 159 case 2: 160 case 3: 161 csrow->nr_pages = 512 << (20 - PAGE_SHIFT); 162 break; 163 case 4: 164 csrow->nr_pages = 1024 << (20 - PAGE_SHIFT); 165 break; 166 case 5: 167 csrow->nr_pages = 2048 << (20 - PAGE_SHIFT); 168 break; 169 default: 170 edac_mc_printk(mci, KERN_ERR, 171 "Unrecognized Rank Config. rankcfg=%u\n", 172 rankcfg); 173 return -EINVAL; 174 } 175 176 csrow->first_page = last_page_in_mmc; 177 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; 178 last_page_in_mmc += csrow->nr_pages; 179 csrow->page_mask = 0; 180 csrow->grain = PASEMI_EDAC_ERROR_GRAIN; 181 csrow->mtype = MEM_DDR; 182 csrow->dtype = DEV_UNKNOWN; 183 csrow->edac_mode = edac_mode; 184 } 185 return 0; 186} 187 188static int __devinit pasemi_edac_probe(struct pci_dev *pdev, 189 const struct pci_device_id *ent) 190{ 191 struct mem_ctl_info *mci = NULL; 192 u32 errctl1, errcor, scrub, mcen; 193 194 pci_read_config_dword(pdev, MCCFG_MCEN, &mcen); 195 if (!(mcen & MCCFG_MCEN_MMC_EN)) 196 return -ENODEV; 197 198 /* 199 * We should think about enabling other error detection later on 200 */ 201 202 pci_read_config_dword(pdev, MCDEBUG_ERRCTL1, &errctl1); 203 errctl1 |= MCDEBUG_ERRCTL1_SBE_LOG_EN | 204 MCDEBUG_ERRCTL1_MBE_LOG_EN | 205 MCDEBUG_ERRCTL1_RFL_LOG_EN; 206 pci_write_config_dword(pdev, MCDEBUG_ERRCTL1, errctl1); 207 208 mci = edac_mc_alloc(0, PASEMI_EDAC_NR_CSROWS, PASEMI_EDAC_NR_CHANS, 209 system_mmc_id++); 210 211 if (mci == NULL) 212 return -ENOMEM; 213 214 pci_read_config_dword(pdev, MCCFG_ERRCOR, &errcor); 215 errcor |= MCCFG_ERRCOR_RNK_FAIL_DET_EN | 216 MCCFG_ERRCOR_ECC_GEN_EN | 217 MCCFG_ERRCOR_ECC_CRR_EN; 218 219 mci->dev = &pdev->dev; 220 mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR; 221 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 222 mci->edac_cap = (errcor & MCCFG_ERRCOR_ECC_GEN_EN) ? 223 ((errcor & MCCFG_ERRCOR_ECC_CRR_EN) ? 224 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_EC) : 225 EDAC_FLAG_NONE; 226 mci->mod_name = MODULE_NAME; 227 mci->dev_name = pci_name(pdev); 228 mci->ctl_name = "pasemi,pwrficient-mc"; 229 mci->edac_check = pasemi_edac_check; 230 mci->ctl_page_to_phys = NULL; 231 pci_read_config_dword(pdev, MCCFG_SCRUB, &scrub); 232 mci->scrub_cap = SCRUB_FLAG_HW_PROG | SCRUB_FLAG_HW_SRC; 233 mci->scrub_mode = 234 ((errcor & MCCFG_ERRCOR_ECC_CRR_EN) ? SCRUB_FLAG_HW_SRC : 0) | 235 ((scrub & MCCFG_SCRUB_RGLR_SCRB_EN) ? SCRUB_FLAG_HW_PROG : 0); 236 237 if (pasemi_edac_init_csrows(mci, pdev, 238 (mci->edac_cap & EDAC_FLAG_SECDED) ? 239 EDAC_SECDED : 240 ((mci->edac_cap & EDAC_FLAG_EC) ? 241 EDAC_EC : EDAC_NONE))) 242 goto fail; 243 244 /* 245 * Clear status 246 */ 247 pasemi_edac_get_error_info(mci); 248 249 if (edac_mc_add_mc(mci)) 250 goto fail; 251 252 /* get this far and it's successful */ 253 return 0; 254 255fail: 256 edac_mc_free(mci); 257 return -ENODEV; 258} 259 260static void __devexit pasemi_edac_remove(struct pci_dev *pdev) 261{ 262 struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev); 263 264 if (!mci) 265 return; 266 267 edac_mc_free(mci); 268} 269 270 271static const struct pci_device_id pasemi_edac_pci_tbl[] = { 272 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa00a) }, 273 { } 274}; 275 276MODULE_DEVICE_TABLE(pci, pasemi_edac_pci_tbl); 277 278static struct pci_driver pasemi_edac_driver = { 279 .name = MODULE_NAME, 280 .probe = pasemi_edac_probe, 281 .remove = __devexit_p(pasemi_edac_remove), 282 .id_table = pasemi_edac_pci_tbl, 283}; 284 285static int __init pasemi_edac_init(void) 286{ 287 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 288 opstate_init(); 289 290 return pci_register_driver(&pasemi_edac_driver); 291} 292 293static void __exit pasemi_edac_exit(void) 294{ 295 pci_unregister_driver(&pasemi_edac_driver); 296} 297 298module_init(pasemi_edac_init); 299module_exit(pasemi_edac_exit); 300 301MODULE_LICENSE("GPL"); 302MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>"); 303MODULE_DESCRIPTION("MC support for PA Semi PWRficient memory controller"); 304module_param(edac_op_state, int, 0444); 305MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 306