1#ifndef __MV_CRYPTO_H__ 2 3#define DIGEST_INITIAL_VAL_A 0xdd00 4#define DIGEST_INITIAL_VAL_B 0xdd04 5#define DIGEST_INITIAL_VAL_C 0xdd08 6#define DIGEST_INITIAL_VAL_D 0xdd0c 7#define DIGEST_INITIAL_VAL_E 0xdd10 8#define DES_CMD_REG 0xdd58 9 10#define SEC_ACCEL_CMD 0xde00 11#define SEC_CMD_EN_SEC_ACCL0 (1 << 0) 12#define SEC_CMD_EN_SEC_ACCL1 (1 << 1) 13#define SEC_CMD_DISABLE_SEC (1 << 2) 14 15#define SEC_ACCEL_DESC_P0 0xde04 16#define SEC_DESC_P0_PTR(x) (x) 17 18#define SEC_ACCEL_DESC_P1 0xde14 19#define SEC_DESC_P1_PTR(x) (x) 20 21#define SEC_ACCEL_CFG 0xde08 22#define SEC_CFG_STOP_DIG_ERR (1 << 0) 23#define SEC_CFG_CH0_W_IDMA (1 << 7) 24#define SEC_CFG_CH1_W_IDMA (1 << 8) 25#define SEC_CFG_ACT_CH0_IDMA (1 << 9) 26#define SEC_CFG_ACT_CH1_IDMA (1 << 10) 27 28#define SEC_ACCEL_STATUS 0xde0c 29#define SEC_ST_ACT_0 (1 << 0) 30#define SEC_ST_ACT_1 (1 << 1) 31 32/* 33 * FPGA_INT_STATUS looks like a FPGA leftover and is documented only in Errata 34 * 4.12. It looks like that it was part of an IRQ-controller in FPGA and 35 * someone forgot to remove it while switching to the core and moving to 36 * SEC_ACCEL_INT_STATUS. 37 */ 38#define FPGA_INT_STATUS 0xdd68 39#define SEC_ACCEL_INT_STATUS 0xde20 40#define SEC_INT_AUTH_DONE (1 << 0) 41#define SEC_INT_DES_E_DONE (1 << 1) 42#define SEC_INT_AES_E_DONE (1 << 2) 43#define SEC_INT_AES_D_DONE (1 << 3) 44#define SEC_INT_ENC_DONE (1 << 4) 45#define SEC_INT_ACCEL0_DONE (1 << 5) 46#define SEC_INT_ACCEL1_DONE (1 << 6) 47#define SEC_INT_ACC0_IDMA_DONE (1 << 7) 48#define SEC_INT_ACC1_IDMA_DONE (1 << 8) 49 50#define SEC_ACCEL_INT_MASK 0xde24 51 52#define AES_KEY_LEN (8 * 4) 53 54struct sec_accel_config { 55 56 u32 config; 57#define CFG_OP_MAC_ONLY 0 58#define CFG_OP_CRYPT_ONLY 1 59#define CFG_OP_MAC_CRYPT 2 60#define CFG_OP_CRYPT_MAC 3 61#define CFG_MACM_MD5 (4 << 4) 62#define CFG_MACM_SHA1 (5 << 4) 63#define CFG_MACM_HMAC_MD5 (6 << 4) 64#define CFG_MACM_HMAC_SHA1 (7 << 4) 65#define CFG_ENCM_DES (1 << 8) 66#define CFG_ENCM_3DES (2 << 8) 67#define CFG_ENCM_AES (3 << 8) 68#define CFG_DIR_ENC (0 << 12) 69#define CFG_DIR_DEC (1 << 12) 70#define CFG_ENC_MODE_ECB (0 << 16) 71#define CFG_ENC_MODE_CBC (1 << 16) 72#define CFG_3DES_EEE (0 << 20) 73#define CFG_3DES_EDE (1 << 20) 74#define CFG_AES_LEN_128 (0 << 24) 75#define CFG_AES_LEN_192 (1 << 24) 76#define CFG_AES_LEN_256 (2 << 24) 77#define CFG_NOT_FRAG (0 << 30) 78#define CFG_FIRST_FRAG (1 << 30) 79#define CFG_LAST_FRAG (2 << 30) 80#define CFG_MID_FRAG (3 << 30) 81 82 u32 enc_p; 83#define ENC_P_SRC(x) (x) 84#define ENC_P_DST(x) ((x) << 16) 85 86 u32 enc_len; 87#define ENC_LEN(x) (x) 88 89 u32 enc_key_p; 90#define ENC_KEY_P(x) (x) 91 92 u32 enc_iv; 93#define ENC_IV_POINT(x) ((x) << 0) 94#define ENC_IV_BUF_POINT(x) ((x) << 16) 95 96 u32 mac_src_p; 97#define MAC_SRC_DATA_P(x) (x) 98#define MAC_SRC_TOTAL_LEN(x) ((x) << 16) 99 100 u32 mac_digest; 101#define MAC_DIGEST_P(x) (x) 102#define MAC_FRAG_LEN(x) ((x) << 16) 103 u32 mac_iv; 104#define MAC_INNER_IV_P(x) (x) 105#define MAC_OUTER_IV_P(x) ((x) << 16) 106}__attribute__ ((packed)); 107 /* 108 * /-----------\ 0 109 * | ACCEL CFG | 4 * 8 110 * |-----------| 0x20 111 * | CRYPT KEY | 8 * 4 112 * |-----------| 0x40 113 * | IV IN | 4 * 4 114 * |-----------| 0x40 (inplace) 115 * | IV BUF | 4 * 4 116 * |-----------| 0x80 117 * | DATA IN | 16 * x (max ->max_req_size) 118 * |-----------| 0x80 (inplace operation) 119 * | DATA OUT | 16 * x (max ->max_req_size) 120 * \-----------/ SRAM size 121 */ 122 123 /* Hashing memory map: 124 * /-----------\ 0 125 * | ACCEL CFG | 4 * 8 126 * |-----------| 0x20 127 * | Inner IV | 5 * 4 128 * |-----------| 0x34 129 * | Outer IV | 5 * 4 130 * |-----------| 0x48 131 * | Output BUF| 5 * 4 132 * |-----------| 0x80 133 * | DATA IN | 64 * x (max ->max_req_size) 134 * \-----------/ SRAM size 135 */ 136#define SRAM_CONFIG 0x00 137#define SRAM_DATA_KEY_P 0x20 138#define SRAM_DATA_IV 0x40 139#define SRAM_DATA_IV_BUF 0x40 140#define SRAM_DATA_IN_START 0x80 141#define SRAM_DATA_OUT_START 0x80 142 143#define SRAM_HMAC_IV_IN 0x20 144#define SRAM_HMAC_IV_OUT 0x34 145#define SRAM_DIGEST_BUF 0x48 146 147#define SRAM_CFG_SPACE 0x80 148 149#endif 150