1/* 2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 Exp $ 3 * 4 * Device driver for Microgate SyncLink Multiport 5 * high speed multiprotocol serial adapter. 6 * 7 * written by Paul Fulghum for Microgate Corporation 8 * paulkf@microgate.com 9 * 10 * Microgate and SyncLink are trademarks of Microgate Corporation 11 * 12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds 13 * This code is released under the GNU General Public License (GPL) 14 * 15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 25 * OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) 29#if defined(__i386__) 30# define BREAKPOINT() asm(" int $3"); 31#else 32# define BREAKPOINT() { } 33#endif 34 35#define MAX_DEVICES 12 36 37#include <linux/module.h> 38#include <linux/errno.h> 39#include <linux/signal.h> 40#include <linux/sched.h> 41#include <linux/timer.h> 42#include <linux/interrupt.h> 43#include <linux/pci.h> 44#include <linux/tty.h> 45#include <linux/tty_flip.h> 46#include <linux/serial.h> 47#include <linux/major.h> 48#include <linux/string.h> 49#include <linux/fcntl.h> 50#include <linux/ptrace.h> 51#include <linux/ioport.h> 52#include <linux/mm.h> 53#include <linux/seq_file.h> 54#include <linux/slab.h> 55#include <linux/netdevice.h> 56#include <linux/vmalloc.h> 57#include <linux/init.h> 58#include <linux/delay.h> 59#include <linux/ioctl.h> 60 61#include <asm/system.h> 62#include <asm/io.h> 63#include <asm/irq.h> 64#include <asm/dma.h> 65#include <linux/bitops.h> 66#include <asm/types.h> 67#include <linux/termios.h> 68#include <linux/workqueue.h> 69#include <linux/hdlc.h> 70#include <linux/synclink.h> 71 72#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && \ 73 defined(CONFIG_SYNCLINKMP_MODULE)) 74#define SYNCLINK_GENERIC_HDLC 1 75#else 76#define SYNCLINK_GENERIC_HDLC 0 77#endif 78 79#define GET_USER(error,value,addr) error = get_user(value,addr) 80#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 81#define PUT_USER(error,value,addr) error = put_user(value,addr) 82#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 83 84#include <asm/uaccess.h> 85 86static MGSL_PARAMS default_params = { 87 MGSL_MODE_HDLC, /* unsigned long mode */ 88 0, /* unsigned char loopback; */ 89 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */ 90 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */ 91 0, /* unsigned long clock_speed; */ 92 0xff, /* unsigned char addr_filter; */ 93 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */ 94 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */ 95 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */ 96 9600, /* unsigned long data_rate; */ 97 8, /* unsigned char data_bits; */ 98 1, /* unsigned char stop_bits; */ 99 ASYNC_PARITY_NONE /* unsigned char parity; */ 100}; 101 102/* size in bytes of DMA data buffers */ 103#define SCABUFSIZE 1024 104#define SCA_MEM_SIZE 0x40000 105#define SCA_BASE_SIZE 512 106#define SCA_REG_SIZE 16 107#define SCA_MAX_PORTS 4 108#define SCAMAXDESC 128 109 110#define BUFFERLISTSIZE 4096 111 112/* SCA-I style DMA buffer descriptor */ 113typedef struct _SCADESC 114{ 115 u16 next; /* lower l6 bits of next descriptor addr */ 116 u16 buf_ptr; /* lower 16 bits of buffer addr */ 117 u8 buf_base; /* upper 8 bits of buffer addr */ 118 u8 pad1; 119 u16 length; /* length of buffer */ 120 u8 status; /* status of buffer */ 121 u8 pad2; 122} SCADESC, *PSCADESC; 123 124typedef struct _SCADESC_EX 125{ 126 /* device driver bookkeeping section */ 127 char *virt_addr; /* virtual address of data buffer */ 128 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */ 129} SCADESC_EX, *PSCADESC_EX; 130 131/* The queue of BH actions to be performed */ 132 133#define BH_RECEIVE 1 134#define BH_TRANSMIT 2 135#define BH_STATUS 4 136 137#define IO_PIN_SHUTDOWN_LIMIT 100 138 139struct _input_signal_events { 140 int ri_up; 141 int ri_down; 142 int dsr_up; 143 int dsr_down; 144 int dcd_up; 145 int dcd_down; 146 int cts_up; 147 int cts_down; 148}; 149 150/* 151 * Device instance data structure 152 */ 153typedef struct _synclinkmp_info { 154 void *if_ptr; /* General purpose pointer (used by SPPP) */ 155 int magic; 156 struct tty_port port; 157 int line; 158 unsigned short close_delay; 159 unsigned short closing_wait; /* time to wait before closing */ 160 161 struct mgsl_icount icount; 162 163 int timeout; 164 int x_char; /* xon/xoff character */ 165 u16 read_status_mask1; /* break detection (SR1 indications) */ 166 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */ 167 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */ 168 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */ 169 unsigned char *tx_buf; 170 int tx_put; 171 int tx_get; 172 int tx_count; 173 174 wait_queue_head_t status_event_wait_q; 175 wait_queue_head_t event_wait_q; 176 struct timer_list tx_timer; /* HDLC transmit timeout timer */ 177 struct _synclinkmp_info *next_device; /* device list link */ 178 struct timer_list status_timer; /* input signal status check timer */ 179 180 spinlock_t lock; /* spinlock for synchronizing with ISR */ 181 struct work_struct task; /* task structure for scheduling bh */ 182 183 u32 max_frame_size; /* as set by device config */ 184 185 u32 pending_bh; 186 187 bool bh_running; /* Protection from multiple */ 188 int isr_overflow; 189 bool bh_requested; 190 191 int dcd_chkcount; /* check counts to prevent */ 192 int cts_chkcount; /* too many IRQs if a signal */ 193 int dsr_chkcount; /* is floating */ 194 int ri_chkcount; 195 196 char *buffer_list; /* virtual address of Rx & Tx buffer lists */ 197 unsigned long buffer_list_phys; 198 199 unsigned int rx_buf_count; /* count of total allocated Rx buffers */ 200 SCADESC *rx_buf_list; /* list of receive buffer entries */ 201 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */ 202 unsigned int current_rx_buf; 203 204 unsigned int tx_buf_count; /* count of total allocated Tx buffers */ 205 SCADESC *tx_buf_list; /* list of transmit buffer entries */ 206 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */ 207 unsigned int last_tx_buf; 208 209 unsigned char *tmp_rx_buf; 210 unsigned int tmp_rx_buf_count; 211 212 bool rx_enabled; 213 bool rx_overflow; 214 215 bool tx_enabled; 216 bool tx_active; 217 u32 idle_mode; 218 219 unsigned char ie0_value; 220 unsigned char ie1_value; 221 unsigned char ie2_value; 222 unsigned char ctrlreg_value; 223 unsigned char old_signals; 224 225 char device_name[25]; /* device instance name */ 226 227 int port_count; 228 int adapter_num; 229 int port_num; 230 231 struct _synclinkmp_info *port_array[SCA_MAX_PORTS]; 232 233 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */ 234 235 unsigned int irq_level; /* interrupt level */ 236 unsigned long irq_flags; 237 bool irq_requested; /* true if IRQ requested */ 238 239 MGSL_PARAMS params; /* communications parameters */ 240 241 unsigned char serial_signals; /* current serial signal states */ 242 243 bool irq_occurred; /* for diagnostics use */ 244 unsigned int init_error; /* Initialization startup error */ 245 246 u32 last_mem_alloc; 247 unsigned char* memory_base; /* shared memory address (PCI only) */ 248 u32 phys_memory_base; 249 int shared_mem_requested; 250 251 unsigned char* sca_base; /* HD64570 SCA Memory address */ 252 u32 phys_sca_base; 253 u32 sca_offset; 254 bool sca_base_requested; 255 256 unsigned char* lcr_base; /* local config registers (PCI only) */ 257 u32 phys_lcr_base; 258 u32 lcr_offset; 259 int lcr_mem_requested; 260 261 unsigned char* statctrl_base; /* status/control register memory */ 262 u32 phys_statctrl_base; 263 u32 statctrl_offset; 264 bool sca_statctrl_requested; 265 266 u32 misc_ctrl_value; 267 char flag_buf[MAX_ASYNC_BUFFER_SIZE]; 268 char char_buf[MAX_ASYNC_BUFFER_SIZE]; 269 bool drop_rts_on_tx_done; 270 271 struct _input_signal_events input_signal_events; 272 273 /* SPPP/Cisco HDLC device parts */ 274 int netcount; 275 spinlock_t netlock; 276 277#if SYNCLINK_GENERIC_HDLC 278 struct net_device *netdev; 279#endif 280 281} SLMP_INFO; 282 283#define MGSL_MAGIC 0x5401 284 285/* 286 * define serial signal status change macros 287 */ 288#define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */ 289#define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */ 290#define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */ 291#define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */ 292 293/* Common Register macros */ 294#define LPR 0x00 295#define PABR0 0x02 296#define PABR1 0x03 297#define WCRL 0x04 298#define WCRM 0x05 299#define WCRH 0x06 300#define DPCR 0x08 301#define DMER 0x09 302#define ISR0 0x10 303#define ISR1 0x11 304#define ISR2 0x12 305#define IER0 0x14 306#define IER1 0x15 307#define IER2 0x16 308#define ITCR 0x18 309#define INTVR 0x1a 310#define IMVR 0x1c 311 312/* MSCI Register macros */ 313#define TRB 0x20 314#define TRBL 0x20 315#define TRBH 0x21 316#define SR0 0x22 317#define SR1 0x23 318#define SR2 0x24 319#define SR3 0x25 320#define FST 0x26 321#define IE0 0x28 322#define IE1 0x29 323#define IE2 0x2a 324#define FIE 0x2b 325#define CMD 0x2c 326#define MD0 0x2e 327#define MD1 0x2f 328#define MD2 0x30 329#define CTL 0x31 330#define SA0 0x32 331#define SA1 0x33 332#define IDL 0x34 333#define TMC 0x35 334#define RXS 0x36 335#define TXS 0x37 336#define TRC0 0x38 337#define TRC1 0x39 338#define RRC 0x3a 339#define CST0 0x3c 340#define CST1 0x3d 341 342/* Timer Register Macros */ 343#define TCNT 0x60 344#define TCNTL 0x60 345#define TCNTH 0x61 346#define TCONR 0x62 347#define TCONRL 0x62 348#define TCONRH 0x63 349#define TMCS 0x64 350#define TEPR 0x65 351 352/* DMA Controller Register macros */ 353#define DARL 0x80 354#define DARH 0x81 355#define DARB 0x82 356#define BAR 0x80 357#define BARL 0x80 358#define BARH 0x81 359#define BARB 0x82 360#define SAR 0x84 361#define SARL 0x84 362#define SARH 0x85 363#define SARB 0x86 364#define CPB 0x86 365#define CDA 0x88 366#define CDAL 0x88 367#define CDAH 0x89 368#define EDA 0x8a 369#define EDAL 0x8a 370#define EDAH 0x8b 371#define BFL 0x8c 372#define BFLL 0x8c 373#define BFLH 0x8d 374#define BCR 0x8e 375#define BCRL 0x8e 376#define BCRH 0x8f 377#define DSR 0x90 378#define DMR 0x91 379#define FCT 0x93 380#define DIR 0x94 381#define DCMD 0x95 382 383/* combine with timer or DMA register address */ 384#define TIMER0 0x00 385#define TIMER1 0x08 386#define TIMER2 0x10 387#define TIMER3 0x18 388#define RXDMA 0x00 389#define TXDMA 0x20 390 391/* SCA Command Codes */ 392#define NOOP 0x00 393#define TXRESET 0x01 394#define TXENABLE 0x02 395#define TXDISABLE 0x03 396#define TXCRCINIT 0x04 397#define TXCRCEXCL 0x05 398#define TXEOM 0x06 399#define TXABORT 0x07 400#define MPON 0x08 401#define TXBUFCLR 0x09 402#define RXRESET 0x11 403#define RXENABLE 0x12 404#define RXDISABLE 0x13 405#define RXCRCINIT 0x14 406#define RXREJECT 0x15 407#define SEARCHMP 0x16 408#define RXCRCEXCL 0x17 409#define RXCRCCALC 0x18 410#define CHRESET 0x21 411#define HUNT 0x31 412 413/* DMA command codes */ 414#define SWABORT 0x01 415#define FEICLEAR 0x02 416 417/* IE0 */ 418#define TXINTE BIT7 419#define RXINTE BIT6 420#define TXRDYE BIT1 421#define RXRDYE BIT0 422 423/* IE1 & SR1 */ 424#define UDRN BIT7 425#define IDLE BIT6 426#define SYNCD BIT4 427#define FLGD BIT4 428#define CCTS BIT3 429#define CDCD BIT2 430#define BRKD BIT1 431#define ABTD BIT1 432#define GAPD BIT1 433#define BRKE BIT0 434#define IDLD BIT0 435 436/* IE2 & SR2 */ 437#define EOM BIT7 438#define PMP BIT6 439#define SHRT BIT6 440#define PE BIT5 441#define ABT BIT5 442#define FRME BIT4 443#define RBIT BIT4 444#define OVRN BIT3 445#define CRCE BIT2 446 447 448/* 449 * Global linked list of SyncLink devices 450 */ 451static SLMP_INFO *synclinkmp_device_list = NULL; 452static int synclinkmp_adapter_count = -1; 453static int synclinkmp_device_count = 0; 454 455/* 456 * Set this param to non-zero to load eax with the 457 * .text section address and breakpoint on module load. 458 * This is useful for use with gdb and add-symbol-file command. 459 */ 460static int break_on_load = 0; 461 462/* 463 * Driver major number, defaults to zero to get auto 464 * assigned major number. May be forced as module parameter. 465 */ 466static int ttymajor = 0; 467 468/* 469 * Array of user specified options for ISA adapters. 470 */ 471static int debug_level = 0; 472static int maxframe[MAX_DEVICES] = {0,}; 473 474module_param(break_on_load, bool, 0); 475module_param(ttymajor, int, 0); 476module_param(debug_level, int, 0); 477module_param_array(maxframe, int, NULL, 0); 478 479static char *driver_name = "SyncLink MultiPort driver"; 480static char *driver_version = "$Revision: 4.38 $"; 481 482static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent); 483static void synclinkmp_remove_one(struct pci_dev *dev); 484 485static struct pci_device_id synclinkmp_pci_tbl[] = { 486 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, }, 487 { 0, }, /* terminate list */ 488}; 489MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl); 490 491MODULE_LICENSE("GPL"); 492 493static struct pci_driver synclinkmp_pci_driver = { 494 .name = "synclinkmp", 495 .id_table = synclinkmp_pci_tbl, 496 .probe = synclinkmp_init_one, 497 .remove = __devexit_p(synclinkmp_remove_one), 498}; 499 500 501static struct tty_driver *serial_driver; 502 503/* number of characters left in xmit buffer before we ask for more */ 504#define WAKEUP_CHARS 256 505 506 507/* tty callbacks */ 508 509static int open(struct tty_struct *tty, struct file * filp); 510static void close(struct tty_struct *tty, struct file * filp); 511static void hangup(struct tty_struct *tty); 512static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); 513 514static int write(struct tty_struct *tty, const unsigned char *buf, int count); 515static int put_char(struct tty_struct *tty, unsigned char ch); 516static void send_xchar(struct tty_struct *tty, char ch); 517static void wait_until_sent(struct tty_struct *tty, int timeout); 518static int write_room(struct tty_struct *tty); 519static void flush_chars(struct tty_struct *tty); 520static void flush_buffer(struct tty_struct *tty); 521static void tx_hold(struct tty_struct *tty); 522static void tx_release(struct tty_struct *tty); 523 524static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg); 525static int chars_in_buffer(struct tty_struct *tty); 526static void throttle(struct tty_struct * tty); 527static void unthrottle(struct tty_struct * tty); 528static int set_break(struct tty_struct *tty, int break_state); 529 530#if SYNCLINK_GENERIC_HDLC 531#define dev_to_port(D) (dev_to_hdlc(D)->priv) 532static void hdlcdev_tx_done(SLMP_INFO *info); 533static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size); 534static int hdlcdev_init(SLMP_INFO *info); 535static void hdlcdev_exit(SLMP_INFO *info); 536#endif 537 538/* ioctl handlers */ 539 540static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount); 541static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params); 542static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params); 543static int get_txidle(SLMP_INFO *info, int __user *idle_mode); 544static int set_txidle(SLMP_INFO *info, int idle_mode); 545static int tx_enable(SLMP_INFO *info, int enable); 546static int tx_abort(SLMP_INFO *info); 547static int rx_enable(SLMP_INFO *info, int enable); 548static int modem_input_wait(SLMP_INFO *info,int arg); 549static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr); 550static int tiocmget(struct tty_struct *tty, struct file *file); 551static int tiocmset(struct tty_struct *tty, struct file *file, 552 unsigned int set, unsigned int clear); 553static int set_break(struct tty_struct *tty, int break_state); 554 555static void add_device(SLMP_INFO *info); 556static void device_init(int adapter_num, struct pci_dev *pdev); 557static int claim_resources(SLMP_INFO *info); 558static void release_resources(SLMP_INFO *info); 559 560static int startup(SLMP_INFO *info); 561static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info); 562static int carrier_raised(struct tty_port *port); 563static void shutdown(SLMP_INFO *info); 564static void program_hw(SLMP_INFO *info); 565static void change_params(SLMP_INFO *info); 566 567static bool init_adapter(SLMP_INFO *info); 568static bool register_test(SLMP_INFO *info); 569static bool irq_test(SLMP_INFO *info); 570static bool loopback_test(SLMP_INFO *info); 571static int adapter_test(SLMP_INFO *info); 572static bool memory_test(SLMP_INFO *info); 573 574static void reset_adapter(SLMP_INFO *info); 575static void reset_port(SLMP_INFO *info); 576static void async_mode(SLMP_INFO *info); 577static void hdlc_mode(SLMP_INFO *info); 578 579static void rx_stop(SLMP_INFO *info); 580static void rx_start(SLMP_INFO *info); 581static void rx_reset_buffers(SLMP_INFO *info); 582static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last); 583static bool rx_get_frame(SLMP_INFO *info); 584 585static void tx_start(SLMP_INFO *info); 586static void tx_stop(SLMP_INFO *info); 587static void tx_load_fifo(SLMP_INFO *info); 588static void tx_set_idle(SLMP_INFO *info); 589static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count); 590 591static void get_signals(SLMP_INFO *info); 592static void set_signals(SLMP_INFO *info); 593static void enable_loopback(SLMP_INFO *info, int enable); 594static void set_rate(SLMP_INFO *info, u32 data_rate); 595 596static int bh_action(SLMP_INFO *info); 597static void bh_handler(struct work_struct *work); 598static void bh_receive(SLMP_INFO *info); 599static void bh_transmit(SLMP_INFO *info); 600static void bh_status(SLMP_INFO *info); 601static void isr_timer(SLMP_INFO *info); 602static void isr_rxint(SLMP_INFO *info); 603static void isr_rxrdy(SLMP_INFO *info); 604static void isr_txint(SLMP_INFO *info); 605static void isr_txrdy(SLMP_INFO *info); 606static void isr_rxdmaok(SLMP_INFO *info); 607static void isr_rxdmaerror(SLMP_INFO *info); 608static void isr_txdmaok(SLMP_INFO *info); 609static void isr_txdmaerror(SLMP_INFO *info); 610static void isr_io_pin(SLMP_INFO *info, u16 status); 611 612static int alloc_dma_bufs(SLMP_INFO *info); 613static void free_dma_bufs(SLMP_INFO *info); 614static int alloc_buf_list(SLMP_INFO *info); 615static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count); 616static int alloc_tmp_rx_buf(SLMP_INFO *info); 617static void free_tmp_rx_buf(SLMP_INFO *info); 618 619static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count); 620static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit); 621static void tx_timeout(unsigned long context); 622static void status_timeout(unsigned long context); 623 624static unsigned char read_reg(SLMP_INFO *info, unsigned char addr); 625static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val); 626static u16 read_reg16(SLMP_INFO *info, unsigned char addr); 627static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val); 628static unsigned char read_status_reg(SLMP_INFO * info); 629static void write_control_reg(SLMP_INFO * info); 630 631 632static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes 633static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes 634static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes 635 636static u32 misc_ctrl_value = 0x007e4040; 637static u32 lcr1_brdr_value = 0x00800028; 638 639static u32 read_ahead_count = 8; 640 641/* DPCR, DMA Priority Control 642 * 643 * 07..05 Not used, must be 0 644 * 04 BRC, bus release condition: 0=all transfers complete 645 * 1=release after 1 xfer on all channels 646 * 03 CCC, channel change condition: 0=every cycle 647 * 1=after each channel completes all xfers 648 * 02..00 PR<2..0>, priority 100=round robin 649 * 650 * 00000100 = 0x00 651 */ 652static unsigned char dma_priority = 0x04; 653 654// Number of bytes that can be written to shared RAM 655// in a single write operation 656static u32 sca_pci_load_interval = 64; 657 658/* 659 * 1st function defined in .text section. Calling this function in 660 * init_module() followed by a breakpoint allows a remote debugger 661 * (gdb) to get the .text address for the add-symbol-file command. 662 * This allows remote debugging of dynamically loadable modules. 663 */ 664static void* synclinkmp_get_text_ptr(void); 665static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;} 666 667static inline int sanity_check(SLMP_INFO *info, 668 char *name, const char *routine) 669{ 670#ifdef SANITY_CHECK 671 static const char *badmagic = 672 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n"; 673 static const char *badinfo = 674 "Warning: null synclinkmp_struct for (%s) in %s\n"; 675 676 if (!info) { 677 printk(badinfo, name, routine); 678 return 1; 679 } 680 if (info->magic != MGSL_MAGIC) { 681 printk(badmagic, name, routine); 682 return 1; 683 } 684#else 685 if (!info) 686 return 1; 687#endif 688 return 0; 689} 690 691/** 692 * line discipline callback wrappers 693 * 694 * The wrappers maintain line discipline references 695 * while calling into the line discipline. 696 * 697 * ldisc_receive_buf - pass receive data to line discipline 698 */ 699 700static void ldisc_receive_buf(struct tty_struct *tty, 701 const __u8 *data, char *flags, int count) 702{ 703 struct tty_ldisc *ld; 704 if (!tty) 705 return; 706 ld = tty_ldisc_ref(tty); 707 if (ld) { 708 if (ld->ops->receive_buf) 709 ld->ops->receive_buf(tty, data, flags, count); 710 tty_ldisc_deref(ld); 711 } 712} 713 714/* tty callbacks */ 715 716/* Called when a port is opened. Init and enable port. 717 */ 718static int open(struct tty_struct *tty, struct file *filp) 719{ 720 SLMP_INFO *info; 721 int retval, line; 722 unsigned long flags; 723 724 line = tty->index; 725 if ((line < 0) || (line >= synclinkmp_device_count)) { 726 printk("%s(%d): open with invalid line #%d.\n", 727 __FILE__,__LINE__,line); 728 return -ENODEV; 729 } 730 731 info = synclinkmp_device_list; 732 while(info && info->line != line) 733 info = info->next_device; 734 if (sanity_check(info, tty->name, "open")) 735 return -ENODEV; 736 if ( info->init_error ) { 737 printk("%s(%d):%s device is not allocated, init error=%d\n", 738 __FILE__,__LINE__,info->device_name,info->init_error); 739 return -ENODEV; 740 } 741 742 tty->driver_data = info; 743 info->port.tty = tty; 744 745 if (debug_level >= DEBUG_LEVEL_INFO) 746 printk("%s(%d):%s open(), old ref count = %d\n", 747 __FILE__,__LINE__,tty->driver->name, info->port.count); 748 749 /* If port is closing, signal caller to try again */ 750 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){ 751 if (info->port.flags & ASYNC_CLOSING) 752 interruptible_sleep_on(&info->port.close_wait); 753 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ? 754 -EAGAIN : -ERESTARTSYS); 755 goto cleanup; 756 } 757 758 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; 759 760 spin_lock_irqsave(&info->netlock, flags); 761 if (info->netcount) { 762 retval = -EBUSY; 763 spin_unlock_irqrestore(&info->netlock, flags); 764 goto cleanup; 765 } 766 info->port.count++; 767 spin_unlock_irqrestore(&info->netlock, flags); 768 769 if (info->port.count == 1) { 770 /* 1st open on this device, init hardware */ 771 retval = startup(info); 772 if (retval < 0) 773 goto cleanup; 774 } 775 776 retval = block_til_ready(tty, filp, info); 777 if (retval) { 778 if (debug_level >= DEBUG_LEVEL_INFO) 779 printk("%s(%d):%s block_til_ready() returned %d\n", 780 __FILE__,__LINE__, info->device_name, retval); 781 goto cleanup; 782 } 783 784 if (debug_level >= DEBUG_LEVEL_INFO) 785 printk("%s(%d):%s open() success\n", 786 __FILE__,__LINE__, info->device_name); 787 retval = 0; 788 789cleanup: 790 if (retval) { 791 if (tty->count == 1) 792 info->port.tty = NULL; /* tty layer will release tty struct */ 793 if(info->port.count) 794 info->port.count--; 795 } 796 797 return retval; 798} 799 800/* Called when port is closed. Wait for remaining data to be 801 * sent. Disable port and free resources. 802 */ 803static void close(struct tty_struct *tty, struct file *filp) 804{ 805 SLMP_INFO * info = tty->driver_data; 806 807 if (sanity_check(info, tty->name, "close")) 808 return; 809 810 if (debug_level >= DEBUG_LEVEL_INFO) 811 printk("%s(%d):%s close() entry, count=%d\n", 812 __FILE__,__LINE__, info->device_name, info->port.count); 813 814 if (tty_port_close_start(&info->port, tty, filp) == 0) 815 goto cleanup; 816 817 mutex_lock(&info->port.mutex); 818 if (info->port.flags & ASYNC_INITIALIZED) 819 wait_until_sent(tty, info->timeout); 820 821 flush_buffer(tty); 822 tty_ldisc_flush(tty); 823 shutdown(info); 824 mutex_unlock(&info->port.mutex); 825 826 tty_port_close_end(&info->port, tty); 827 info->port.tty = NULL; 828cleanup: 829 if (debug_level >= DEBUG_LEVEL_INFO) 830 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__, 831 tty->driver->name, info->port.count); 832} 833 834/* Called by tty_hangup() when a hangup is signaled. 835 * This is the same as closing all open descriptors for the port. 836 */ 837static void hangup(struct tty_struct *tty) 838{ 839 SLMP_INFO *info = tty->driver_data; 840 unsigned long flags; 841 842 if (debug_level >= DEBUG_LEVEL_INFO) 843 printk("%s(%d):%s hangup()\n", 844 __FILE__,__LINE__, info->device_name ); 845 846 if (sanity_check(info, tty->name, "hangup")) 847 return; 848 849 mutex_lock(&info->port.mutex); 850 flush_buffer(tty); 851 shutdown(info); 852 853 spin_lock_irqsave(&info->port.lock, flags); 854 info->port.count = 0; 855 info->port.flags &= ~ASYNC_NORMAL_ACTIVE; 856 info->port.tty = NULL; 857 spin_unlock_irqrestore(&info->port.lock, flags); 858 mutex_unlock(&info->port.mutex); 859 860 wake_up_interruptible(&info->port.open_wait); 861} 862 863/* Set new termios settings 864 */ 865static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) 866{ 867 SLMP_INFO *info = tty->driver_data; 868 unsigned long flags; 869 870 if (debug_level >= DEBUG_LEVEL_INFO) 871 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__, 872 tty->driver->name ); 873 874 change_params(info); 875 876 /* Handle transition to B0 status */ 877 if (old_termios->c_cflag & CBAUD && 878 !(tty->termios->c_cflag & CBAUD)) { 879 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); 880 spin_lock_irqsave(&info->lock,flags); 881 set_signals(info); 882 spin_unlock_irqrestore(&info->lock,flags); 883 } 884 885 /* Handle transition away from B0 status */ 886 if (!(old_termios->c_cflag & CBAUD) && 887 tty->termios->c_cflag & CBAUD) { 888 info->serial_signals |= SerialSignal_DTR; 889 if (!(tty->termios->c_cflag & CRTSCTS) || 890 !test_bit(TTY_THROTTLED, &tty->flags)) { 891 info->serial_signals |= SerialSignal_RTS; 892 } 893 spin_lock_irqsave(&info->lock,flags); 894 set_signals(info); 895 spin_unlock_irqrestore(&info->lock,flags); 896 } 897 898 /* Handle turning off CRTSCTS */ 899 if (old_termios->c_cflag & CRTSCTS && 900 !(tty->termios->c_cflag & CRTSCTS)) { 901 tty->hw_stopped = 0; 902 tx_release(tty); 903 } 904} 905 906/* Send a block of data 907 * 908 * Arguments: 909 * 910 * tty pointer to tty information structure 911 * buf pointer to buffer containing send data 912 * count size of send data in bytes 913 * 914 * Return Value: number of characters written 915 */ 916static int write(struct tty_struct *tty, 917 const unsigned char *buf, int count) 918{ 919 int c, ret = 0; 920 SLMP_INFO *info = tty->driver_data; 921 unsigned long flags; 922 923 if (debug_level >= DEBUG_LEVEL_INFO) 924 printk("%s(%d):%s write() count=%d\n", 925 __FILE__,__LINE__,info->device_name,count); 926 927 if (sanity_check(info, tty->name, "write")) 928 goto cleanup; 929 930 if (!info->tx_buf) 931 goto cleanup; 932 933 if (info->params.mode == MGSL_MODE_HDLC) { 934 if (count > info->max_frame_size) { 935 ret = -EIO; 936 goto cleanup; 937 } 938 if (info->tx_active) 939 goto cleanup; 940 if (info->tx_count) { 941 /* send accumulated data from send_char() calls */ 942 /* as frame and wait before accepting more data. */ 943 tx_load_dma_buffer(info, info->tx_buf, info->tx_count); 944 goto start; 945 } 946 ret = info->tx_count = count; 947 tx_load_dma_buffer(info, buf, count); 948 goto start; 949 } 950 951 for (;;) { 952 c = min_t(int, count, 953 min(info->max_frame_size - info->tx_count - 1, 954 info->max_frame_size - info->tx_put)); 955 if (c <= 0) 956 break; 957 958 memcpy(info->tx_buf + info->tx_put, buf, c); 959 960 spin_lock_irqsave(&info->lock,flags); 961 info->tx_put += c; 962 if (info->tx_put >= info->max_frame_size) 963 info->tx_put -= info->max_frame_size; 964 info->tx_count += c; 965 spin_unlock_irqrestore(&info->lock,flags); 966 967 buf += c; 968 count -= c; 969 ret += c; 970 } 971 972 if (info->params.mode == MGSL_MODE_HDLC) { 973 if (count) { 974 ret = info->tx_count = 0; 975 goto cleanup; 976 } 977 tx_load_dma_buffer(info, info->tx_buf, info->tx_count); 978 } 979start: 980 if (info->tx_count && !tty->stopped && !tty->hw_stopped) { 981 spin_lock_irqsave(&info->lock,flags); 982 if (!info->tx_active) 983 tx_start(info); 984 spin_unlock_irqrestore(&info->lock,flags); 985 } 986 987cleanup: 988 if (debug_level >= DEBUG_LEVEL_INFO) 989 printk( "%s(%d):%s write() returning=%d\n", 990 __FILE__,__LINE__,info->device_name,ret); 991 return ret; 992} 993 994/* Add a character to the transmit buffer. 995 */ 996static int put_char(struct tty_struct *tty, unsigned char ch) 997{ 998 SLMP_INFO *info = tty->driver_data; 999 unsigned long flags; 1000 int ret = 0; 1001 1002 if ( debug_level >= DEBUG_LEVEL_INFO ) { 1003 printk( "%s(%d):%s put_char(%d)\n", 1004 __FILE__,__LINE__,info->device_name,ch); 1005 } 1006 1007 if (sanity_check(info, tty->name, "put_char")) 1008 return 0; 1009 1010 if (!info->tx_buf) 1011 return 0; 1012 1013 spin_lock_irqsave(&info->lock,flags); 1014 1015 if ( (info->params.mode != MGSL_MODE_HDLC) || 1016 !info->tx_active ) { 1017 1018 if (info->tx_count < info->max_frame_size - 1) { 1019 info->tx_buf[info->tx_put++] = ch; 1020 if (info->tx_put >= info->max_frame_size) 1021 info->tx_put -= info->max_frame_size; 1022 info->tx_count++; 1023 ret = 1; 1024 } 1025 } 1026 1027 spin_unlock_irqrestore(&info->lock,flags); 1028 return ret; 1029} 1030 1031/* Send a high-priority XON/XOFF character 1032 */ 1033static void send_xchar(struct tty_struct *tty, char ch) 1034{ 1035 SLMP_INFO *info = tty->driver_data; 1036 unsigned long flags; 1037 1038 if (debug_level >= DEBUG_LEVEL_INFO) 1039 printk("%s(%d):%s send_xchar(%d)\n", 1040 __FILE__,__LINE__, info->device_name, ch ); 1041 1042 if (sanity_check(info, tty->name, "send_xchar")) 1043 return; 1044 1045 info->x_char = ch; 1046 if (ch) { 1047 /* Make sure transmit interrupts are on */ 1048 spin_lock_irqsave(&info->lock,flags); 1049 if (!info->tx_enabled) 1050 tx_start(info); 1051 spin_unlock_irqrestore(&info->lock,flags); 1052 } 1053} 1054 1055/* Wait until the transmitter is empty. 1056 */ 1057static void wait_until_sent(struct tty_struct *tty, int timeout) 1058{ 1059 SLMP_INFO * info = tty->driver_data; 1060 unsigned long orig_jiffies, char_time; 1061 1062 if (!info ) 1063 return; 1064 1065 if (debug_level >= DEBUG_LEVEL_INFO) 1066 printk("%s(%d):%s wait_until_sent() entry\n", 1067 __FILE__,__LINE__, info->device_name ); 1068 1069 if (sanity_check(info, tty->name, "wait_until_sent")) 1070 return; 1071 1072 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags)) 1073 goto exit; 1074 1075 orig_jiffies = jiffies; 1076 1077 /* Set check interval to 1/5 of estimated time to 1078 * send a character, and make it at least 1. The check 1079 * interval should also be less than the timeout. 1080 * Note: use tight timings here to satisfy the NIST-PCTS. 1081 */ 1082 1083 if ( info->params.data_rate ) { 1084 char_time = info->timeout/(32 * 5); 1085 if (!char_time) 1086 char_time++; 1087 } else 1088 char_time = 1; 1089 1090 if (timeout) 1091 char_time = min_t(unsigned long, char_time, timeout); 1092 1093 if ( info->params.mode == MGSL_MODE_HDLC ) { 1094 while (info->tx_active) { 1095 msleep_interruptible(jiffies_to_msecs(char_time)); 1096 if (signal_pending(current)) 1097 break; 1098 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 1099 break; 1100 } 1101 } else { 1102 /* 1103 * TODO: determine if there is something similar to USC16C32 1104 * TXSTATUS_ALL_SENT status 1105 */ 1106 while ( info->tx_active && info->tx_enabled) { 1107 msleep_interruptible(jiffies_to_msecs(char_time)); 1108 if (signal_pending(current)) 1109 break; 1110 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 1111 break; 1112 } 1113 } 1114 1115exit: 1116 if (debug_level >= DEBUG_LEVEL_INFO) 1117 printk("%s(%d):%s wait_until_sent() exit\n", 1118 __FILE__,__LINE__, info->device_name ); 1119} 1120 1121/* Return the count of free bytes in transmit buffer 1122 */ 1123static int write_room(struct tty_struct *tty) 1124{ 1125 SLMP_INFO *info = tty->driver_data; 1126 int ret; 1127 1128 if (sanity_check(info, tty->name, "write_room")) 1129 return 0; 1130 1131 if (info->params.mode == MGSL_MODE_HDLC) { 1132 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; 1133 } else { 1134 ret = info->max_frame_size - info->tx_count - 1; 1135 if (ret < 0) 1136 ret = 0; 1137 } 1138 1139 if (debug_level >= DEBUG_LEVEL_INFO) 1140 printk("%s(%d):%s write_room()=%d\n", 1141 __FILE__, __LINE__, info->device_name, ret); 1142 1143 return ret; 1144} 1145 1146/* enable transmitter and send remaining buffered characters 1147 */ 1148static void flush_chars(struct tty_struct *tty) 1149{ 1150 SLMP_INFO *info = tty->driver_data; 1151 unsigned long flags; 1152 1153 if ( debug_level >= DEBUG_LEVEL_INFO ) 1154 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n", 1155 __FILE__,__LINE__,info->device_name,info->tx_count); 1156 1157 if (sanity_check(info, tty->name, "flush_chars")) 1158 return; 1159 1160 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped || 1161 !info->tx_buf) 1162 return; 1163 1164 if ( debug_level >= DEBUG_LEVEL_INFO ) 1165 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n", 1166 __FILE__,__LINE__,info->device_name ); 1167 1168 spin_lock_irqsave(&info->lock,flags); 1169 1170 if (!info->tx_active) { 1171 if ( (info->params.mode == MGSL_MODE_HDLC) && 1172 info->tx_count ) { 1173 /* operating in synchronous (frame oriented) mode */ 1174 /* copy data from circular tx_buf to */ 1175 /* transmit DMA buffer. */ 1176 tx_load_dma_buffer(info, 1177 info->tx_buf,info->tx_count); 1178 } 1179 tx_start(info); 1180 } 1181 1182 spin_unlock_irqrestore(&info->lock,flags); 1183} 1184 1185/* Discard all data in the send buffer 1186 */ 1187static void flush_buffer(struct tty_struct *tty) 1188{ 1189 SLMP_INFO *info = tty->driver_data; 1190 unsigned long flags; 1191 1192 if (debug_level >= DEBUG_LEVEL_INFO) 1193 printk("%s(%d):%s flush_buffer() entry\n", 1194 __FILE__,__LINE__, info->device_name ); 1195 1196 if (sanity_check(info, tty->name, "flush_buffer")) 1197 return; 1198 1199 spin_lock_irqsave(&info->lock,flags); 1200 info->tx_count = info->tx_put = info->tx_get = 0; 1201 del_timer(&info->tx_timer); 1202 spin_unlock_irqrestore(&info->lock,flags); 1203 1204 tty_wakeup(tty); 1205} 1206 1207/* throttle (stop) transmitter 1208 */ 1209static void tx_hold(struct tty_struct *tty) 1210{ 1211 SLMP_INFO *info = tty->driver_data; 1212 unsigned long flags; 1213 1214 if (sanity_check(info, tty->name, "tx_hold")) 1215 return; 1216 1217 if ( debug_level >= DEBUG_LEVEL_INFO ) 1218 printk("%s(%d):%s tx_hold()\n", 1219 __FILE__,__LINE__,info->device_name); 1220 1221 spin_lock_irqsave(&info->lock,flags); 1222 if (info->tx_enabled) 1223 tx_stop(info); 1224 spin_unlock_irqrestore(&info->lock,flags); 1225} 1226 1227/* release (start) transmitter 1228 */ 1229static void tx_release(struct tty_struct *tty) 1230{ 1231 SLMP_INFO *info = tty->driver_data; 1232 unsigned long flags; 1233 1234 if (sanity_check(info, tty->name, "tx_release")) 1235 return; 1236 1237 if ( debug_level >= DEBUG_LEVEL_INFO ) 1238 printk("%s(%d):%s tx_release()\n", 1239 __FILE__,__LINE__,info->device_name); 1240 1241 spin_lock_irqsave(&info->lock,flags); 1242 if (!info->tx_enabled) 1243 tx_start(info); 1244 spin_unlock_irqrestore(&info->lock,flags); 1245} 1246 1247/* Service an IOCTL request 1248 * 1249 * Arguments: 1250 * 1251 * tty pointer to tty instance data 1252 * file pointer to associated file object for device 1253 * cmd IOCTL command code 1254 * arg command argument/context 1255 * 1256 * Return Value: 0 if success, otherwise error code 1257 */ 1258static int ioctl(struct tty_struct *tty, struct file *file, 1259 unsigned int cmd, unsigned long arg) 1260{ 1261 SLMP_INFO *info = tty->driver_data; 1262 int error; 1263 struct mgsl_icount cnow; /* kernel counter temps */ 1264 struct serial_icounter_struct __user *p_cuser; /* user space */ 1265 unsigned long flags; 1266 void __user *argp = (void __user *)arg; 1267 1268 if (debug_level >= DEBUG_LEVEL_INFO) 1269 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__, 1270 info->device_name, cmd ); 1271 1272 if (sanity_check(info, tty->name, "ioctl")) 1273 return -ENODEV; 1274 1275 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && 1276 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { 1277 if (tty->flags & (1 << TTY_IO_ERROR)) 1278 return -EIO; 1279 } 1280 1281 switch (cmd) { 1282 case MGSL_IOCGPARAMS: 1283 return get_params(info, argp); 1284 case MGSL_IOCSPARAMS: 1285 return set_params(info, argp); 1286 case MGSL_IOCGTXIDLE: 1287 return get_txidle(info, argp); 1288 case MGSL_IOCSTXIDLE: 1289 return set_txidle(info, (int)arg); 1290 case MGSL_IOCTXENABLE: 1291 return tx_enable(info, (int)arg); 1292 case MGSL_IOCRXENABLE: 1293 return rx_enable(info, (int)arg); 1294 case MGSL_IOCTXABORT: 1295 return tx_abort(info); 1296 case MGSL_IOCGSTATS: 1297 return get_stats(info, argp); 1298 case MGSL_IOCWAITEVENT: 1299 return wait_mgsl_event(info, argp); 1300 case MGSL_IOCLOOPTXDONE: 1301 return 0; // TODO: Not supported, need to document 1302 /* Wait for modem input (DCD,RI,DSR,CTS) change 1303 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS) 1304 */ 1305 case TIOCMIWAIT: 1306 return modem_input_wait(info,(int)arg); 1307 1308 /* 1309 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) 1310 * Return: write counters to the user passed counter struct 1311 * NB: both 1->0 and 0->1 transitions are counted except for 1312 * RI where only 0->1 is counted. 1313 */ 1314 case TIOCGICOUNT: 1315 spin_lock_irqsave(&info->lock,flags); 1316 cnow = info->icount; 1317 spin_unlock_irqrestore(&info->lock,flags); 1318 p_cuser = argp; 1319 PUT_USER(error,cnow.cts, &p_cuser->cts); 1320 if (error) return error; 1321 PUT_USER(error,cnow.dsr, &p_cuser->dsr); 1322 if (error) return error; 1323 PUT_USER(error,cnow.rng, &p_cuser->rng); 1324 if (error) return error; 1325 PUT_USER(error,cnow.dcd, &p_cuser->dcd); 1326 if (error) return error; 1327 PUT_USER(error,cnow.rx, &p_cuser->rx); 1328 if (error) return error; 1329 PUT_USER(error,cnow.tx, &p_cuser->tx); 1330 if (error) return error; 1331 PUT_USER(error,cnow.frame, &p_cuser->frame); 1332 if (error) return error; 1333 PUT_USER(error,cnow.overrun, &p_cuser->overrun); 1334 if (error) return error; 1335 PUT_USER(error,cnow.parity, &p_cuser->parity); 1336 if (error) return error; 1337 PUT_USER(error,cnow.brk, &p_cuser->brk); 1338 if (error) return error; 1339 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun); 1340 if (error) return error; 1341 return 0; 1342 default: 1343 return -ENOIOCTLCMD; 1344 } 1345 return 0; 1346} 1347 1348/* 1349 * /proc fs routines.... 1350 */ 1351 1352static inline void line_info(struct seq_file *m, SLMP_INFO *info) 1353{ 1354 char stat_buf[30]; 1355 unsigned long flags; 1356 1357 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n" 1358 "\tIRQ=%d MaxFrameSize=%u\n", 1359 info->device_name, 1360 info->phys_sca_base, 1361 info->phys_memory_base, 1362 info->phys_statctrl_base, 1363 info->phys_lcr_base, 1364 info->irq_level, 1365 info->max_frame_size ); 1366 1367 /* output current serial signal states */ 1368 spin_lock_irqsave(&info->lock,flags); 1369 get_signals(info); 1370 spin_unlock_irqrestore(&info->lock,flags); 1371 1372 stat_buf[0] = 0; 1373 stat_buf[1] = 0; 1374 if (info->serial_signals & SerialSignal_RTS) 1375 strcat(stat_buf, "|RTS"); 1376 if (info->serial_signals & SerialSignal_CTS) 1377 strcat(stat_buf, "|CTS"); 1378 if (info->serial_signals & SerialSignal_DTR) 1379 strcat(stat_buf, "|DTR"); 1380 if (info->serial_signals & SerialSignal_DSR) 1381 strcat(stat_buf, "|DSR"); 1382 if (info->serial_signals & SerialSignal_DCD) 1383 strcat(stat_buf, "|CD"); 1384 if (info->serial_signals & SerialSignal_RI) 1385 strcat(stat_buf, "|RI"); 1386 1387 if (info->params.mode == MGSL_MODE_HDLC) { 1388 seq_printf(m, "\tHDLC txok:%d rxok:%d", 1389 info->icount.txok, info->icount.rxok); 1390 if (info->icount.txunder) 1391 seq_printf(m, " txunder:%d", info->icount.txunder); 1392 if (info->icount.txabort) 1393 seq_printf(m, " txabort:%d", info->icount.txabort); 1394 if (info->icount.rxshort) 1395 seq_printf(m, " rxshort:%d", info->icount.rxshort); 1396 if (info->icount.rxlong) 1397 seq_printf(m, " rxlong:%d", info->icount.rxlong); 1398 if (info->icount.rxover) 1399 seq_printf(m, " rxover:%d", info->icount.rxover); 1400 if (info->icount.rxcrc) 1401 seq_printf(m, " rxlong:%d", info->icount.rxcrc); 1402 } else { 1403 seq_printf(m, "\tASYNC tx:%d rx:%d", 1404 info->icount.tx, info->icount.rx); 1405 if (info->icount.frame) 1406 seq_printf(m, " fe:%d", info->icount.frame); 1407 if (info->icount.parity) 1408 seq_printf(m, " pe:%d", info->icount.parity); 1409 if (info->icount.brk) 1410 seq_printf(m, " brk:%d", info->icount.brk); 1411 if (info->icount.overrun) 1412 seq_printf(m, " oe:%d", info->icount.overrun); 1413 } 1414 1415 /* Append serial signal status to end */ 1416 seq_printf(m, " %s\n", stat_buf+1); 1417 1418 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", 1419 info->tx_active,info->bh_requested,info->bh_running, 1420 info->pending_bh); 1421} 1422 1423/* Called to print information about devices 1424 */ 1425static int synclinkmp_proc_show(struct seq_file *m, void *v) 1426{ 1427 SLMP_INFO *info; 1428 1429 seq_printf(m, "synclinkmp driver:%s\n", driver_version); 1430 1431 info = synclinkmp_device_list; 1432 while( info ) { 1433 line_info(m, info); 1434 info = info->next_device; 1435 } 1436 return 0; 1437} 1438 1439static int synclinkmp_proc_open(struct inode *inode, struct file *file) 1440{ 1441 return single_open(file, synclinkmp_proc_show, NULL); 1442} 1443 1444static const struct file_operations synclinkmp_proc_fops = { 1445 .owner = THIS_MODULE, 1446 .open = synclinkmp_proc_open, 1447 .read = seq_read, 1448 .llseek = seq_lseek, 1449 .release = single_release, 1450}; 1451 1452/* Return the count of bytes in transmit buffer 1453 */ 1454static int chars_in_buffer(struct tty_struct *tty) 1455{ 1456 SLMP_INFO *info = tty->driver_data; 1457 1458 if (sanity_check(info, tty->name, "chars_in_buffer")) 1459 return 0; 1460 1461 if (debug_level >= DEBUG_LEVEL_INFO) 1462 printk("%s(%d):%s chars_in_buffer()=%d\n", 1463 __FILE__, __LINE__, info->device_name, info->tx_count); 1464 1465 return info->tx_count; 1466} 1467 1468/* Signal remote device to throttle send data (our receive data) 1469 */ 1470static void throttle(struct tty_struct * tty) 1471{ 1472 SLMP_INFO *info = tty->driver_data; 1473 unsigned long flags; 1474 1475 if (debug_level >= DEBUG_LEVEL_INFO) 1476 printk("%s(%d):%s throttle() entry\n", 1477 __FILE__,__LINE__, info->device_name ); 1478 1479 if (sanity_check(info, tty->name, "throttle")) 1480 return; 1481 1482 if (I_IXOFF(tty)) 1483 send_xchar(tty, STOP_CHAR(tty)); 1484 1485 if (tty->termios->c_cflag & CRTSCTS) { 1486 spin_lock_irqsave(&info->lock,flags); 1487 info->serial_signals &= ~SerialSignal_RTS; 1488 set_signals(info); 1489 spin_unlock_irqrestore(&info->lock,flags); 1490 } 1491} 1492 1493/* Signal remote device to stop throttling send data (our receive data) 1494 */ 1495static void unthrottle(struct tty_struct * tty) 1496{ 1497 SLMP_INFO *info = tty->driver_data; 1498 unsigned long flags; 1499 1500 if (debug_level >= DEBUG_LEVEL_INFO) 1501 printk("%s(%d):%s unthrottle() entry\n", 1502 __FILE__,__LINE__, info->device_name ); 1503 1504 if (sanity_check(info, tty->name, "unthrottle")) 1505 return; 1506 1507 if (I_IXOFF(tty)) { 1508 if (info->x_char) 1509 info->x_char = 0; 1510 else 1511 send_xchar(tty, START_CHAR(tty)); 1512 } 1513 1514 if (tty->termios->c_cflag & CRTSCTS) { 1515 spin_lock_irqsave(&info->lock,flags); 1516 info->serial_signals |= SerialSignal_RTS; 1517 set_signals(info); 1518 spin_unlock_irqrestore(&info->lock,flags); 1519 } 1520} 1521 1522/* set or clear transmit break condition 1523 * break_state -1=set break condition, 0=clear 1524 */ 1525static int set_break(struct tty_struct *tty, int break_state) 1526{ 1527 unsigned char RegValue; 1528 SLMP_INFO * info = tty->driver_data; 1529 unsigned long flags; 1530 1531 if (debug_level >= DEBUG_LEVEL_INFO) 1532 printk("%s(%d):%s set_break(%d)\n", 1533 __FILE__,__LINE__, info->device_name, break_state); 1534 1535 if (sanity_check(info, tty->name, "set_break")) 1536 return -EINVAL; 1537 1538 spin_lock_irqsave(&info->lock,flags); 1539 RegValue = read_reg(info, CTL); 1540 if (break_state == -1) 1541 RegValue |= BIT3; 1542 else 1543 RegValue &= ~BIT3; 1544 write_reg(info, CTL, RegValue); 1545 spin_unlock_irqrestore(&info->lock,flags); 1546 return 0; 1547} 1548 1549#if SYNCLINK_GENERIC_HDLC 1550 1551/** 1552 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) 1553 * set encoding and frame check sequence (FCS) options 1554 * 1555 * dev pointer to network device structure 1556 * encoding serial encoding setting 1557 * parity FCS setting 1558 * 1559 * returns 0 if success, otherwise error code 1560 */ 1561static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, 1562 unsigned short parity) 1563{ 1564 SLMP_INFO *info = dev_to_port(dev); 1565 unsigned char new_encoding; 1566 unsigned short new_crctype; 1567 1568 /* return error if TTY interface open */ 1569 if (info->port.count) 1570 return -EBUSY; 1571 1572 switch (encoding) 1573 { 1574 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; 1575 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; 1576 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; 1577 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; 1578 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; 1579 default: return -EINVAL; 1580 } 1581 1582 switch (parity) 1583 { 1584 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; 1585 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; 1586 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; 1587 default: return -EINVAL; 1588 } 1589 1590 info->params.encoding = new_encoding; 1591 info->params.crc_type = new_crctype; 1592 1593 /* if network interface up, reprogram hardware */ 1594 if (info->netcount) 1595 program_hw(info); 1596 1597 return 0; 1598} 1599 1600/** 1601 * called by generic HDLC layer to send frame 1602 * 1603 * skb socket buffer containing HDLC frame 1604 * dev pointer to network device structure 1605 */ 1606static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, 1607 struct net_device *dev) 1608{ 1609 SLMP_INFO *info = dev_to_port(dev); 1610 unsigned long flags; 1611 1612 if (debug_level >= DEBUG_LEVEL_INFO) 1613 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name); 1614 1615 /* stop sending until this frame completes */ 1616 netif_stop_queue(dev); 1617 1618 /* copy data to device buffers */ 1619 info->tx_count = skb->len; 1620 tx_load_dma_buffer(info, skb->data, skb->len); 1621 1622 /* update network statistics */ 1623 dev->stats.tx_packets++; 1624 dev->stats.tx_bytes += skb->len; 1625 1626 /* done with socket buffer, so free it */ 1627 dev_kfree_skb(skb); 1628 1629 /* save start time for transmit timeout detection */ 1630 dev->trans_start = jiffies; 1631 1632 /* start hardware transmitter if necessary */ 1633 spin_lock_irqsave(&info->lock,flags); 1634 if (!info->tx_active) 1635 tx_start(info); 1636 spin_unlock_irqrestore(&info->lock,flags); 1637 1638 return NETDEV_TX_OK; 1639} 1640 1641/** 1642 * called by network layer when interface enabled 1643 * claim resources and initialize hardware 1644 * 1645 * dev pointer to network device structure 1646 * 1647 * returns 0 if success, otherwise error code 1648 */ 1649static int hdlcdev_open(struct net_device *dev) 1650{ 1651 SLMP_INFO *info = dev_to_port(dev); 1652 int rc; 1653 unsigned long flags; 1654 1655 if (debug_level >= DEBUG_LEVEL_INFO) 1656 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name); 1657 1658 /* generic HDLC layer open processing */ 1659 if ((rc = hdlc_open(dev))) 1660 return rc; 1661 1662 /* arbitrate between network and tty opens */ 1663 spin_lock_irqsave(&info->netlock, flags); 1664 if (info->port.count != 0 || info->netcount != 0) { 1665 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name); 1666 spin_unlock_irqrestore(&info->netlock, flags); 1667 return -EBUSY; 1668 } 1669 info->netcount=1; 1670 spin_unlock_irqrestore(&info->netlock, flags); 1671 1672 /* claim resources and init adapter */ 1673 if ((rc = startup(info)) != 0) { 1674 spin_lock_irqsave(&info->netlock, flags); 1675 info->netcount=0; 1676 spin_unlock_irqrestore(&info->netlock, flags); 1677 return rc; 1678 } 1679 1680 /* assert DTR and RTS, apply hardware settings */ 1681 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; 1682 program_hw(info); 1683 1684 /* enable network layer transmit */ 1685 dev->trans_start = jiffies; 1686 netif_start_queue(dev); 1687 1688 /* inform generic HDLC layer of current DCD status */ 1689 spin_lock_irqsave(&info->lock, flags); 1690 get_signals(info); 1691 spin_unlock_irqrestore(&info->lock, flags); 1692 if (info->serial_signals & SerialSignal_DCD) 1693 netif_carrier_on(dev); 1694 else 1695 netif_carrier_off(dev); 1696 return 0; 1697} 1698 1699/** 1700 * called by network layer when interface is disabled 1701 * shutdown hardware and release resources 1702 * 1703 * dev pointer to network device structure 1704 * 1705 * returns 0 if success, otherwise error code 1706 */ 1707static int hdlcdev_close(struct net_device *dev) 1708{ 1709 SLMP_INFO *info = dev_to_port(dev); 1710 unsigned long flags; 1711 1712 if (debug_level >= DEBUG_LEVEL_INFO) 1713 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name); 1714 1715 netif_stop_queue(dev); 1716 1717 /* shutdown adapter and release resources */ 1718 shutdown(info); 1719 1720 hdlc_close(dev); 1721 1722 spin_lock_irqsave(&info->netlock, flags); 1723 info->netcount=0; 1724 spin_unlock_irqrestore(&info->netlock, flags); 1725 1726 return 0; 1727} 1728 1729/** 1730 * called by network layer to process IOCTL call to network device 1731 * 1732 * dev pointer to network device structure 1733 * ifr pointer to network interface request structure 1734 * cmd IOCTL command code 1735 * 1736 * returns 0 if success, otherwise error code 1737 */ 1738static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1739{ 1740 const size_t size = sizeof(sync_serial_settings); 1741 sync_serial_settings new_line; 1742 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 1743 SLMP_INFO *info = dev_to_port(dev); 1744 unsigned int flags; 1745 1746 if (debug_level >= DEBUG_LEVEL_INFO) 1747 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name); 1748 1749 /* return error if TTY interface open */ 1750 if (info->port.count) 1751 return -EBUSY; 1752 1753 if (cmd != SIOCWANDEV) 1754 return hdlc_ioctl(dev, ifr, cmd); 1755 1756 switch(ifr->ifr_settings.type) { 1757 case IF_GET_IFACE: /* return current sync_serial_settings */ 1758 1759 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 1760 if (ifr->ifr_settings.size < size) { 1761 ifr->ifr_settings.size = size; /* data size wanted */ 1762 return -ENOBUFS; 1763 } 1764 1765 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1766 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1767 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1768 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1769 1770 switch (flags){ 1771 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1772 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1773 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1774 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1775 default: new_line.clock_type = CLOCK_DEFAULT; 1776 } 1777 1778 new_line.clock_rate = info->params.clock_speed; 1779 new_line.loopback = info->params.loopback ? 1:0; 1780 1781 if (copy_to_user(line, &new_line, size)) 1782 return -EFAULT; 1783 return 0; 1784 1785 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ 1786 1787 if(!capable(CAP_NET_ADMIN)) 1788 return -EPERM; 1789 if (copy_from_user(&new_line, line, size)) 1790 return -EFAULT; 1791 1792 switch (new_line.clock_type) 1793 { 1794 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; 1795 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; 1796 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; 1797 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; 1798 case CLOCK_DEFAULT: flags = info->params.flags & 1799 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1800 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1801 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1802 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; 1803 default: return -EINVAL; 1804 } 1805 1806 if (new_line.loopback != 0 && new_line.loopback != 1) 1807 return -EINVAL; 1808 1809 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1810 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1811 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1812 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1813 info->params.flags |= flags; 1814 1815 info->params.loopback = new_line.loopback; 1816 1817 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) 1818 info->params.clock_speed = new_line.clock_rate; 1819 else 1820 info->params.clock_speed = 0; 1821 1822 /* if network interface up, reprogram hardware */ 1823 if (info->netcount) 1824 program_hw(info); 1825 return 0; 1826 1827 default: 1828 return hdlc_ioctl(dev, ifr, cmd); 1829 } 1830} 1831 1832/** 1833 * called by network layer when transmit timeout is detected 1834 * 1835 * dev pointer to network device structure 1836 */ 1837static void hdlcdev_tx_timeout(struct net_device *dev) 1838{ 1839 SLMP_INFO *info = dev_to_port(dev); 1840 unsigned long flags; 1841 1842 if (debug_level >= DEBUG_LEVEL_INFO) 1843 printk("hdlcdev_tx_timeout(%s)\n",dev->name); 1844 1845 dev->stats.tx_errors++; 1846 dev->stats.tx_aborted_errors++; 1847 1848 spin_lock_irqsave(&info->lock,flags); 1849 tx_stop(info); 1850 spin_unlock_irqrestore(&info->lock,flags); 1851 1852 netif_wake_queue(dev); 1853} 1854 1855/** 1856 * called by device driver when transmit completes 1857 * reenable network layer transmit if stopped 1858 * 1859 * info pointer to device instance information 1860 */ 1861static void hdlcdev_tx_done(SLMP_INFO *info) 1862{ 1863 if (netif_queue_stopped(info->netdev)) 1864 netif_wake_queue(info->netdev); 1865} 1866 1867/** 1868 * called by device driver when frame received 1869 * pass frame to network layer 1870 * 1871 * info pointer to device instance information 1872 * buf pointer to buffer contianing frame data 1873 * size count of data bytes in buf 1874 */ 1875static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size) 1876{ 1877 struct sk_buff *skb = dev_alloc_skb(size); 1878 struct net_device *dev = info->netdev; 1879 1880 if (debug_level >= DEBUG_LEVEL_INFO) 1881 printk("hdlcdev_rx(%s)\n",dev->name); 1882 1883 if (skb == NULL) { 1884 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", 1885 dev->name); 1886 dev->stats.rx_dropped++; 1887 return; 1888 } 1889 1890 memcpy(skb_put(skb, size), buf, size); 1891 1892 skb->protocol = hdlc_type_trans(skb, dev); 1893 1894 dev->stats.rx_packets++; 1895 dev->stats.rx_bytes += size; 1896 1897 netif_rx(skb); 1898} 1899 1900static const struct net_device_ops hdlcdev_ops = { 1901 .ndo_open = hdlcdev_open, 1902 .ndo_stop = hdlcdev_close, 1903 .ndo_change_mtu = hdlc_change_mtu, 1904 .ndo_start_xmit = hdlc_start_xmit, 1905 .ndo_do_ioctl = hdlcdev_ioctl, 1906 .ndo_tx_timeout = hdlcdev_tx_timeout, 1907}; 1908 1909/** 1910 * called by device driver when adding device instance 1911 * do generic HDLC initialization 1912 * 1913 * info pointer to device instance information 1914 * 1915 * returns 0 if success, otherwise error code 1916 */ 1917static int hdlcdev_init(SLMP_INFO *info) 1918{ 1919 int rc; 1920 struct net_device *dev; 1921 hdlc_device *hdlc; 1922 1923 /* allocate and initialize network and HDLC layer objects */ 1924 1925 if (!(dev = alloc_hdlcdev(info))) { 1926 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__); 1927 return -ENOMEM; 1928 } 1929 1930 /* for network layer reporting purposes only */ 1931 dev->mem_start = info->phys_sca_base; 1932 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1; 1933 dev->irq = info->irq_level; 1934 1935 /* network layer callbacks and settings */ 1936 dev->netdev_ops = &hdlcdev_ops; 1937 dev->watchdog_timeo = 10 * HZ; 1938 dev->tx_queue_len = 50; 1939 1940 /* generic HDLC layer callbacks and settings */ 1941 hdlc = dev_to_hdlc(dev); 1942 hdlc->attach = hdlcdev_attach; 1943 hdlc->xmit = hdlcdev_xmit; 1944 1945 /* register objects with HDLC layer */ 1946 if ((rc = register_hdlc_device(dev))) { 1947 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); 1948 free_netdev(dev); 1949 return rc; 1950 } 1951 1952 info->netdev = dev; 1953 return 0; 1954} 1955 1956/** 1957 * called by device driver when removing device instance 1958 * do generic HDLC cleanup 1959 * 1960 * info pointer to device instance information 1961 */ 1962static void hdlcdev_exit(SLMP_INFO *info) 1963{ 1964 unregister_hdlc_device(info->netdev); 1965 free_netdev(info->netdev); 1966 info->netdev = NULL; 1967} 1968 1969#endif /* CONFIG_HDLC */ 1970 1971 1972/* Return next bottom half action to perform. 1973 * Return Value: BH action code or 0 if nothing to do. 1974 */ 1975static int bh_action(SLMP_INFO *info) 1976{ 1977 unsigned long flags; 1978 int rc = 0; 1979 1980 spin_lock_irqsave(&info->lock,flags); 1981 1982 if (info->pending_bh & BH_RECEIVE) { 1983 info->pending_bh &= ~BH_RECEIVE; 1984 rc = BH_RECEIVE; 1985 } else if (info->pending_bh & BH_TRANSMIT) { 1986 info->pending_bh &= ~BH_TRANSMIT; 1987 rc = BH_TRANSMIT; 1988 } else if (info->pending_bh & BH_STATUS) { 1989 info->pending_bh &= ~BH_STATUS; 1990 rc = BH_STATUS; 1991 } 1992 1993 if (!rc) { 1994 /* Mark BH routine as complete */ 1995 info->bh_running = false; 1996 info->bh_requested = false; 1997 } 1998 1999 spin_unlock_irqrestore(&info->lock,flags); 2000 2001 return rc; 2002} 2003 2004/* Perform bottom half processing of work items queued by ISR. 2005 */ 2006static void bh_handler(struct work_struct *work) 2007{ 2008 SLMP_INFO *info = container_of(work, SLMP_INFO, task); 2009 int action; 2010 2011 if (!info) 2012 return; 2013 2014 if ( debug_level >= DEBUG_LEVEL_BH ) 2015 printk( "%s(%d):%s bh_handler() entry\n", 2016 __FILE__,__LINE__,info->device_name); 2017 2018 info->bh_running = true; 2019 2020 while((action = bh_action(info)) != 0) { 2021 2022 /* Process work item */ 2023 if ( debug_level >= DEBUG_LEVEL_BH ) 2024 printk( "%s(%d):%s bh_handler() work item action=%d\n", 2025 __FILE__,__LINE__,info->device_name, action); 2026 2027 switch (action) { 2028 2029 case BH_RECEIVE: 2030 bh_receive(info); 2031 break; 2032 case BH_TRANSMIT: 2033 bh_transmit(info); 2034 break; 2035 case BH_STATUS: 2036 bh_status(info); 2037 break; 2038 default: 2039 /* unknown work item ID */ 2040 printk("%s(%d):%s Unknown work item ID=%08X!\n", 2041 __FILE__,__LINE__,info->device_name,action); 2042 break; 2043 } 2044 } 2045 2046 if ( debug_level >= DEBUG_LEVEL_BH ) 2047 printk( "%s(%d):%s bh_handler() exit\n", 2048 __FILE__,__LINE__,info->device_name); 2049} 2050 2051static void bh_receive(SLMP_INFO *info) 2052{ 2053 if ( debug_level >= DEBUG_LEVEL_BH ) 2054 printk( "%s(%d):%s bh_receive()\n", 2055 __FILE__,__LINE__,info->device_name); 2056 2057 while( rx_get_frame(info) ); 2058} 2059 2060static void bh_transmit(SLMP_INFO *info) 2061{ 2062 struct tty_struct *tty = info->port.tty; 2063 2064 if ( debug_level >= DEBUG_LEVEL_BH ) 2065 printk( "%s(%d):%s bh_transmit() entry\n", 2066 __FILE__,__LINE__,info->device_name); 2067 2068 if (tty) 2069 tty_wakeup(tty); 2070} 2071 2072static void bh_status(SLMP_INFO *info) 2073{ 2074 if ( debug_level >= DEBUG_LEVEL_BH ) 2075 printk( "%s(%d):%s bh_status() entry\n", 2076 __FILE__,__LINE__,info->device_name); 2077 2078 info->ri_chkcount = 0; 2079 info->dsr_chkcount = 0; 2080 info->dcd_chkcount = 0; 2081 info->cts_chkcount = 0; 2082} 2083 2084static void isr_timer(SLMP_INFO * info) 2085{ 2086 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; 2087 2088 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */ 2089 write_reg(info, IER2, 0); 2090 2091 /* TMCS, Timer Control/Status Register 2092 * 2093 * 07 CMF, Compare match flag (read only) 1=match 2094 * 06 ECMI, CMF Interrupt Enable: 0=disabled 2095 * 05 Reserved, must be 0 2096 * 04 TME, Timer Enable 2097 * 03..00 Reserved, must be 0 2098 * 2099 * 0000 0000 2100 */ 2101 write_reg(info, (unsigned char)(timer + TMCS), 0); 2102 2103 info->irq_occurred = true; 2104 2105 if ( debug_level >= DEBUG_LEVEL_ISR ) 2106 printk("%s(%d):%s isr_timer()\n", 2107 __FILE__,__LINE__,info->device_name); 2108} 2109 2110static void isr_rxint(SLMP_INFO * info) 2111{ 2112 struct tty_struct *tty = info->port.tty; 2113 struct mgsl_icount *icount = &info->icount; 2114 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD); 2115 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN; 2116 2117 /* clear status bits */ 2118 if (status) 2119 write_reg(info, SR1, status); 2120 2121 if (status2) 2122 write_reg(info, SR2, status2); 2123 2124 if ( debug_level >= DEBUG_LEVEL_ISR ) 2125 printk("%s(%d):%s isr_rxint status=%02X %02x\n", 2126 __FILE__,__LINE__,info->device_name,status,status2); 2127 2128 if (info->params.mode == MGSL_MODE_ASYNC) { 2129 if (status & BRKD) { 2130 icount->brk++; 2131 2132 /* process break detection if tty control 2133 * is not set to ignore it 2134 */ 2135 if ( tty ) { 2136 if (!(status & info->ignore_status_mask1)) { 2137 if (info->read_status_mask1 & BRKD) { 2138 tty_insert_flip_char(tty, 0, TTY_BREAK); 2139 if (info->port.flags & ASYNC_SAK) 2140 do_SAK(tty); 2141 } 2142 } 2143 } 2144 } 2145 } 2146 else { 2147 if (status & (FLGD|IDLD)) { 2148 if (status & FLGD) 2149 info->icount.exithunt++; 2150 else if (status & IDLD) 2151 info->icount.rxidle++; 2152 wake_up_interruptible(&info->event_wait_q); 2153 } 2154 } 2155 2156 if (status & CDCD) { 2157 /* simulate a common modem status change interrupt 2158 * for our handler 2159 */ 2160 get_signals( info ); 2161 isr_io_pin(info, 2162 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD)); 2163 } 2164} 2165 2166/* 2167 * handle async rx data interrupts 2168 */ 2169static void isr_rxrdy(SLMP_INFO * info) 2170{ 2171 u16 status; 2172 unsigned char DataByte; 2173 struct tty_struct *tty = info->port.tty; 2174 struct mgsl_icount *icount = &info->icount; 2175 2176 if ( debug_level >= DEBUG_LEVEL_ISR ) 2177 printk("%s(%d):%s isr_rxrdy\n", 2178 __FILE__,__LINE__,info->device_name); 2179 2180 while((status = read_reg(info,CST0)) & BIT0) 2181 { 2182 int flag = 0; 2183 bool over = false; 2184 DataByte = read_reg(info,TRB); 2185 2186 icount->rx++; 2187 2188 if ( status & (PE + FRME + OVRN) ) { 2189 printk("%s(%d):%s rxerr=%04X\n", 2190 __FILE__,__LINE__,info->device_name,status); 2191 2192 /* update error statistics */ 2193 if (status & PE) 2194 icount->parity++; 2195 else if (status & FRME) 2196 icount->frame++; 2197 else if (status & OVRN) 2198 icount->overrun++; 2199 2200 /* discard char if tty control flags say so */ 2201 if (status & info->ignore_status_mask2) 2202 continue; 2203 2204 status &= info->read_status_mask2; 2205 2206 if ( tty ) { 2207 if (status & PE) 2208 flag = TTY_PARITY; 2209 else if (status & FRME) 2210 flag = TTY_FRAME; 2211 if (status & OVRN) { 2212 /* Overrun is special, since it's 2213 * reported immediately, and doesn't 2214 * affect the current character 2215 */ 2216 over = true; 2217 } 2218 } 2219 } /* end of if (error) */ 2220 2221 if ( tty ) { 2222 tty_insert_flip_char(tty, DataByte, flag); 2223 if (over) 2224 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 2225 } 2226 } 2227 2228 if ( debug_level >= DEBUG_LEVEL_ISR ) { 2229 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n", 2230 __FILE__,__LINE__,info->device_name, 2231 icount->rx,icount->brk,icount->parity, 2232 icount->frame,icount->overrun); 2233 } 2234 2235 if ( tty ) 2236 tty_flip_buffer_push(tty); 2237} 2238 2239static void isr_txeom(SLMP_INFO * info, unsigned char status) 2240{ 2241 if ( debug_level >= DEBUG_LEVEL_ISR ) 2242 printk("%s(%d):%s isr_txeom status=%02x\n", 2243 __FILE__,__LINE__,info->device_name,status); 2244 2245 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ 2246 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ 2247 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 2248 2249 if (status & UDRN) { 2250 write_reg(info, CMD, TXRESET); 2251 write_reg(info, CMD, TXENABLE); 2252 } else 2253 write_reg(info, CMD, TXBUFCLR); 2254 2255 /* disable and clear tx interrupts */ 2256 info->ie0_value &= ~TXRDYE; 2257 info->ie1_value &= ~(IDLE + UDRN); 2258 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); 2259 write_reg(info, SR1, (unsigned char)(UDRN + IDLE)); 2260 2261 if ( info->tx_active ) { 2262 if (info->params.mode != MGSL_MODE_ASYNC) { 2263 if (status & UDRN) 2264 info->icount.txunder++; 2265 else if (status & IDLE) 2266 info->icount.txok++; 2267 } 2268 2269 info->tx_active = false; 2270 info->tx_count = info->tx_put = info->tx_get = 0; 2271 2272 del_timer(&info->tx_timer); 2273 2274 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) { 2275 info->serial_signals &= ~SerialSignal_RTS; 2276 info->drop_rts_on_tx_done = false; 2277 set_signals(info); 2278 } 2279 2280#if SYNCLINK_GENERIC_HDLC 2281 if (info->netcount) 2282 hdlcdev_tx_done(info); 2283 else 2284#endif 2285 { 2286 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2287 tx_stop(info); 2288 return; 2289 } 2290 info->pending_bh |= BH_TRANSMIT; 2291 } 2292 } 2293} 2294 2295 2296/* 2297 * handle tx status interrupts 2298 */ 2299static void isr_txint(SLMP_INFO * info) 2300{ 2301 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS); 2302 2303 /* clear status bits */ 2304 write_reg(info, SR1, status); 2305 2306 if ( debug_level >= DEBUG_LEVEL_ISR ) 2307 printk("%s(%d):%s isr_txint status=%02x\n", 2308 __FILE__,__LINE__,info->device_name,status); 2309 2310 if (status & (UDRN + IDLE)) 2311 isr_txeom(info, status); 2312 2313 if (status & CCTS) { 2314 /* simulate a common modem status change interrupt 2315 * for our handler 2316 */ 2317 get_signals( info ); 2318 isr_io_pin(info, 2319 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS)); 2320 2321 } 2322} 2323 2324/* 2325 * handle async tx data interrupts 2326 */ 2327static void isr_txrdy(SLMP_INFO * info) 2328{ 2329 if ( debug_level >= DEBUG_LEVEL_ISR ) 2330 printk("%s(%d):%s isr_txrdy() tx_count=%d\n", 2331 __FILE__,__LINE__,info->device_name,info->tx_count); 2332 2333 if (info->params.mode != MGSL_MODE_ASYNC) { 2334 /* disable TXRDY IRQ, enable IDLE IRQ */ 2335 info->ie0_value &= ~TXRDYE; 2336 info->ie1_value |= IDLE; 2337 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); 2338 return; 2339 } 2340 2341 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2342 tx_stop(info); 2343 return; 2344 } 2345 2346 if ( info->tx_count ) 2347 tx_load_fifo( info ); 2348 else { 2349 info->tx_active = false; 2350 info->ie0_value &= ~TXRDYE; 2351 write_reg(info, IE0, info->ie0_value); 2352 } 2353 2354 if (info->tx_count < WAKEUP_CHARS) 2355 info->pending_bh |= BH_TRANSMIT; 2356} 2357 2358static void isr_rxdmaok(SLMP_INFO * info) 2359{ 2360 /* BIT7 = EOT (end of transfer) 2361 * BIT6 = EOM (end of message/frame) 2362 */ 2363 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0; 2364 2365 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ 2366 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); 2367 2368 if ( debug_level >= DEBUG_LEVEL_ISR ) 2369 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n", 2370 __FILE__,__LINE__,info->device_name,status); 2371 2372 info->pending_bh |= BH_RECEIVE; 2373} 2374 2375static void isr_rxdmaerror(SLMP_INFO * info) 2376{ 2377 /* BIT5 = BOF (buffer overflow) 2378 * BIT4 = COF (counter overflow) 2379 */ 2380 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30; 2381 2382 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ 2383 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); 2384 2385 if ( debug_level >= DEBUG_LEVEL_ISR ) 2386 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n", 2387 __FILE__,__LINE__,info->device_name,status); 2388 2389 info->rx_overflow = true; 2390 info->pending_bh |= BH_RECEIVE; 2391} 2392 2393static void isr_txdmaok(SLMP_INFO * info) 2394{ 2395 unsigned char status_reg1 = read_reg(info, SR1); 2396 2397 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ 2398 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ 2399 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 2400 2401 if ( debug_level >= DEBUG_LEVEL_ISR ) 2402 printk("%s(%d):%s isr_txdmaok(), status=%02x\n", 2403 __FILE__,__LINE__,info->device_name,status_reg1); 2404 2405 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */ 2406 write_reg16(info, TRC0, 0); 2407 info->ie0_value |= TXRDYE; 2408 write_reg(info, IE0, info->ie0_value); 2409} 2410 2411static void isr_txdmaerror(SLMP_INFO * info) 2412{ 2413 /* BIT5 = BOF (buffer overflow) 2414 * BIT4 = COF (counter overflow) 2415 */ 2416 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30; 2417 2418 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ 2419 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1)); 2420 2421 if ( debug_level >= DEBUG_LEVEL_ISR ) 2422 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n", 2423 __FILE__,__LINE__,info->device_name,status); 2424} 2425 2426/* handle input serial signal changes 2427 */ 2428static void isr_io_pin( SLMP_INFO *info, u16 status ) 2429{ 2430 struct mgsl_icount *icount; 2431 2432 if ( debug_level >= DEBUG_LEVEL_ISR ) 2433 printk("%s(%d):isr_io_pin status=%04X\n", 2434 __FILE__,__LINE__,status); 2435 2436 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED | 2437 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) { 2438 icount = &info->icount; 2439 /* update input line counters */ 2440 if (status & MISCSTATUS_RI_LATCHED) { 2441 icount->rng++; 2442 if ( status & SerialSignal_RI ) 2443 info->input_signal_events.ri_up++; 2444 else 2445 info->input_signal_events.ri_down++; 2446 } 2447 if (status & MISCSTATUS_DSR_LATCHED) { 2448 icount->dsr++; 2449 if ( status & SerialSignal_DSR ) 2450 info->input_signal_events.dsr_up++; 2451 else 2452 info->input_signal_events.dsr_down++; 2453 } 2454 if (status & MISCSTATUS_DCD_LATCHED) { 2455 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { 2456 info->ie1_value &= ~CDCD; 2457 write_reg(info, IE1, info->ie1_value); 2458 } 2459 icount->dcd++; 2460 if (status & SerialSignal_DCD) { 2461 info->input_signal_events.dcd_up++; 2462 } else 2463 info->input_signal_events.dcd_down++; 2464#if SYNCLINK_GENERIC_HDLC 2465 if (info->netcount) { 2466 if (status & SerialSignal_DCD) 2467 netif_carrier_on(info->netdev); 2468 else 2469 netif_carrier_off(info->netdev); 2470 } 2471#endif 2472 } 2473 if (status & MISCSTATUS_CTS_LATCHED) 2474 { 2475 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { 2476 info->ie1_value &= ~CCTS; 2477 write_reg(info, IE1, info->ie1_value); 2478 } 2479 icount->cts++; 2480 if ( status & SerialSignal_CTS ) 2481 info->input_signal_events.cts_up++; 2482 else 2483 info->input_signal_events.cts_down++; 2484 } 2485 wake_up_interruptible(&info->status_event_wait_q); 2486 wake_up_interruptible(&info->event_wait_q); 2487 2488 if ( (info->port.flags & ASYNC_CHECK_CD) && 2489 (status & MISCSTATUS_DCD_LATCHED) ) { 2490 if ( debug_level >= DEBUG_LEVEL_ISR ) 2491 printk("%s CD now %s...", info->device_name, 2492 (status & SerialSignal_DCD) ? "on" : "off"); 2493 if (status & SerialSignal_DCD) 2494 wake_up_interruptible(&info->port.open_wait); 2495 else { 2496 if ( debug_level >= DEBUG_LEVEL_ISR ) 2497 printk("doing serial hangup..."); 2498 if (info->port.tty) 2499 tty_hangup(info->port.tty); 2500 } 2501 } 2502 2503 if ( (info->port.flags & ASYNC_CTS_FLOW) && 2504 (status & MISCSTATUS_CTS_LATCHED) ) { 2505 if ( info->port.tty ) { 2506 if (info->port.tty->hw_stopped) { 2507 if (status & SerialSignal_CTS) { 2508 if ( debug_level >= DEBUG_LEVEL_ISR ) 2509 printk("CTS tx start..."); 2510 info->port.tty->hw_stopped = 0; 2511 tx_start(info); 2512 info->pending_bh |= BH_TRANSMIT; 2513 return; 2514 } 2515 } else { 2516 if (!(status & SerialSignal_CTS)) { 2517 if ( debug_level >= DEBUG_LEVEL_ISR ) 2518 printk("CTS tx stop..."); 2519 info->port.tty->hw_stopped = 1; 2520 tx_stop(info); 2521 } 2522 } 2523 } 2524 } 2525 } 2526 2527 info->pending_bh |= BH_STATUS; 2528} 2529 2530/* Interrupt service routine entry point. 2531 * 2532 * Arguments: 2533 * irq interrupt number that caused interrupt 2534 * dev_id device ID supplied during interrupt registration 2535 * regs interrupted processor context 2536 */ 2537static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id) 2538{ 2539 SLMP_INFO *info = dev_id; 2540 unsigned char status, status0, status1=0; 2541 unsigned char dmastatus, dmastatus0, dmastatus1=0; 2542 unsigned char timerstatus0, timerstatus1=0; 2543 unsigned char shift; 2544 unsigned int i; 2545 unsigned short tmp; 2546 2547 if ( debug_level >= DEBUG_LEVEL_ISR ) 2548 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n", 2549 __FILE__, __LINE__, info->irq_level); 2550 2551 spin_lock(&info->lock); 2552 2553 for(;;) { 2554 2555 /* get status for SCA0 (ports 0-1) */ 2556 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */ 2557 status0 = (unsigned char)tmp; 2558 dmastatus0 = (unsigned char)(tmp>>8); 2559 timerstatus0 = read_reg(info, ISR2); 2560 2561 if ( debug_level >= DEBUG_LEVEL_ISR ) 2562 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n", 2563 __FILE__, __LINE__, info->device_name, 2564 status0, dmastatus0, timerstatus0); 2565 2566 if (info->port_count == 4) { 2567 /* get status for SCA1 (ports 2-3) */ 2568 tmp = read_reg16(info->port_array[2], ISR0); 2569 status1 = (unsigned char)tmp; 2570 dmastatus1 = (unsigned char)(tmp>>8); 2571 timerstatus1 = read_reg(info->port_array[2], ISR2); 2572 2573 if ( debug_level >= DEBUG_LEVEL_ISR ) 2574 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n", 2575 __FILE__,__LINE__,info->device_name, 2576 status1,dmastatus1,timerstatus1); 2577 } 2578 2579 if (!status0 && !dmastatus0 && !timerstatus0 && 2580 !status1 && !dmastatus1 && !timerstatus1) 2581 break; 2582 2583 for(i=0; i < info->port_count ; i++) { 2584 if (info->port_array[i] == NULL) 2585 continue; 2586 if (i < 2) { 2587 status = status0; 2588 dmastatus = dmastatus0; 2589 } else { 2590 status = status1; 2591 dmastatus = dmastatus1; 2592 } 2593 2594 shift = i & 1 ? 4 :0; 2595 2596 if (status & BIT0 << shift) 2597 isr_rxrdy(info->port_array[i]); 2598 if (status & BIT1 << shift) 2599 isr_txrdy(info->port_array[i]); 2600 if (status & BIT2 << shift) 2601 isr_rxint(info->port_array[i]); 2602 if (status & BIT3 << shift) 2603 isr_txint(info->port_array[i]); 2604 2605 if (dmastatus & BIT0 << shift) 2606 isr_rxdmaerror(info->port_array[i]); 2607 if (dmastatus & BIT1 << shift) 2608 isr_rxdmaok(info->port_array[i]); 2609 if (dmastatus & BIT2 << shift) 2610 isr_txdmaerror(info->port_array[i]); 2611 if (dmastatus & BIT3 << shift) 2612 isr_txdmaok(info->port_array[i]); 2613 } 2614 2615 if (timerstatus0 & (BIT5 | BIT4)) 2616 isr_timer(info->port_array[0]); 2617 if (timerstatus0 & (BIT7 | BIT6)) 2618 isr_timer(info->port_array[1]); 2619 if (timerstatus1 & (BIT5 | BIT4)) 2620 isr_timer(info->port_array[2]); 2621 if (timerstatus1 & (BIT7 | BIT6)) 2622 isr_timer(info->port_array[3]); 2623 } 2624 2625 for(i=0; i < info->port_count ; i++) { 2626 SLMP_INFO * port = info->port_array[i]; 2627 2628 /* Request bottom half processing if there's something 2629 * for it to do and the bh is not already running. 2630 * 2631 * Note: startup adapter diags require interrupts. 2632 * do not request bottom half processing if the 2633 * device is not open in a normal mode. 2634 */ 2635 if ( port && (port->port.count || port->netcount) && 2636 port->pending_bh && !port->bh_running && 2637 !port->bh_requested ) { 2638 if ( debug_level >= DEBUG_LEVEL_ISR ) 2639 printk("%s(%d):%s queueing bh task.\n", 2640 __FILE__,__LINE__,port->device_name); 2641 schedule_work(&port->task); 2642 port->bh_requested = true; 2643 } 2644 } 2645 2646 spin_unlock(&info->lock); 2647 2648 if ( debug_level >= DEBUG_LEVEL_ISR ) 2649 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n", 2650 __FILE__, __LINE__, info->irq_level); 2651 return IRQ_HANDLED; 2652} 2653 2654/* Initialize and start device. 2655 */ 2656static int startup(SLMP_INFO * info) 2657{ 2658 if ( debug_level >= DEBUG_LEVEL_INFO ) 2659 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name); 2660 2661 if (info->port.flags & ASYNC_INITIALIZED) 2662 return 0; 2663 2664 if (!info->tx_buf) { 2665 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 2666 if (!info->tx_buf) { 2667 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n", 2668 __FILE__,__LINE__,info->device_name); 2669 return -ENOMEM; 2670 } 2671 } 2672 2673 info->pending_bh = 0; 2674 2675 memset(&info->icount, 0, sizeof(info->icount)); 2676 2677 /* program hardware for current parameters */ 2678 reset_port(info); 2679 2680 change_params(info); 2681 2682 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); 2683 2684 if (info->port.tty) 2685 clear_bit(TTY_IO_ERROR, &info->port.tty->flags); 2686 2687 info->port.flags |= ASYNC_INITIALIZED; 2688 2689 return 0; 2690} 2691 2692/* Called by close() and hangup() to shutdown hardware 2693 */ 2694static void shutdown(SLMP_INFO * info) 2695{ 2696 unsigned long flags; 2697 2698 if (!(info->port.flags & ASYNC_INITIALIZED)) 2699 return; 2700 2701 if (debug_level >= DEBUG_LEVEL_INFO) 2702 printk("%s(%d):%s synclinkmp_shutdown()\n", 2703 __FILE__,__LINE__, info->device_name ); 2704 2705 /* clear status wait queue because status changes */ 2706 /* can't happen after shutting down the hardware */ 2707 wake_up_interruptible(&info->status_event_wait_q); 2708 wake_up_interruptible(&info->event_wait_q); 2709 2710 del_timer(&info->tx_timer); 2711 del_timer(&info->status_timer); 2712 2713 kfree(info->tx_buf); 2714 info->tx_buf = NULL; 2715 2716 spin_lock_irqsave(&info->lock,flags); 2717 2718 reset_port(info); 2719 2720 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) { 2721 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS); 2722 set_signals(info); 2723 } 2724 2725 spin_unlock_irqrestore(&info->lock,flags); 2726 2727 if (info->port.tty) 2728 set_bit(TTY_IO_ERROR, &info->port.tty->flags); 2729 2730 info->port.flags &= ~ASYNC_INITIALIZED; 2731} 2732 2733static void program_hw(SLMP_INFO *info) 2734{ 2735 unsigned long flags; 2736 2737 spin_lock_irqsave(&info->lock,flags); 2738 2739 rx_stop(info); 2740 tx_stop(info); 2741 2742 info->tx_count = info->tx_put = info->tx_get = 0; 2743 2744 if (info->params.mode == MGSL_MODE_HDLC || info->netcount) 2745 hdlc_mode(info); 2746 else 2747 async_mode(info); 2748 2749 set_signals(info); 2750 2751 info->dcd_chkcount = 0; 2752 info->cts_chkcount = 0; 2753 info->ri_chkcount = 0; 2754 info->dsr_chkcount = 0; 2755 2756 info->ie1_value |= (CDCD|CCTS); 2757 write_reg(info, IE1, info->ie1_value); 2758 2759 get_signals(info); 2760 2761 if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) ) 2762 rx_start(info); 2763 2764 spin_unlock_irqrestore(&info->lock,flags); 2765} 2766 2767/* Reconfigure adapter based on new parameters 2768 */ 2769static void change_params(SLMP_INFO *info) 2770{ 2771 unsigned cflag; 2772 int bits_per_char; 2773 2774 if (!info->port.tty || !info->port.tty->termios) 2775 return; 2776 2777 if (debug_level >= DEBUG_LEVEL_INFO) 2778 printk("%s(%d):%s change_params()\n", 2779 __FILE__,__LINE__, info->device_name ); 2780 2781 cflag = info->port.tty->termios->c_cflag; 2782 2783 /* if B0 rate (hangup) specified then negate DTR and RTS */ 2784 /* otherwise assert DTR and RTS */ 2785 if (cflag & CBAUD) 2786 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; 2787 else 2788 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); 2789 2790 /* byte size and parity */ 2791 2792 switch (cflag & CSIZE) { 2793 case CS5: info->params.data_bits = 5; break; 2794 case CS6: info->params.data_bits = 6; break; 2795 case CS7: info->params.data_bits = 7; break; 2796 case CS8: info->params.data_bits = 8; break; 2797 /* Never happens, but GCC is too dumb to figure it out */ 2798 default: info->params.data_bits = 7; break; 2799 } 2800 2801 if (cflag & CSTOPB) 2802 info->params.stop_bits = 2; 2803 else 2804 info->params.stop_bits = 1; 2805 2806 info->params.parity = ASYNC_PARITY_NONE; 2807 if (cflag & PARENB) { 2808 if (cflag & PARODD) 2809 info->params.parity = ASYNC_PARITY_ODD; 2810 else 2811 info->params.parity = ASYNC_PARITY_EVEN; 2812#ifdef CMSPAR 2813 if (cflag & CMSPAR) 2814 info->params.parity = ASYNC_PARITY_SPACE; 2815#endif 2816 } 2817 2818 /* calculate number of jiffies to transmit a full 2819 * FIFO (32 bytes) at specified data rate 2820 */ 2821 bits_per_char = info->params.data_bits + 2822 info->params.stop_bits + 1; 2823 2824 /* if port data rate is set to 460800 or less then 2825 * allow tty settings to override, otherwise keep the 2826 * current data rate. 2827 */ 2828 if (info->params.data_rate <= 460800) { 2829 info->params.data_rate = tty_get_baud_rate(info->port.tty); 2830 } 2831 2832 if ( info->params.data_rate ) { 2833 info->timeout = (32*HZ*bits_per_char) / 2834 info->params.data_rate; 2835 } 2836 info->timeout += HZ/50; /* Add .02 seconds of slop */ 2837 2838 if (cflag & CRTSCTS) 2839 info->port.flags |= ASYNC_CTS_FLOW; 2840 else 2841 info->port.flags &= ~ASYNC_CTS_FLOW; 2842 2843 if (cflag & CLOCAL) 2844 info->port.flags &= ~ASYNC_CHECK_CD; 2845 else 2846 info->port.flags |= ASYNC_CHECK_CD; 2847 2848 /* process tty input control flags */ 2849 2850 info->read_status_mask2 = OVRN; 2851 if (I_INPCK(info->port.tty)) 2852 info->read_status_mask2 |= PE | FRME; 2853 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) 2854 info->read_status_mask1 |= BRKD; 2855 if (I_IGNPAR(info->port.tty)) 2856 info->ignore_status_mask2 |= PE | FRME; 2857 if (I_IGNBRK(info->port.tty)) { 2858 info->ignore_status_mask1 |= BRKD; 2859 /* If ignoring parity and break indicators, ignore 2860 * overruns too. (For real raw support). 2861 */ 2862 if (I_IGNPAR(info->port.tty)) 2863 info->ignore_status_mask2 |= OVRN; 2864 } 2865 2866 program_hw(info); 2867} 2868 2869static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount) 2870{ 2871 int err; 2872 2873 if (debug_level >= DEBUG_LEVEL_INFO) 2874 printk("%s(%d):%s get_params()\n", 2875 __FILE__,__LINE__, info->device_name); 2876 2877 if (!user_icount) { 2878 memset(&info->icount, 0, sizeof(info->icount)); 2879 } else { 2880 mutex_lock(&info->port.mutex); 2881 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount)); 2882 mutex_unlock(&info->port.mutex); 2883 if (err) 2884 return -EFAULT; 2885 } 2886 2887 return 0; 2888} 2889 2890static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params) 2891{ 2892 int err; 2893 if (debug_level >= DEBUG_LEVEL_INFO) 2894 printk("%s(%d):%s get_params()\n", 2895 __FILE__,__LINE__, info->device_name); 2896 2897 mutex_lock(&info->port.mutex); 2898 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS)); 2899 mutex_unlock(&info->port.mutex); 2900 if (err) { 2901 if ( debug_level >= DEBUG_LEVEL_INFO ) 2902 printk( "%s(%d):%s get_params() user buffer copy failed\n", 2903 __FILE__,__LINE__,info->device_name); 2904 return -EFAULT; 2905 } 2906 2907 return 0; 2908} 2909 2910static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params) 2911{ 2912 unsigned long flags; 2913 MGSL_PARAMS tmp_params; 2914 int err; 2915 2916 if (debug_level >= DEBUG_LEVEL_INFO) 2917 printk("%s(%d):%s set_params\n", 2918 __FILE__,__LINE__,info->device_name ); 2919 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS)); 2920 if (err) { 2921 if ( debug_level >= DEBUG_LEVEL_INFO ) 2922 printk( "%s(%d):%s set_params() user buffer copy failed\n", 2923 __FILE__,__LINE__,info->device_name); 2924 return -EFAULT; 2925 } 2926 2927 mutex_lock(&info->port.mutex); 2928 spin_lock_irqsave(&info->lock,flags); 2929 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); 2930 spin_unlock_irqrestore(&info->lock,flags); 2931 2932 change_params(info); 2933 mutex_unlock(&info->port.mutex); 2934 2935 return 0; 2936} 2937 2938static int get_txidle(SLMP_INFO * info, int __user *idle_mode) 2939{ 2940 int err; 2941 2942 if (debug_level >= DEBUG_LEVEL_INFO) 2943 printk("%s(%d):%s get_txidle()=%d\n", 2944 __FILE__,__LINE__, info->device_name, info->idle_mode); 2945 2946 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int)); 2947 if (err) { 2948 if ( debug_level >= DEBUG_LEVEL_INFO ) 2949 printk( "%s(%d):%s get_txidle() user buffer copy failed\n", 2950 __FILE__,__LINE__,info->device_name); 2951 return -EFAULT; 2952 } 2953 2954 return 0; 2955} 2956 2957static int set_txidle(SLMP_INFO * info, int idle_mode) 2958{ 2959 unsigned long flags; 2960 2961 if (debug_level >= DEBUG_LEVEL_INFO) 2962 printk("%s(%d):%s set_txidle(%d)\n", 2963 __FILE__,__LINE__,info->device_name, idle_mode ); 2964 2965 spin_lock_irqsave(&info->lock,flags); 2966 info->idle_mode = idle_mode; 2967 tx_set_idle( info ); 2968 spin_unlock_irqrestore(&info->lock,flags); 2969 return 0; 2970} 2971 2972static int tx_enable(SLMP_INFO * info, int enable) 2973{ 2974 unsigned long flags; 2975 2976 if (debug_level >= DEBUG_LEVEL_INFO) 2977 printk("%s(%d):%s tx_enable(%d)\n", 2978 __FILE__,__LINE__,info->device_name, enable); 2979 2980 spin_lock_irqsave(&info->lock,flags); 2981 if ( enable ) { 2982 if ( !info->tx_enabled ) { 2983 tx_start(info); 2984 } 2985 } else { 2986 if ( info->tx_enabled ) 2987 tx_stop(info); 2988 } 2989 spin_unlock_irqrestore(&info->lock,flags); 2990 return 0; 2991} 2992 2993/* abort send HDLC frame 2994 */ 2995static int tx_abort(SLMP_INFO * info) 2996{ 2997 unsigned long flags; 2998 2999 if (debug_level >= DEBUG_LEVEL_INFO) 3000 printk("%s(%d):%s tx_abort()\n", 3001 __FILE__,__LINE__,info->device_name); 3002 3003 spin_lock_irqsave(&info->lock,flags); 3004 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) { 3005 info->ie1_value &= ~UDRN; 3006 info->ie1_value |= IDLE; 3007 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ 3008 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ 3009 3010 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ 3011 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 3012 3013 write_reg(info, CMD, TXABORT); 3014 } 3015 spin_unlock_irqrestore(&info->lock,flags); 3016 return 0; 3017} 3018 3019static int rx_enable(SLMP_INFO * info, int enable) 3020{ 3021 unsigned long flags; 3022 3023 if (debug_level >= DEBUG_LEVEL_INFO) 3024 printk("%s(%d):%s rx_enable(%d)\n", 3025 __FILE__,__LINE__,info->device_name,enable); 3026 3027 spin_lock_irqsave(&info->lock,flags); 3028 if ( enable ) { 3029 if ( !info->rx_enabled ) 3030 rx_start(info); 3031 } else { 3032 if ( info->rx_enabled ) 3033 rx_stop(info); 3034 } 3035 spin_unlock_irqrestore(&info->lock,flags); 3036 return 0; 3037} 3038 3039/* wait for specified event to occur 3040 */ 3041static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr) 3042{ 3043 unsigned long flags; 3044 int s; 3045 int rc=0; 3046 struct mgsl_icount cprev, cnow; 3047 int events; 3048 int mask; 3049 struct _input_signal_events oldsigs, newsigs; 3050 DECLARE_WAITQUEUE(wait, current); 3051 3052 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); 3053 if (rc) { 3054 return -EFAULT; 3055 } 3056 3057 if (debug_level >= DEBUG_LEVEL_INFO) 3058 printk("%s(%d):%s wait_mgsl_event(%d)\n", 3059 __FILE__,__LINE__,info->device_name,mask); 3060 3061 spin_lock_irqsave(&info->lock,flags); 3062 3063 /* return immediately if state matches requested events */ 3064 get_signals(info); 3065 s = info->serial_signals; 3066 3067 events = mask & 3068 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + 3069 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + 3070 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + 3071 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); 3072 if (events) { 3073 spin_unlock_irqrestore(&info->lock,flags); 3074 goto exit; 3075 } 3076 3077 /* save current irq counts */ 3078 cprev = info->icount; 3079 oldsigs = info->input_signal_events; 3080 3081 /* enable hunt and idle irqs if needed */ 3082 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { 3083 unsigned char oldval = info->ie1_value; 3084 unsigned char newval = oldval + 3085 (mask & MgslEvent_ExitHuntMode ? FLGD:0) + 3086 (mask & MgslEvent_IdleReceived ? IDLD:0); 3087 if ( oldval != newval ) { 3088 info->ie1_value = newval; 3089 write_reg(info, IE1, info->ie1_value); 3090 } 3091 } 3092 3093 set_current_state(TASK_INTERRUPTIBLE); 3094 add_wait_queue(&info->event_wait_q, &wait); 3095 3096 spin_unlock_irqrestore(&info->lock,flags); 3097 3098 for(;;) { 3099 schedule(); 3100 if (signal_pending(current)) { 3101 rc = -ERESTARTSYS; 3102 break; 3103 } 3104 3105 /* get current irq counts */ 3106 spin_lock_irqsave(&info->lock,flags); 3107 cnow = info->icount; 3108 newsigs = info->input_signal_events; 3109 set_current_state(TASK_INTERRUPTIBLE); 3110 spin_unlock_irqrestore(&info->lock,flags); 3111 3112 /* if no change, wait aborted for some reason */ 3113 if (newsigs.dsr_up == oldsigs.dsr_up && 3114 newsigs.dsr_down == oldsigs.dsr_down && 3115 newsigs.dcd_up == oldsigs.dcd_up && 3116 newsigs.dcd_down == oldsigs.dcd_down && 3117 newsigs.cts_up == oldsigs.cts_up && 3118 newsigs.cts_down == oldsigs.cts_down && 3119 newsigs.ri_up == oldsigs.ri_up && 3120 newsigs.ri_down == oldsigs.ri_down && 3121 cnow.exithunt == cprev.exithunt && 3122 cnow.rxidle == cprev.rxidle) { 3123 rc = -EIO; 3124 break; 3125 } 3126 3127 events = mask & 3128 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + 3129 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + 3130 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + 3131 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + 3132 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + 3133 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + 3134 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + 3135 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + 3136 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + 3137 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); 3138 if (events) 3139 break; 3140 3141 cprev = cnow; 3142 oldsigs = newsigs; 3143 } 3144 3145 remove_wait_queue(&info->event_wait_q, &wait); 3146 set_current_state(TASK_RUNNING); 3147 3148 3149 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { 3150 spin_lock_irqsave(&info->lock,flags); 3151 if (!waitqueue_active(&info->event_wait_q)) { 3152 /* disable enable exit hunt mode/idle rcvd IRQs */ 3153 info->ie1_value &= ~(FLGD|IDLD); 3154 write_reg(info, IE1, info->ie1_value); 3155 } 3156 spin_unlock_irqrestore(&info->lock,flags); 3157 } 3158exit: 3159 if ( rc == 0 ) 3160 PUT_USER(rc, events, mask_ptr); 3161 3162 return rc; 3163} 3164 3165static int modem_input_wait(SLMP_INFO *info,int arg) 3166{ 3167 unsigned long flags; 3168 int rc; 3169 struct mgsl_icount cprev, cnow; 3170 DECLARE_WAITQUEUE(wait, current); 3171 3172 /* save current irq counts */ 3173 spin_lock_irqsave(&info->lock,flags); 3174 cprev = info->icount; 3175 add_wait_queue(&info->status_event_wait_q, &wait); 3176 set_current_state(TASK_INTERRUPTIBLE); 3177 spin_unlock_irqrestore(&info->lock,flags); 3178 3179 for(;;) { 3180 schedule(); 3181 if (signal_pending(current)) { 3182 rc = -ERESTARTSYS; 3183 break; 3184 } 3185 3186 /* get new irq counts */ 3187 spin_lock_irqsave(&info->lock,flags); 3188 cnow = info->icount; 3189 set_current_state(TASK_INTERRUPTIBLE); 3190 spin_unlock_irqrestore(&info->lock,flags); 3191 3192 /* if no change, wait aborted for some reason */ 3193 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 3194 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 3195 rc = -EIO; 3196 break; 3197 } 3198 3199 /* check for change in caller specified modem input */ 3200 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || 3201 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || 3202 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || 3203 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { 3204 rc = 0; 3205 break; 3206 } 3207 3208 cprev = cnow; 3209 } 3210 remove_wait_queue(&info->status_event_wait_q, &wait); 3211 set_current_state(TASK_RUNNING); 3212 return rc; 3213} 3214 3215/* return the state of the serial control and status signals 3216 */ 3217static int tiocmget(struct tty_struct *tty, struct file *file) 3218{ 3219 SLMP_INFO *info = tty->driver_data; 3220 unsigned int result; 3221 unsigned long flags; 3222 3223 spin_lock_irqsave(&info->lock,flags); 3224 get_signals(info); 3225 spin_unlock_irqrestore(&info->lock,flags); 3226 3227 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) + 3228 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) + 3229 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) + 3230 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) + 3231 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) + 3232 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0); 3233 3234 if (debug_level >= DEBUG_LEVEL_INFO) 3235 printk("%s(%d):%s tiocmget() value=%08X\n", 3236 __FILE__,__LINE__, info->device_name, result ); 3237 return result; 3238} 3239 3240/* set modem control signals (DTR/RTS) 3241 */ 3242static int tiocmset(struct tty_struct *tty, struct file *file, 3243 unsigned int set, unsigned int clear) 3244{ 3245 SLMP_INFO *info = tty->driver_data; 3246 unsigned long flags; 3247 3248 if (debug_level >= DEBUG_LEVEL_INFO) 3249 printk("%s(%d):%s tiocmset(%x,%x)\n", 3250 __FILE__,__LINE__,info->device_name, set, clear); 3251 3252 if (set & TIOCM_RTS) 3253 info->serial_signals |= SerialSignal_RTS; 3254 if (set & TIOCM_DTR) 3255 info->serial_signals |= SerialSignal_DTR; 3256 if (clear & TIOCM_RTS) 3257 info->serial_signals &= ~SerialSignal_RTS; 3258 if (clear & TIOCM_DTR) 3259 info->serial_signals &= ~SerialSignal_DTR; 3260 3261 spin_lock_irqsave(&info->lock,flags); 3262 set_signals(info); 3263 spin_unlock_irqrestore(&info->lock,flags); 3264 3265 return 0; 3266} 3267 3268static int carrier_raised(struct tty_port *port) 3269{ 3270 SLMP_INFO *info = container_of(port, SLMP_INFO, port); 3271 unsigned long flags; 3272 3273 spin_lock_irqsave(&info->lock,flags); 3274 get_signals(info); 3275 spin_unlock_irqrestore(&info->lock,flags); 3276 3277 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0; 3278} 3279 3280static void dtr_rts(struct tty_port *port, int on) 3281{ 3282 SLMP_INFO *info = container_of(port, SLMP_INFO, port); 3283 unsigned long flags; 3284 3285 spin_lock_irqsave(&info->lock,flags); 3286 if (on) 3287 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR; 3288 else 3289 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR); 3290 set_signals(info); 3291 spin_unlock_irqrestore(&info->lock,flags); 3292} 3293 3294/* Block the current process until the specified port is ready to open. 3295 */ 3296static int block_til_ready(struct tty_struct *tty, struct file *filp, 3297 SLMP_INFO *info) 3298{ 3299 DECLARE_WAITQUEUE(wait, current); 3300 int retval; 3301 bool do_clocal = false; 3302 bool extra_count = false; 3303 unsigned long flags; 3304 int cd; 3305 struct tty_port *port = &info->port; 3306 3307 if (debug_level >= DEBUG_LEVEL_INFO) 3308 printk("%s(%d):%s block_til_ready()\n", 3309 __FILE__,__LINE__, tty->driver->name ); 3310 3311 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ 3312 /* nonblock mode is set or port is not enabled */ 3313 /* just verify that callout device is not active */ 3314 port->flags |= ASYNC_NORMAL_ACTIVE; 3315 return 0; 3316 } 3317 3318 if (tty->termios->c_cflag & CLOCAL) 3319 do_clocal = true; 3320 3321 /* Wait for carrier detect and the line to become 3322 * free (i.e., not in use by the callout). While we are in 3323 * this loop, port->count is dropped by one, so that 3324 * close() knows when to free things. We restore it upon 3325 * exit, either normal or abnormal. 3326 */ 3327 3328 retval = 0; 3329 add_wait_queue(&port->open_wait, &wait); 3330 3331 if (debug_level >= DEBUG_LEVEL_INFO) 3332 printk("%s(%d):%s block_til_ready() before block, count=%d\n", 3333 __FILE__,__LINE__, tty->driver->name, port->count ); 3334 3335 spin_lock_irqsave(&info->lock, flags); 3336 if (!tty_hung_up_p(filp)) { 3337 extra_count = true; 3338 port->count--; 3339 } 3340 spin_unlock_irqrestore(&info->lock, flags); 3341 port->blocked_open++; 3342 3343 while (1) { 3344 if (tty->termios->c_cflag & CBAUD) 3345 tty_port_raise_dtr_rts(port); 3346 3347 set_current_state(TASK_INTERRUPTIBLE); 3348 3349 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ 3350 retval = (port->flags & ASYNC_HUP_NOTIFY) ? 3351 -EAGAIN : -ERESTARTSYS; 3352 break; 3353 } 3354 3355 cd = tty_port_carrier_raised(port); 3356 3357 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd)) 3358 break; 3359 3360 if (signal_pending(current)) { 3361 retval = -ERESTARTSYS; 3362 break; 3363 } 3364 3365 if (debug_level >= DEBUG_LEVEL_INFO) 3366 printk("%s(%d):%s block_til_ready() count=%d\n", 3367 __FILE__,__LINE__, tty->driver->name, port->count ); 3368 3369 tty_unlock(); 3370 schedule(); 3371 tty_lock(); 3372 } 3373 3374 set_current_state(TASK_RUNNING); 3375 remove_wait_queue(&port->open_wait, &wait); 3376 3377 if (extra_count) 3378 port->count++; 3379 port->blocked_open--; 3380 3381 if (debug_level >= DEBUG_LEVEL_INFO) 3382 printk("%s(%d):%s block_til_ready() after, count=%d\n", 3383 __FILE__,__LINE__, tty->driver->name, port->count ); 3384 3385 if (!retval) 3386 port->flags |= ASYNC_NORMAL_ACTIVE; 3387 3388 return retval; 3389} 3390 3391static int alloc_dma_bufs(SLMP_INFO *info) 3392{ 3393 unsigned short BuffersPerFrame; 3394 unsigned short BufferCount; 3395 3396 // Force allocation to start at 64K boundary for each port. 3397 // This is necessary because *all* buffer descriptors for a port 3398 // *must* be in the same 64K block. All descriptors on a port 3399 // share a common 'base' address (upper 8 bits of 24 bits) programmed 3400 // into the CBP register. 3401 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num; 3402 3403 /* Calculate the number of DMA buffers necessary to hold the */ 3404 /* largest allowable frame size. Note: If the max frame size is */ 3405 /* not an even multiple of the DMA buffer size then we need to */ 3406 /* round the buffer count per frame up one. */ 3407 3408 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE); 3409 if ( info->max_frame_size % SCABUFSIZE ) 3410 BuffersPerFrame++; 3411 3412 /* calculate total number of data buffers (SCABUFSIZE) possible 3413 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory 3414 * for the descriptor list (BUFFERLISTSIZE). 3415 */ 3416 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE; 3417 3418 /* limit number of buffers to maximum amount of descriptors */ 3419 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC)) 3420 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC); 3421 3422 /* use enough buffers to transmit one max size frame */ 3423 info->tx_buf_count = BuffersPerFrame + 1; 3424 3425 /* never use more than half the available buffers for transmit */ 3426 if (info->tx_buf_count > (BufferCount/2)) 3427 info->tx_buf_count = BufferCount/2; 3428 3429 if (info->tx_buf_count > SCAMAXDESC) 3430 info->tx_buf_count = SCAMAXDESC; 3431 3432 /* use remaining buffers for receive */ 3433 info->rx_buf_count = BufferCount - info->tx_buf_count; 3434 3435 if (info->rx_buf_count > SCAMAXDESC) 3436 info->rx_buf_count = SCAMAXDESC; 3437 3438 if ( debug_level >= DEBUG_LEVEL_INFO ) 3439 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n", 3440 __FILE__,__LINE__, info->device_name, 3441 info->tx_buf_count,info->rx_buf_count); 3442 3443 if ( alloc_buf_list( info ) < 0 || 3444 alloc_frame_bufs(info, 3445 info->rx_buf_list, 3446 info->rx_buf_list_ex, 3447 info->rx_buf_count) < 0 || 3448 alloc_frame_bufs(info, 3449 info->tx_buf_list, 3450 info->tx_buf_list_ex, 3451 info->tx_buf_count) < 0 || 3452 alloc_tmp_rx_buf(info) < 0 ) { 3453 printk("%s(%d):%s Can't allocate DMA buffer memory\n", 3454 __FILE__,__LINE__, info->device_name); 3455 return -ENOMEM; 3456 } 3457 3458 rx_reset_buffers( info ); 3459 3460 return 0; 3461} 3462 3463/* Allocate DMA buffers for the transmit and receive descriptor lists. 3464 */ 3465static int alloc_buf_list(SLMP_INFO *info) 3466{ 3467 unsigned int i; 3468 3469 /* build list in adapter shared memory */ 3470 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc; 3471 info->buffer_list_phys = info->port_array[0]->last_mem_alloc; 3472 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE; 3473 3474 memset(info->buffer_list, 0, BUFFERLISTSIZE); 3475 3476 /* Save virtual address pointers to the receive and */ 3477 /* transmit buffer lists. (Receive 1st). These pointers will */ 3478 /* be used by the processor to access the lists. */ 3479 info->rx_buf_list = (SCADESC *)info->buffer_list; 3480 3481 info->tx_buf_list = (SCADESC *)info->buffer_list; 3482 info->tx_buf_list += info->rx_buf_count; 3483 3484 /* Build links for circular buffer entry lists (tx and rx) 3485 * 3486 * Note: links are physical addresses read by the SCA device 3487 * to determine the next buffer entry to use. 3488 */ 3489 3490 for ( i = 0; i < info->rx_buf_count; i++ ) { 3491 /* calculate and store physical address of this buffer entry */ 3492 info->rx_buf_list_ex[i].phys_entry = 3493 info->buffer_list_phys + (i * sizeof(SCABUFSIZE)); 3494 3495 /* calculate and store physical address of */ 3496 /* next entry in cirular list of entries */ 3497 info->rx_buf_list[i].next = info->buffer_list_phys; 3498 if ( i < info->rx_buf_count - 1 ) 3499 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC); 3500 3501 info->rx_buf_list[i].length = SCABUFSIZE; 3502 } 3503 3504 for ( i = 0; i < info->tx_buf_count; i++ ) { 3505 /* calculate and store physical address of this buffer entry */ 3506 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys + 3507 ((info->rx_buf_count + i) * sizeof(SCADESC)); 3508 3509 /* calculate and store physical address of */ 3510 /* next entry in cirular list of entries */ 3511 3512 info->tx_buf_list[i].next = info->buffer_list_phys + 3513 info->rx_buf_count * sizeof(SCADESC); 3514 3515 if ( i < info->tx_buf_count - 1 ) 3516 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC); 3517 } 3518 3519 return 0; 3520} 3521 3522/* Allocate the frame DMA buffers used by the specified buffer list. 3523 */ 3524static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count) 3525{ 3526 int i; 3527 unsigned long phys_addr; 3528 3529 for ( i = 0; i < count; i++ ) { 3530 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc; 3531 phys_addr = info->port_array[0]->last_mem_alloc; 3532 info->port_array[0]->last_mem_alloc += SCABUFSIZE; 3533 3534 buf_list[i].buf_ptr = (unsigned short)phys_addr; 3535 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16); 3536 } 3537 3538 return 0; 3539} 3540 3541static void free_dma_bufs(SLMP_INFO *info) 3542{ 3543 info->buffer_list = NULL; 3544 info->rx_buf_list = NULL; 3545 info->tx_buf_list = NULL; 3546} 3547 3548/* allocate buffer large enough to hold max_frame_size. 3549 * This buffer is used to pass an assembled frame to the line discipline. 3550 */ 3551static int alloc_tmp_rx_buf(SLMP_INFO *info) 3552{ 3553 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 3554 if (info->tmp_rx_buf == NULL) 3555 return -ENOMEM; 3556 return 0; 3557} 3558 3559static void free_tmp_rx_buf(SLMP_INFO *info) 3560{ 3561 kfree(info->tmp_rx_buf); 3562 info->tmp_rx_buf = NULL; 3563} 3564 3565static int claim_resources(SLMP_INFO *info) 3566{ 3567 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) { 3568 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n", 3569 __FILE__,__LINE__,info->device_name, info->phys_memory_base); 3570 info->init_error = DiagStatus_AddressConflict; 3571 goto errout; 3572 } 3573 else 3574 info->shared_mem_requested = true; 3575 3576 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) { 3577 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n", 3578 __FILE__,__LINE__,info->device_name, info->phys_lcr_base); 3579 info->init_error = DiagStatus_AddressConflict; 3580 goto errout; 3581 } 3582 else 3583 info->lcr_mem_requested = true; 3584 3585 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) { 3586 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n", 3587 __FILE__,__LINE__,info->device_name, info->phys_sca_base); 3588 info->init_error = DiagStatus_AddressConflict; 3589 goto errout; 3590 } 3591 else 3592 info->sca_base_requested = true; 3593 3594 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) { 3595 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n", 3596 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base); 3597 info->init_error = DiagStatus_AddressConflict; 3598 goto errout; 3599 } 3600 else 3601 info->sca_statctrl_requested = true; 3602 3603 info->memory_base = ioremap_nocache(info->phys_memory_base, 3604 SCA_MEM_SIZE); 3605 if (!info->memory_base) { 3606 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n", 3607 __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 3608 info->init_error = DiagStatus_CantAssignPciResources; 3609 goto errout; 3610 } 3611 3612 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE); 3613 if (!info->lcr_base) { 3614 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n", 3615 __FILE__,__LINE__,info->device_name, info->phys_lcr_base ); 3616 info->init_error = DiagStatus_CantAssignPciResources; 3617 goto errout; 3618 } 3619 info->lcr_base += info->lcr_offset; 3620 3621 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE); 3622 if (!info->sca_base) { 3623 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n", 3624 __FILE__,__LINE__,info->device_name, info->phys_sca_base ); 3625 info->init_error = DiagStatus_CantAssignPciResources; 3626 goto errout; 3627 } 3628 info->sca_base += info->sca_offset; 3629 3630 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base, 3631 PAGE_SIZE); 3632 if (!info->statctrl_base) { 3633 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n", 3634 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base ); 3635 info->init_error = DiagStatus_CantAssignPciResources; 3636 goto errout; 3637 } 3638 info->statctrl_base += info->statctrl_offset; 3639 3640 if ( !memory_test(info) ) { 3641 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n", 3642 __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 3643 info->init_error = DiagStatus_MemoryError; 3644 goto errout; 3645 } 3646 3647 return 0; 3648 3649errout: 3650 release_resources( info ); 3651 return -ENODEV; 3652} 3653 3654static void release_resources(SLMP_INFO *info) 3655{ 3656 if ( debug_level >= DEBUG_LEVEL_INFO ) 3657 printk( "%s(%d):%s release_resources() entry\n", 3658 __FILE__,__LINE__,info->device_name ); 3659 3660 if ( info->irq_requested ) { 3661 free_irq(info->irq_level, info); 3662 info->irq_requested = false; 3663 } 3664 3665 if ( info->shared_mem_requested ) { 3666 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE); 3667 info->shared_mem_requested = false; 3668 } 3669 if ( info->lcr_mem_requested ) { 3670 release_mem_region(info->phys_lcr_base + info->lcr_offset,128); 3671 info->lcr_mem_requested = false; 3672 } 3673 if ( info->sca_base_requested ) { 3674 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE); 3675 info->sca_base_requested = false; 3676 } 3677 if ( info->sca_statctrl_requested ) { 3678 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE); 3679 info->sca_statctrl_requested = false; 3680 } 3681 3682 if (info->memory_base){ 3683 iounmap(info->memory_base); 3684 info->memory_base = NULL; 3685 } 3686 3687 if (info->sca_base) { 3688 iounmap(info->sca_base - info->sca_offset); 3689 info->sca_base=NULL; 3690 } 3691 3692 if (info->statctrl_base) { 3693 iounmap(info->statctrl_base - info->statctrl_offset); 3694 info->statctrl_base=NULL; 3695 } 3696 3697 if (info->lcr_base){ 3698 iounmap(info->lcr_base - info->lcr_offset); 3699 info->lcr_base = NULL; 3700 } 3701 3702 if ( debug_level >= DEBUG_LEVEL_INFO ) 3703 printk( "%s(%d):%s release_resources() exit\n", 3704 __FILE__,__LINE__,info->device_name ); 3705} 3706 3707/* Add the specified device instance data structure to the 3708 * global linked list of devices and increment the device count. 3709 */ 3710static void add_device(SLMP_INFO *info) 3711{ 3712 info->next_device = NULL; 3713 info->line = synclinkmp_device_count; 3714 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num); 3715 3716 if (info->line < MAX_DEVICES) { 3717 if (maxframe[info->line]) 3718 info->max_frame_size = maxframe[info->line]; 3719 } 3720 3721 synclinkmp_device_count++; 3722 3723 if ( !synclinkmp_device_list ) 3724 synclinkmp_device_list = info; 3725 else { 3726 SLMP_INFO *current_dev = synclinkmp_device_list; 3727 while( current_dev->next_device ) 3728 current_dev = current_dev->next_device; 3729 current_dev->next_device = info; 3730 } 3731 3732 if ( info->max_frame_size < 4096 ) 3733 info->max_frame_size = 4096; 3734 else if ( info->max_frame_size > 65535 ) 3735 info->max_frame_size = 65535; 3736 3737 printk( "SyncLink MultiPort %s: " 3738 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n", 3739 info->device_name, 3740 info->phys_sca_base, 3741 info->phys_memory_base, 3742 info->phys_statctrl_base, 3743 info->phys_lcr_base, 3744 info->irq_level, 3745 info->max_frame_size ); 3746 3747#if SYNCLINK_GENERIC_HDLC 3748 hdlcdev_init(info); 3749#endif 3750} 3751 3752static const struct tty_port_operations port_ops = { 3753 .carrier_raised = carrier_raised, 3754 .dtr_rts = dtr_rts, 3755}; 3756 3757/* Allocate and initialize a device instance structure 3758 * 3759 * Return Value: pointer to SLMP_INFO if success, otherwise NULL 3760 */ 3761static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) 3762{ 3763 SLMP_INFO *info; 3764 3765 info = kzalloc(sizeof(SLMP_INFO), 3766 GFP_KERNEL); 3767 3768 if (!info) { 3769 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n", 3770 __FILE__,__LINE__, adapter_num, port_num); 3771 } else { 3772 tty_port_init(&info->port); 3773 info->port.ops = &port_ops; 3774 info->magic = MGSL_MAGIC; 3775 INIT_WORK(&info->task, bh_handler); 3776 info->max_frame_size = 4096; 3777 info->port.close_delay = 5*HZ/10; 3778 info->port.closing_wait = 30*HZ; 3779 init_waitqueue_head(&info->status_event_wait_q); 3780 init_waitqueue_head(&info->event_wait_q); 3781 spin_lock_init(&info->netlock); 3782 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); 3783 info->idle_mode = HDLC_TXIDLE_FLAGS; 3784 info->adapter_num = adapter_num; 3785 info->port_num = port_num; 3786 3787 /* Copy configuration info to device instance data */ 3788 info->irq_level = pdev->irq; 3789 info->phys_lcr_base = pci_resource_start(pdev,0); 3790 info->phys_sca_base = pci_resource_start(pdev,2); 3791 info->phys_memory_base = pci_resource_start(pdev,3); 3792 info->phys_statctrl_base = pci_resource_start(pdev,4); 3793 3794 /* Because veremap only works on page boundaries we must map 3795 * a larger area than is actually implemented for the LCR 3796 * memory range. We map a full page starting at the page boundary. 3797 */ 3798 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1); 3799 info->phys_lcr_base &= ~(PAGE_SIZE-1); 3800 3801 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1); 3802 info->phys_sca_base &= ~(PAGE_SIZE-1); 3803 3804 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1); 3805 info->phys_statctrl_base &= ~(PAGE_SIZE-1); 3806 3807 info->bus_type = MGSL_BUS_TYPE_PCI; 3808 info->irq_flags = IRQF_SHARED; 3809 3810 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); 3811 setup_timer(&info->status_timer, status_timeout, 3812 (unsigned long)info); 3813 3814 /* Store the PCI9050 misc control register value because a flaw 3815 * in the PCI9050 prevents LCR registers from being read if 3816 * BIOS assigns an LCR base address with bit 7 set. 3817 * 3818 * Only the misc control register is accessed for which only 3819 * write access is needed, so set an initial value and change 3820 * bits to the device instance data as we write the value 3821 * to the actual misc control register. 3822 */ 3823 info->misc_ctrl_value = 0x087e4546; 3824 3825 /* initial port state is unknown - if startup errors 3826 * occur, init_error will be set to indicate the 3827 * problem. Once the port is fully initialized, 3828 * this value will be set to 0 to indicate the 3829 * port is available. 3830 */ 3831 info->init_error = -1; 3832 } 3833 3834 return info; 3835} 3836 3837static void device_init(int adapter_num, struct pci_dev *pdev) 3838{ 3839 SLMP_INFO *port_array[SCA_MAX_PORTS]; 3840 int port; 3841 3842 /* allocate device instances for up to SCA_MAX_PORTS devices */ 3843 for ( port = 0; port < SCA_MAX_PORTS; ++port ) { 3844 port_array[port] = alloc_dev(adapter_num,port,pdev); 3845 if( port_array[port] == NULL ) { 3846 for ( --port; port >= 0; --port ) 3847 kfree(port_array[port]); 3848 return; 3849 } 3850 } 3851 3852 /* give copy of port_array to all ports and add to device list */ 3853 for ( port = 0; port < SCA_MAX_PORTS; ++port ) { 3854 memcpy(port_array[port]->port_array,port_array,sizeof(port_array)); 3855 add_device( port_array[port] ); 3856 spin_lock_init(&port_array[port]->lock); 3857 } 3858 3859 /* Allocate and claim adapter resources */ 3860 if ( !claim_resources(port_array[0]) ) { 3861 3862 alloc_dma_bufs(port_array[0]); 3863 3864 /* copy resource information from first port to others */ 3865 for ( port = 1; port < SCA_MAX_PORTS; ++port ) { 3866 port_array[port]->lock = port_array[0]->lock; 3867 port_array[port]->irq_level = port_array[0]->irq_level; 3868 port_array[port]->memory_base = port_array[0]->memory_base; 3869 port_array[port]->sca_base = port_array[0]->sca_base; 3870 port_array[port]->statctrl_base = port_array[0]->statctrl_base; 3871 port_array[port]->lcr_base = port_array[0]->lcr_base; 3872 alloc_dma_bufs(port_array[port]); 3873 } 3874 3875 if ( request_irq(port_array[0]->irq_level, 3876 synclinkmp_interrupt, 3877 port_array[0]->irq_flags, 3878 port_array[0]->device_name, 3879 port_array[0]) < 0 ) { 3880 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n", 3881 __FILE__,__LINE__, 3882 port_array[0]->device_name, 3883 port_array[0]->irq_level ); 3884 } 3885 else { 3886 port_array[0]->irq_requested = true; 3887 adapter_test(port_array[0]); 3888 } 3889 } 3890} 3891 3892static const struct tty_operations ops = { 3893 .open = open, 3894 .close = close, 3895 .write = write, 3896 .put_char = put_char, 3897 .flush_chars = flush_chars, 3898 .write_room = write_room, 3899 .chars_in_buffer = chars_in_buffer, 3900 .flush_buffer = flush_buffer, 3901 .ioctl = ioctl, 3902 .throttle = throttle, 3903 .unthrottle = unthrottle, 3904 .send_xchar = send_xchar, 3905 .break_ctl = set_break, 3906 .wait_until_sent = wait_until_sent, 3907 .set_termios = set_termios, 3908 .stop = tx_hold, 3909 .start = tx_release, 3910 .hangup = hangup, 3911 .tiocmget = tiocmget, 3912 .tiocmset = tiocmset, 3913 .proc_fops = &synclinkmp_proc_fops, 3914}; 3915 3916 3917static void synclinkmp_cleanup(void) 3918{ 3919 int rc; 3920 SLMP_INFO *info; 3921 SLMP_INFO *tmp; 3922 3923 printk("Unloading %s %s\n", driver_name, driver_version); 3924 3925 if (serial_driver) { 3926 if ((rc = tty_unregister_driver(serial_driver))) 3927 printk("%s(%d) failed to unregister tty driver err=%d\n", 3928 __FILE__,__LINE__,rc); 3929 put_tty_driver(serial_driver); 3930 } 3931 3932 /* reset devices */ 3933 info = synclinkmp_device_list; 3934 while(info) { 3935 reset_port(info); 3936 info = info->next_device; 3937 } 3938 3939 /* release devices */ 3940 info = synclinkmp_device_list; 3941 while(info) { 3942#if SYNCLINK_GENERIC_HDLC 3943 hdlcdev_exit(info); 3944#endif 3945 free_dma_bufs(info); 3946 free_tmp_rx_buf(info); 3947 if ( info->port_num == 0 ) { 3948 if (info->sca_base) 3949 write_reg(info, LPR, 1); /* set low power mode */ 3950 release_resources(info); 3951 } 3952 tmp = info; 3953 info = info->next_device; 3954 kfree(tmp); 3955 } 3956 3957 pci_unregister_driver(&synclinkmp_pci_driver); 3958} 3959 3960/* Driver initialization entry point. 3961 */ 3962 3963static int __init synclinkmp_init(void) 3964{ 3965 int rc; 3966 3967 if (break_on_load) { 3968 synclinkmp_get_text_ptr(); 3969 BREAKPOINT(); 3970 } 3971 3972 printk("%s %s\n", driver_name, driver_version); 3973 3974 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) { 3975 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc); 3976 return rc; 3977 } 3978 3979 serial_driver = alloc_tty_driver(128); 3980 if (!serial_driver) { 3981 rc = -ENOMEM; 3982 goto error; 3983 } 3984 3985 /* Initialize the tty_driver structure */ 3986 3987 serial_driver->owner = THIS_MODULE; 3988 serial_driver->driver_name = "synclinkmp"; 3989 serial_driver->name = "ttySLM"; 3990 serial_driver->major = ttymajor; 3991 serial_driver->minor_start = 64; 3992 serial_driver->type = TTY_DRIVER_TYPE_SERIAL; 3993 serial_driver->subtype = SERIAL_TYPE_NORMAL; 3994 serial_driver->init_termios = tty_std_termios; 3995 serial_driver->init_termios.c_cflag = 3996 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 3997 serial_driver->init_termios.c_ispeed = 9600; 3998 serial_driver->init_termios.c_ospeed = 9600; 3999 serial_driver->flags = TTY_DRIVER_REAL_RAW; 4000 tty_set_operations(serial_driver, &ops); 4001 if ((rc = tty_register_driver(serial_driver)) < 0) { 4002 printk("%s(%d):Couldn't register serial driver\n", 4003 __FILE__,__LINE__); 4004 put_tty_driver(serial_driver); 4005 serial_driver = NULL; 4006 goto error; 4007 } 4008 4009 printk("%s %s, tty major#%d\n", 4010 driver_name, driver_version, 4011 serial_driver->major); 4012 4013 return 0; 4014 4015error: 4016 synclinkmp_cleanup(); 4017 return rc; 4018} 4019 4020static void __exit synclinkmp_exit(void) 4021{ 4022 synclinkmp_cleanup(); 4023} 4024 4025module_init(synclinkmp_init); 4026module_exit(synclinkmp_exit); 4027 4028/* Set the port for internal loopback mode. 4029 * The TxCLK and RxCLK signals are generated from the BRG and 4030 * the TxD is looped back to the RxD internally. 4031 */ 4032static void enable_loopback(SLMP_INFO *info, int enable) 4033{ 4034 if (enable) { 4035 /* MD2 (Mode Register 2) 4036 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback 4037 */ 4038 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); 4039 4040 /* degate external TxC clock source */ 4041 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); 4042 write_control_reg(info); 4043 4044 /* RXS/TXS (Rx/Tx clock source) 4045 * 07 Reserved, must be 0 4046 * 06..04 Clock Source, 100=BRG 4047 * 03..00 Clock Divisor, 0000=1 4048 */ 4049 write_reg(info, RXS, 0x40); 4050 write_reg(info, TXS, 0x40); 4051 4052 } else { 4053 /* MD2 (Mode Register 2) 4054 * 01..00 CNCT<1..0> Channel connection, 0=normal 4055 */ 4056 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); 4057 4058 /* RXS/TXS (Rx/Tx clock source) 4059 * 07 Reserved, must be 0 4060 * 06..04 Clock Source, 000=RxC/TxC Pin 4061 * 03..00 Clock Divisor, 0000=1 4062 */ 4063 write_reg(info, RXS, 0x00); 4064 write_reg(info, TXS, 0x00); 4065 } 4066 4067 /* set LinkSpeed if available, otherwise default to 2Mbps */ 4068 if (info->params.clock_speed) 4069 set_rate(info, info->params.clock_speed); 4070 else 4071 set_rate(info, 3686400); 4072} 4073 4074/* Set the baud rate register to the desired speed 4075 * 4076 * data_rate data rate of clock in bits per second 4077 * A data rate of 0 disables the AUX clock. 4078 */ 4079static void set_rate( SLMP_INFO *info, u32 data_rate ) 4080{ 4081 u32 TMCValue; 4082 unsigned char BRValue; 4083 u32 Divisor=0; 4084 4085 /* fBRG = fCLK/(TMC * 2^BR) 4086 */ 4087 if (data_rate != 0) { 4088 Divisor = 14745600/data_rate; 4089 if (!Divisor) 4090 Divisor = 1; 4091 4092 TMCValue = Divisor; 4093 4094 BRValue = 0; 4095 if (TMCValue != 1 && TMCValue != 2) { 4096 /* BRValue of 0 provides 50/50 duty cycle *only* when 4097 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides 4098 * 50/50 duty cycle. 4099 */ 4100 BRValue = 1; 4101 TMCValue >>= 1; 4102 } 4103 4104 /* while TMCValue is too big for TMC register, divide 4105 * by 2 and increment BR exponent. 4106 */ 4107 for(; TMCValue > 256 && BRValue < 10; BRValue++) 4108 TMCValue >>= 1; 4109 4110 write_reg(info, TXS, 4111 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue)); 4112 write_reg(info, RXS, 4113 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue)); 4114 write_reg(info, TMC, (unsigned char)TMCValue); 4115 } 4116 else { 4117 write_reg(info, TXS,0); 4118 write_reg(info, RXS,0); 4119 write_reg(info, TMC, 0); 4120 } 4121} 4122 4123/* Disable receiver 4124 */ 4125static void rx_stop(SLMP_INFO *info) 4126{ 4127 if (debug_level >= DEBUG_LEVEL_ISR) 4128 printk("%s(%d):%s rx_stop()\n", 4129 __FILE__,__LINE__, info->device_name ); 4130 4131 write_reg(info, CMD, RXRESET); 4132 4133 info->ie0_value &= ~RXRDYE; 4134 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */ 4135 4136 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ 4137 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ 4138 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */ 4139 4140 info->rx_enabled = false; 4141 info->rx_overflow = false; 4142} 4143 4144/* enable the receiver 4145 */ 4146static void rx_start(SLMP_INFO *info) 4147{ 4148 int i; 4149 4150 if (debug_level >= DEBUG_LEVEL_ISR) 4151 printk("%s(%d):%s rx_start()\n", 4152 __FILE__,__LINE__, info->device_name ); 4153 4154 write_reg(info, CMD, RXRESET); 4155 4156 if ( info->params.mode == MGSL_MODE_HDLC ) { 4157 /* HDLC, disabe IRQ on rxdata */ 4158 info->ie0_value &= ~RXRDYE; 4159 write_reg(info, IE0, info->ie0_value); 4160 4161 /* Reset all Rx DMA buffers and program rx dma */ 4162 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ 4163 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ 4164 4165 for (i = 0; i < info->rx_buf_count; i++) { 4166 info->rx_buf_list[i].status = 0xff; 4167 4168 // throttle to 4 shared memory writes at a time to prevent 4169 // hogging local bus (keep latency time for DMA requests low). 4170 if (!(i % 4)) 4171 read_status_reg(info); 4172 } 4173 info->current_rx_buf = 0; 4174 4175 /* set current/1st descriptor address */ 4176 write_reg16(info, RXDMA + CDA, 4177 info->rx_buf_list_ex[0].phys_entry); 4178 4179 /* set new last rx descriptor address */ 4180 write_reg16(info, RXDMA + EDA, 4181 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry); 4182 4183 /* set buffer length (shared by all rx dma data buffers) */ 4184 write_reg16(info, RXDMA + BFL, SCABUFSIZE); 4185 4186 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */ 4187 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */ 4188 } else { 4189 /* async, enable IRQ on rxdata */ 4190 info->ie0_value |= RXRDYE; 4191 write_reg(info, IE0, info->ie0_value); 4192 } 4193 4194 write_reg(info, CMD, RXENABLE); 4195 4196 info->rx_overflow = false; 4197 info->rx_enabled = true; 4198} 4199 4200/* Enable the transmitter and send a transmit frame if 4201 * one is loaded in the DMA buffers. 4202 */ 4203static void tx_start(SLMP_INFO *info) 4204{ 4205 if (debug_level >= DEBUG_LEVEL_ISR) 4206 printk("%s(%d):%s tx_start() tx_count=%d\n", 4207 __FILE__,__LINE__, info->device_name,info->tx_count ); 4208 4209 if (!info->tx_enabled ) { 4210 write_reg(info, CMD, TXRESET); 4211 write_reg(info, CMD, TXENABLE); 4212 info->tx_enabled = true; 4213 } 4214 4215 if ( info->tx_count ) { 4216 4217 /* If auto RTS enabled and RTS is inactive, then assert */ 4218 /* RTS and set a flag indicating that the driver should */ 4219 /* negate RTS when the transmission completes. */ 4220 4221 info->drop_rts_on_tx_done = false; 4222 4223 if (info->params.mode != MGSL_MODE_ASYNC) { 4224 4225 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) { 4226 get_signals( info ); 4227 if ( !(info->serial_signals & SerialSignal_RTS) ) { 4228 info->serial_signals |= SerialSignal_RTS; 4229 set_signals( info ); 4230 info->drop_rts_on_tx_done = true; 4231 } 4232 } 4233 4234 write_reg16(info, TRC0, 4235 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level)); 4236 4237 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ 4238 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 4239 4240 /* set TX CDA (current descriptor address) */ 4241 write_reg16(info, TXDMA + CDA, 4242 info->tx_buf_list_ex[0].phys_entry); 4243 4244 /* set TX EDA (last descriptor address) */ 4245 write_reg16(info, TXDMA + EDA, 4246 info->tx_buf_list_ex[info->last_tx_buf].phys_entry); 4247 4248 /* enable underrun IRQ */ 4249 info->ie1_value &= ~IDLE; 4250 info->ie1_value |= UDRN; 4251 write_reg(info, IE1, info->ie1_value); 4252 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); 4253 4254 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */ 4255 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */ 4256 4257 mod_timer(&info->tx_timer, jiffies + 4258 msecs_to_jiffies(5000)); 4259 } 4260 else { 4261 tx_load_fifo(info); 4262 /* async, enable IRQ on txdata */ 4263 info->ie0_value |= TXRDYE; 4264 write_reg(info, IE0, info->ie0_value); 4265 } 4266 4267 info->tx_active = true; 4268 } 4269} 4270 4271/* stop the transmitter and DMA 4272 */ 4273static void tx_stop( SLMP_INFO *info ) 4274{ 4275 if (debug_level >= DEBUG_LEVEL_ISR) 4276 printk("%s(%d):%s tx_stop()\n", 4277 __FILE__,__LINE__, info->device_name ); 4278 4279 del_timer(&info->tx_timer); 4280 4281 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ 4282 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ 4283 4284 write_reg(info, CMD, TXRESET); 4285 4286 info->ie1_value &= ~(UDRN + IDLE); 4287 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ 4288 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ 4289 4290 info->ie0_value &= ~TXRDYE; 4291 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */ 4292 4293 info->tx_enabled = false; 4294 info->tx_active = false; 4295} 4296 4297/* Fill the transmit FIFO until the FIFO is full or 4298 * there is no more data to load. 4299 */ 4300static void tx_load_fifo(SLMP_INFO *info) 4301{ 4302 u8 TwoBytes[2]; 4303 4304 /* do nothing is now tx data available and no XON/XOFF pending */ 4305 4306 if ( !info->tx_count && !info->x_char ) 4307 return; 4308 4309 /* load the Transmit FIFO until FIFOs full or all data sent */ 4310 4311 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) { 4312 4313 /* there is more space in the transmit FIFO and */ 4314 /* there is more data in transmit buffer */ 4315 4316 if ( (info->tx_count > 1) && !info->x_char ) { 4317 /* write 16-bits */ 4318 TwoBytes[0] = info->tx_buf[info->tx_get++]; 4319 if (info->tx_get >= info->max_frame_size) 4320 info->tx_get -= info->max_frame_size; 4321 TwoBytes[1] = info->tx_buf[info->tx_get++]; 4322 if (info->tx_get >= info->max_frame_size) 4323 info->tx_get -= info->max_frame_size; 4324 4325 write_reg16(info, TRB, *((u16 *)TwoBytes)); 4326 4327 info->tx_count -= 2; 4328 info->icount.tx += 2; 4329 } else { 4330 /* only 1 byte left to transmit or 1 FIFO slot left */ 4331 4332 if (info->x_char) { 4333 /* transmit pending high priority char */ 4334 write_reg(info, TRB, info->x_char); 4335 info->x_char = 0; 4336 } else { 4337 write_reg(info, TRB, info->tx_buf[info->tx_get++]); 4338 if (info->tx_get >= info->max_frame_size) 4339 info->tx_get -= info->max_frame_size; 4340 info->tx_count--; 4341 } 4342 info->icount.tx++; 4343 } 4344 } 4345} 4346 4347/* Reset a port to a known state 4348 */ 4349static void reset_port(SLMP_INFO *info) 4350{ 4351 if (info->sca_base) { 4352 4353 tx_stop(info); 4354 rx_stop(info); 4355 4356 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS); 4357 set_signals(info); 4358 4359 /* disable all port interrupts */ 4360 info->ie0_value = 0; 4361 info->ie1_value = 0; 4362 info->ie2_value = 0; 4363 write_reg(info, IE0, info->ie0_value); 4364 write_reg(info, IE1, info->ie1_value); 4365 write_reg(info, IE2, info->ie2_value); 4366 4367 write_reg(info, CMD, CHRESET); 4368 } 4369} 4370 4371/* Reset all the ports to a known state. 4372 */ 4373static void reset_adapter(SLMP_INFO *info) 4374{ 4375 int i; 4376 4377 for ( i=0; i < SCA_MAX_PORTS; ++i) { 4378 if (info->port_array[i]) 4379 reset_port(info->port_array[i]); 4380 } 4381} 4382 4383/* Program port for asynchronous communications. 4384 */ 4385static void async_mode(SLMP_INFO *info) 4386{ 4387 4388 unsigned char RegValue; 4389 4390 tx_stop(info); 4391 rx_stop(info); 4392 4393 /* MD0, Mode Register 0 4394 * 4395 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async 4396 * 04 AUTO, Auto-enable (RTS/CTS/DCD) 4397 * 03 Reserved, must be 0 4398 * 02 CRCCC, CRC Calculation, 0=disabled 4399 * 01..00 STOP<1..0> Stop bits (00=1,10=2) 4400 * 4401 * 0000 0000 4402 */ 4403 RegValue = 0x00; 4404 if (info->params.stop_bits != 1) 4405 RegValue |= BIT1; 4406 write_reg(info, MD0, RegValue); 4407 4408 /* MD1, Mode Register 1 4409 * 4410 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64 4411 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5 4412 * 03..02 RXCHR<1..0>, rx char size 4413 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd 4414 * 4415 * 0100 0000 4416 */ 4417 RegValue = 0x40; 4418 switch (info->params.data_bits) { 4419 case 7: RegValue |= BIT4 + BIT2; break; 4420 case 6: RegValue |= BIT5 + BIT3; break; 4421 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; 4422 } 4423 if (info->params.parity != ASYNC_PARITY_NONE) { 4424 RegValue |= BIT1; 4425 if (info->params.parity == ASYNC_PARITY_ODD) 4426 RegValue |= BIT0; 4427 } 4428 write_reg(info, MD1, RegValue); 4429 4430 /* MD2, Mode Register 2 4431 * 4432 * 07..02 Reserved, must be 0 4433 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback 4434 * 4435 * 0000 0000 4436 */ 4437 RegValue = 0x00; 4438 if (info->params.loopback) 4439 RegValue |= (BIT1 + BIT0); 4440 write_reg(info, MD2, RegValue); 4441 4442 /* RXS, Receive clock source 4443 * 4444 * 07 Reserved, must be 0 4445 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL 4446 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4447 */ 4448 RegValue=BIT6; 4449 write_reg(info, RXS, RegValue); 4450 4451 /* TXS, Transmit clock source 4452 * 4453 * 07 Reserved, must be 0 4454 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock 4455 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4456 */ 4457 RegValue=BIT6; 4458 write_reg(info, TXS, RegValue); 4459 4460 /* Control Register 4461 * 4462 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out 4463 */ 4464 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); 4465 write_control_reg(info); 4466 4467 tx_set_idle(info); 4468 4469 /* RRC Receive Ready Control 0 4470 * 4471 * 07..05 Reserved, must be 0 4472 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte 4473 */ 4474 write_reg(info, RRC, 0x00); 4475 4476 /* TRC0 Transmit Ready Control 0 4477 * 4478 * 07..05 Reserved, must be 0 4479 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes 4480 */ 4481 write_reg(info, TRC0, 0x10); 4482 4483 /* TRC1 Transmit Ready Control 1 4484 * 4485 * 07..05 Reserved, must be 0 4486 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1) 4487 */ 4488 write_reg(info, TRC1, 0x1e); 4489 4490 /* CTL, MSCI control register 4491 * 4492 * 07..06 Reserved, set to 0 4493 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) 4494 * 04 IDLC, idle control, 0=mark 1=idle register 4495 * 03 BRK, break, 0=off 1 =on (async) 4496 * 02 SYNCLD, sync char load enable (BSC) 1=enabled 4497 * 01 GOP, go active on poll (LOOP mode) 1=enabled 4498 * 00 RTS, RTS output control, 0=active 1=inactive 4499 * 4500 * 0001 0001 4501 */ 4502 RegValue = 0x10; 4503 if (!(info->serial_signals & SerialSignal_RTS)) 4504 RegValue |= 0x01; 4505 write_reg(info, CTL, RegValue); 4506 4507 /* enable status interrupts */ 4508 info->ie0_value |= TXINTE + RXINTE; 4509 write_reg(info, IE0, info->ie0_value); 4510 4511 /* enable break detect interrupt */ 4512 info->ie1_value = BRKD; 4513 write_reg(info, IE1, info->ie1_value); 4514 4515 /* enable rx overrun interrupt */ 4516 info->ie2_value = OVRN; 4517 write_reg(info, IE2, info->ie2_value); 4518 4519 set_rate( info, info->params.data_rate * 16 ); 4520} 4521 4522/* Program the SCA for HDLC communications. 4523 */ 4524static void hdlc_mode(SLMP_INFO *info) 4525{ 4526 unsigned char RegValue; 4527 u32 DpllDivisor; 4528 4529 // Can't use DPLL because SCA outputs recovered clock on RxC when 4530 // DPLL mode selected. This causes output contention with RxC receiver. 4531 // Use of DPLL would require external hardware to disable RxC receiver 4532 // when DPLL mode selected. 4533 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL); 4534 4535 /* disable DMA interrupts */ 4536 write_reg(info, TXDMA + DIR, 0); 4537 write_reg(info, RXDMA + DIR, 0); 4538 4539 /* MD0, Mode Register 0 4540 * 4541 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC 4542 * 04 AUTO, Auto-enable (RTS/CTS/DCD) 4543 * 03 Reserved, must be 0 4544 * 02 CRCCC, CRC Calculation, 1=enabled 4545 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16 4546 * 00 CRC0, CRC initial value, 1 = all 1s 4547 * 4548 * 1000 0001 4549 */ 4550 RegValue = 0x81; 4551 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4552 RegValue |= BIT4; 4553 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4554 RegValue |= BIT4; 4555 if (info->params.crc_type == HDLC_CRC_16_CCITT) 4556 RegValue |= BIT2 + BIT1; 4557 write_reg(info, MD0, RegValue); 4558 4559 /* MD1, Mode Register 1 4560 * 4561 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check 4562 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits 4563 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits 4564 * 01..00 PMPM<1..0>, Parity mode, 00=no parity 4565 * 4566 * 0000 0000 4567 */ 4568 RegValue = 0x00; 4569 write_reg(info, MD1, RegValue); 4570 4571 /* MD2, Mode Register 2 4572 * 4573 * 07 NRZFM, 0=NRZ, 1=FM 4574 * 06..05 CODE<1..0> Encoding, 00=NRZ 4575 * 04..03 DRATE<1..0> DPLL Divisor, 00=8 4576 * 02 Reserved, must be 0 4577 * 01..00 CNCT<1..0> Channel connection, 0=normal 4578 * 4579 * 0000 0000 4580 */ 4581 RegValue = 0x00; 4582 switch(info->params.encoding) { 4583 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break; 4584 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ 4585 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ 4586 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */ 4587 } 4588 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) { 4589 DpllDivisor = 16; 4590 RegValue |= BIT3; 4591 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) { 4592 DpllDivisor = 8; 4593 } else { 4594 DpllDivisor = 32; 4595 RegValue |= BIT4; 4596 } 4597 write_reg(info, MD2, RegValue); 4598 4599 4600 /* RXS, Receive clock source 4601 * 4602 * 07 Reserved, must be 0 4603 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL 4604 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4605 */ 4606 RegValue=0; 4607 if (info->params.flags & HDLC_FLAG_RXC_BRG) 4608 RegValue |= BIT6; 4609 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4610 RegValue |= BIT6 + BIT5; 4611 write_reg(info, RXS, RegValue); 4612 4613 /* TXS, Transmit clock source 4614 * 4615 * 07 Reserved, must be 0 4616 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock 4617 * 03..00 RXBR<3..0>, rate divisor, 0000=1 4618 */ 4619 RegValue=0; 4620 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4621 RegValue |= BIT6; 4622 if (info->params.flags & HDLC_FLAG_TXC_DPLL) 4623 RegValue |= BIT6 + BIT5; 4624 write_reg(info, TXS, RegValue); 4625 4626 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4627 set_rate(info, info->params.clock_speed * DpllDivisor); 4628 else 4629 set_rate(info, info->params.clock_speed); 4630 4631 /* GPDATA (General Purpose I/O Data Register) 4632 * 4633 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out 4634 */ 4635 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4636 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); 4637 else 4638 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2)); 4639 write_control_reg(info); 4640 4641 /* RRC Receive Ready Control 0 4642 * 4643 * 07..05 Reserved, must be 0 4644 * 04..00 RRC<4..0> Rx FIFO trigger active 4645 */ 4646 write_reg(info, RRC, rx_active_fifo_level); 4647 4648 /* TRC0 Transmit Ready Control 0 4649 * 4650 * 07..05 Reserved, must be 0 4651 * 04..00 TRC<4..0> Tx FIFO trigger active 4652 */ 4653 write_reg(info, TRC0, tx_active_fifo_level); 4654 4655 /* TRC1 Transmit Ready Control 1 4656 * 4657 * 07..05 Reserved, must be 0 4658 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full) 4659 */ 4660 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1)); 4661 4662 /* DMR, DMA Mode Register 4663 * 4664 * 07..05 Reserved, must be 0 4665 * 04 TMOD, Transfer Mode: 1=chained-block 4666 * 03 Reserved, must be 0 4667 * 02 NF, Number of Frames: 1=multi-frame 4668 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled 4669 * 00 Reserved, must be 0 4670 * 4671 * 0001 0100 4672 */ 4673 write_reg(info, TXDMA + DMR, 0x14); 4674 write_reg(info, RXDMA + DMR, 0x14); 4675 4676 /* Set chain pointer base (upper 8 bits of 24 bit addr) */ 4677 write_reg(info, RXDMA + CPB, 4678 (unsigned char)(info->buffer_list_phys >> 16)); 4679 4680 /* Set chain pointer base (upper 8 bits of 24 bit addr) */ 4681 write_reg(info, TXDMA + CPB, 4682 (unsigned char)(info->buffer_list_phys >> 16)); 4683 4684 /* enable status interrupts. other code enables/disables 4685 * the individual sources for these two interrupt classes. 4686 */ 4687 info->ie0_value |= TXINTE + RXINTE; 4688 write_reg(info, IE0, info->ie0_value); 4689 4690 /* CTL, MSCI control register 4691 * 4692 * 07..06 Reserved, set to 0 4693 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) 4694 * 04 IDLC, idle control, 0=mark 1=idle register 4695 * 03 BRK, break, 0=off 1 =on (async) 4696 * 02 SYNCLD, sync char load enable (BSC) 1=enabled 4697 * 01 GOP, go active on poll (LOOP mode) 1=enabled 4698 * 00 RTS, RTS output control, 0=active 1=inactive 4699 * 4700 * 0001 0001 4701 */ 4702 RegValue = 0x10; 4703 if (!(info->serial_signals & SerialSignal_RTS)) 4704 RegValue |= 0x01; 4705 write_reg(info, CTL, RegValue); 4706 4707 /* preamble not supported ! */ 4708 4709 tx_set_idle(info); 4710 tx_stop(info); 4711 rx_stop(info); 4712 4713 set_rate(info, info->params.clock_speed); 4714 4715 if (info->params.loopback) 4716 enable_loopback(info,1); 4717} 4718 4719/* Set the transmit HDLC idle mode 4720 */ 4721static void tx_set_idle(SLMP_INFO *info) 4722{ 4723 unsigned char RegValue = 0xff; 4724 4725 /* Map API idle mode to SCA register bits */ 4726 switch(info->idle_mode) { 4727 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break; 4728 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break; 4729 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break; 4730 case HDLC_TXIDLE_ONES: RegValue = 0xff; break; 4731 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break; 4732 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break; 4733 case HDLC_TXIDLE_MARK: RegValue = 0xff; break; 4734 } 4735 4736 write_reg(info, IDL, RegValue); 4737} 4738 4739/* Query the adapter for the state of the V24 status (input) signals. 4740 */ 4741static void get_signals(SLMP_INFO *info) 4742{ 4743 u16 status = read_reg(info, SR3); 4744 u16 gpstatus = read_status_reg(info); 4745 u16 testbit; 4746 4747 /* clear all serial signals except DTR and RTS */ 4748 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS; 4749 4750 /* set serial signal bits to reflect MISR */ 4751 4752 if (!(status & BIT3)) 4753 info->serial_signals |= SerialSignal_CTS; 4754 4755 if ( !(status & BIT2)) 4756 info->serial_signals |= SerialSignal_DCD; 4757 4758 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7> 4759 if (!(gpstatus & testbit)) 4760 info->serial_signals |= SerialSignal_RI; 4761 4762 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6> 4763 if (!(gpstatus & testbit)) 4764 info->serial_signals |= SerialSignal_DSR; 4765} 4766 4767/* Set the state of DTR and RTS based on contents of 4768 * serial_signals member of device context. 4769 */ 4770static void set_signals(SLMP_INFO *info) 4771{ 4772 unsigned char RegValue; 4773 u16 EnableBit; 4774 4775 RegValue = read_reg(info, CTL); 4776 if (info->serial_signals & SerialSignal_RTS) 4777 RegValue &= ~BIT0; 4778 else 4779 RegValue |= BIT0; 4780 write_reg(info, CTL, RegValue); 4781 4782 // Port 0..3 DTR is ctrl reg <1,3,5,7> 4783 EnableBit = BIT1 << (info->port_num*2); 4784 if (info->serial_signals & SerialSignal_DTR) 4785 info->port_array[0]->ctrlreg_value &= ~EnableBit; 4786 else 4787 info->port_array[0]->ctrlreg_value |= EnableBit; 4788 write_control_reg(info); 4789} 4790 4791/*******************/ 4792/* DMA Buffer Code */ 4793/*******************/ 4794 4795/* Set the count for all receive buffers to SCABUFSIZE 4796 * and set the current buffer to the first buffer. This effectively 4797 * makes all buffers free and discards any data in buffers. 4798 */ 4799static void rx_reset_buffers(SLMP_INFO *info) 4800{ 4801 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1); 4802} 4803 4804/* Free the buffers used by a received frame 4805 * 4806 * info pointer to device instance data 4807 * first index of 1st receive buffer of frame 4808 * last index of last receive buffer of frame 4809 */ 4810static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last) 4811{ 4812 bool done = false; 4813 4814 while(!done) { 4815 /* reset current buffer for reuse */ 4816 info->rx_buf_list[first].status = 0xff; 4817 4818 if (first == last) { 4819 done = true; 4820 /* set new last rx descriptor address */ 4821 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry); 4822 } 4823 4824 first++; 4825 if (first == info->rx_buf_count) 4826 first = 0; 4827 } 4828 4829 /* set current buffer to next buffer after last buffer of frame */ 4830 info->current_rx_buf = first; 4831} 4832 4833/* Return a received frame from the receive DMA buffers. 4834 * Only frames received without errors are returned. 4835 * 4836 * Return Value: true if frame returned, otherwise false 4837 */ 4838static bool rx_get_frame(SLMP_INFO *info) 4839{ 4840 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */ 4841 unsigned short status; 4842 unsigned int framesize = 0; 4843 bool ReturnCode = false; 4844 unsigned long flags; 4845 struct tty_struct *tty = info->port.tty; 4846 unsigned char addr_field = 0xff; 4847 SCADESC *desc; 4848 SCADESC_EX *desc_ex; 4849 4850CheckAgain: 4851 /* assume no frame returned, set zero length */ 4852 framesize = 0; 4853 addr_field = 0xff; 4854 4855 /* 4856 * current_rx_buf points to the 1st buffer of the next available 4857 * receive frame. To find the last buffer of the frame look for 4858 * a non-zero status field in the buffer entries. (The status 4859 * field is set by the 16C32 after completing a receive frame. 4860 */ 4861 StartIndex = EndIndex = info->current_rx_buf; 4862 4863 for ( ;; ) { 4864 desc = &info->rx_buf_list[EndIndex]; 4865 desc_ex = &info->rx_buf_list_ex[EndIndex]; 4866 4867 if (desc->status == 0xff) 4868 goto Cleanup; /* current desc still in use, no frames available */ 4869 4870 if (framesize == 0 && info->params.addr_filter != 0xff) 4871 addr_field = desc_ex->virt_addr[0]; 4872 4873 framesize += desc->length; 4874 4875 /* Status != 0 means last buffer of frame */ 4876 if (desc->status) 4877 break; 4878 4879 EndIndex++; 4880 if (EndIndex == info->rx_buf_count) 4881 EndIndex = 0; 4882 4883 if (EndIndex == info->current_rx_buf) { 4884 /* all buffers have been 'used' but none mark */ 4885 /* the end of a frame. Reset buffers and receiver. */ 4886 if ( info->rx_enabled ){ 4887 spin_lock_irqsave(&info->lock,flags); 4888 rx_start(info); 4889 spin_unlock_irqrestore(&info->lock,flags); 4890 } 4891 goto Cleanup; 4892 } 4893 4894 } 4895 4896 /* check status of receive frame */ 4897 4898 /* frame status is byte stored after frame data 4899 * 4900 * 7 EOM (end of msg), 1 = last buffer of frame 4901 * 6 Short Frame, 1 = short frame 4902 * 5 Abort, 1 = frame aborted 4903 * 4 Residue, 1 = last byte is partial 4904 * 3 Overrun, 1 = overrun occurred during frame reception 4905 * 2 CRC, 1 = CRC error detected 4906 * 4907 */ 4908 status = desc->status; 4909 4910 /* ignore CRC bit if not using CRC (bit is undefined) */ 4911 /* Note:CRC is not save to data buffer */ 4912 if (info->params.crc_type == HDLC_CRC_NONE) 4913 status &= ~BIT2; 4914 4915 if (framesize == 0 || 4916 (addr_field != 0xff && addr_field != info->params.addr_filter)) { 4917 /* discard 0 byte frames, this seems to occur sometime 4918 * when remote is idling flags. 4919 */ 4920 rx_free_frame_buffers(info, StartIndex, EndIndex); 4921 goto CheckAgain; 4922 } 4923 4924 if (framesize < 2) 4925 status |= BIT6; 4926 4927 if (status & (BIT6+BIT5+BIT3+BIT2)) { 4928 /* received frame has errors, 4929 * update counts and mark frame size as 0 4930 */ 4931 if (status & BIT6) 4932 info->icount.rxshort++; 4933 else if (status & BIT5) 4934 info->icount.rxabort++; 4935 else if (status & BIT3) 4936 info->icount.rxover++; 4937 else 4938 info->icount.rxcrc++; 4939 4940 framesize = 0; 4941#if SYNCLINK_GENERIC_HDLC 4942 { 4943 info->netdev->stats.rx_errors++; 4944 info->netdev->stats.rx_frame_errors++; 4945 } 4946#endif 4947 } 4948 4949 if ( debug_level >= DEBUG_LEVEL_BH ) 4950 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n", 4951 __FILE__,__LINE__,info->device_name,status,framesize); 4952 4953 if ( debug_level >= DEBUG_LEVEL_DATA ) 4954 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr, 4955 min_t(int, framesize,SCABUFSIZE),0); 4956 4957 if (framesize) { 4958 if (framesize > info->max_frame_size) 4959 info->icount.rxlong++; 4960 else { 4961 /* copy dma buffer(s) to contiguous intermediate buffer */ 4962 int copy_count = framesize; 4963 int index = StartIndex; 4964 unsigned char *ptmp = info->tmp_rx_buf; 4965 info->tmp_rx_buf_count = framesize; 4966 4967 info->icount.rxok++; 4968 4969 while(copy_count) { 4970 int partial_count = min(copy_count,SCABUFSIZE); 4971 memcpy( ptmp, 4972 info->rx_buf_list_ex[index].virt_addr, 4973 partial_count ); 4974 ptmp += partial_count; 4975 copy_count -= partial_count; 4976 4977 if ( ++index == info->rx_buf_count ) 4978 index = 0; 4979 } 4980 4981#if SYNCLINK_GENERIC_HDLC 4982 if (info->netcount) 4983 hdlcdev_rx(info,info->tmp_rx_buf,framesize); 4984 else 4985#endif 4986 ldisc_receive_buf(tty,info->tmp_rx_buf, 4987 info->flag_buf, framesize); 4988 } 4989 } 4990 /* Free the buffers used by this frame. */ 4991 rx_free_frame_buffers( info, StartIndex, EndIndex ); 4992 4993 ReturnCode = true; 4994 4995Cleanup: 4996 if ( info->rx_enabled && info->rx_overflow ) { 4997 /* Receiver is enabled, but needs to restarted due to 4998 * rx buffer overflow. If buffers are empty, restart receiver. 4999 */ 5000 if (info->rx_buf_list[EndIndex].status == 0xff) { 5001 spin_lock_irqsave(&info->lock,flags); 5002 rx_start(info); 5003 spin_unlock_irqrestore(&info->lock,flags); 5004 } 5005 } 5006 5007 return ReturnCode; 5008} 5009 5010/* load the transmit DMA buffer with data 5011 */ 5012static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count) 5013{ 5014 unsigned short copy_count; 5015 unsigned int i = 0; 5016 SCADESC *desc; 5017 SCADESC_EX *desc_ex; 5018 5019 if ( debug_level >= DEBUG_LEVEL_DATA ) 5020 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1); 5021 5022 /* Copy source buffer to one or more DMA buffers, starting with 5023 * the first transmit dma buffer. 5024 */ 5025 for(i=0;;) 5026 { 5027 copy_count = min_t(unsigned short,count,SCABUFSIZE); 5028 5029 desc = &info->tx_buf_list[i]; 5030 desc_ex = &info->tx_buf_list_ex[i]; 5031 5032 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count); 5033 5034 desc->length = copy_count; 5035 desc->status = 0; 5036 5037 buf += copy_count; 5038 count -= copy_count; 5039 5040 if (!count) 5041 break; 5042 5043 i++; 5044 if (i >= info->tx_buf_count) 5045 i = 0; 5046 } 5047 5048 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */ 5049 info->last_tx_buf = ++i; 5050} 5051 5052static bool register_test(SLMP_INFO *info) 5053{ 5054 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96}; 5055 static unsigned int count = ARRAY_SIZE(testval); 5056 unsigned int i; 5057 bool rc = true; 5058 unsigned long flags; 5059 5060 spin_lock_irqsave(&info->lock,flags); 5061 reset_port(info); 5062 5063 /* assume failure */ 5064 info->init_error = DiagStatus_AddressFailure; 5065 5066 /* Write bit patterns to various registers but do it out of */ 5067 /* sync, then read back and verify values. */ 5068 5069 for (i = 0 ; i < count ; i++) { 5070 write_reg(info, TMC, testval[i]); 5071 write_reg(info, IDL, testval[(i+1)%count]); 5072 write_reg(info, SA0, testval[(i+2)%count]); 5073 write_reg(info, SA1, testval[(i+3)%count]); 5074 5075 if ( (read_reg(info, TMC) != testval[i]) || 5076 (read_reg(info, IDL) != testval[(i+1)%count]) || 5077 (read_reg(info, SA0) != testval[(i+2)%count]) || 5078 (read_reg(info, SA1) != testval[(i+3)%count]) ) 5079 { 5080 rc = false; 5081 break; 5082 } 5083 } 5084 5085 reset_port(info); 5086 spin_unlock_irqrestore(&info->lock,flags); 5087 5088 return rc; 5089} 5090 5091static bool irq_test(SLMP_INFO *info) 5092{ 5093 unsigned long timeout; 5094 unsigned long flags; 5095 5096 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; 5097 5098 spin_lock_irqsave(&info->lock,flags); 5099 reset_port(info); 5100 5101 /* assume failure */ 5102 info->init_error = DiagStatus_IrqFailure; 5103 info->irq_occurred = false; 5104 5105 /* setup timer0 on SCA0 to interrupt */ 5106 5107 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */ 5108 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); 5109 5110 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */ 5111 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */ 5112 5113 5114 /* TMCS, Timer Control/Status Register 5115 * 5116 * 07 CMF, Compare match flag (read only) 1=match 5117 * 06 ECMI, CMF Interrupt Enable: 1=enabled 5118 * 05 Reserved, must be 0 5119 * 04 TME, Timer Enable 5120 * 03..00 Reserved, must be 0 5121 * 5122 * 0101 0000 5123 */ 5124 write_reg(info, (unsigned char)(timer + TMCS), 0x50); 5125 5126 spin_unlock_irqrestore(&info->lock,flags); 5127 5128 timeout=100; 5129 while( timeout-- && !info->irq_occurred ) { 5130 msleep_interruptible(10); 5131 } 5132 5133 spin_lock_irqsave(&info->lock,flags); 5134 reset_port(info); 5135 spin_unlock_irqrestore(&info->lock,flags); 5136 5137 return info->irq_occurred; 5138} 5139 5140/* initialize individual SCA device (2 ports) 5141 */ 5142static bool sca_init(SLMP_INFO *info) 5143{ 5144 /* set wait controller to single mem partition (low), no wait states */ 5145 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */ 5146 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */ 5147 write_reg(info, WCRL, 0); /* wait controller low range */ 5148 write_reg(info, WCRM, 0); /* wait controller mid range */ 5149 write_reg(info, WCRH, 0); /* wait controller high range */ 5150 5151 /* DPCR, DMA Priority Control 5152 * 5153 * 07..05 Not used, must be 0 5154 * 04 BRC, bus release condition: 0=all transfers complete 5155 * 03 CCC, channel change condition: 0=every cycle 5156 * 02..00 PR<2..0>, priority 100=round robin 5157 * 5158 * 00000100 = 0x04 5159 */ 5160 write_reg(info, DPCR, dma_priority); 5161 5162 /* DMA Master Enable, BIT7: 1=enable all channels */ 5163 write_reg(info, DMER, 0x80); 5164 5165 /* enable all interrupt classes */ 5166 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */ 5167 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */ 5168 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */ 5169 5170 /* ITCR, interrupt control register 5171 * 07 IPC, interrupt priority, 0=MSCI->DMA 5172 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle 5173 * 04 VOS, Vector Output, 0=unmodified vector 5174 * 03..00 Reserved, must be 0 5175 */ 5176 write_reg(info, ITCR, 0); 5177 5178 return true; 5179} 5180 5181/* initialize adapter hardware 5182 */ 5183static bool init_adapter(SLMP_INFO *info) 5184{ 5185 int i; 5186 5187 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */ 5188 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50); 5189 u32 readval; 5190 5191 info->misc_ctrl_value |= BIT30; 5192 *MiscCtrl = info->misc_ctrl_value; 5193 5194 /* 5195 * Force at least 170ns delay before clearing 5196 * reset bit. Each read from LCR takes at least 5197 * 30ns so 10 times for 300ns to be safe. 5198 */ 5199 for(i=0;i<10;i++) 5200 readval = *MiscCtrl; 5201 5202 info->misc_ctrl_value &= ~BIT30; 5203 *MiscCtrl = info->misc_ctrl_value; 5204 5205 /* init control reg (all DTRs off, all clksel=input) */ 5206 info->ctrlreg_value = 0xaa; 5207 write_control_reg(info); 5208 5209 { 5210 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c); 5211 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3); 5212 5213 switch(read_ahead_count) 5214 { 5215 case 16: 5216 lcr1_brdr_value |= BIT5 + BIT4 + BIT3; 5217 break; 5218 case 8: 5219 lcr1_brdr_value |= BIT5 + BIT4; 5220 break; 5221 case 4: 5222 lcr1_brdr_value |= BIT5 + BIT3; 5223 break; 5224 case 0: 5225 lcr1_brdr_value |= BIT5; 5226 break; 5227 } 5228 5229 *LCR1BRDR = lcr1_brdr_value; 5230 *MiscCtrl = misc_ctrl_value; 5231 } 5232 5233 sca_init(info->port_array[0]); 5234 sca_init(info->port_array[2]); 5235 5236 return true; 5237} 5238 5239/* Loopback an HDLC frame to test the hardware 5240 * interrupt and DMA functions. 5241 */ 5242static bool loopback_test(SLMP_INFO *info) 5243{ 5244#define TESTFRAMESIZE 20 5245 5246 unsigned long timeout; 5247 u16 count = TESTFRAMESIZE; 5248 unsigned char buf[TESTFRAMESIZE]; 5249 bool rc = false; 5250 unsigned long flags; 5251 5252 struct tty_struct *oldtty = info->port.tty; 5253 u32 speed = info->params.clock_speed; 5254 5255 info->params.clock_speed = 3686400; 5256 info->port.tty = NULL; 5257 5258 /* assume failure */ 5259 info->init_error = DiagStatus_DmaFailure; 5260 5261 /* build and send transmit frame */ 5262 for (count = 0; count < TESTFRAMESIZE;++count) 5263 buf[count] = (unsigned char)count; 5264 5265 memset(info->tmp_rx_buf,0,TESTFRAMESIZE); 5266 5267 /* program hardware for HDLC and enabled receiver */ 5268 spin_lock_irqsave(&info->lock,flags); 5269 hdlc_mode(info); 5270 enable_loopback(info,1); 5271 rx_start(info); 5272 info->tx_count = count; 5273 tx_load_dma_buffer(info,buf,count); 5274 tx_start(info); 5275 spin_unlock_irqrestore(&info->lock,flags); 5276 5277 /* wait for receive complete */ 5278 /* Set a timeout for waiting for interrupt. */ 5279 for ( timeout = 100; timeout; --timeout ) { 5280 msleep_interruptible(10); 5281 5282 if (rx_get_frame(info)) { 5283 rc = true; 5284 break; 5285 } 5286 } 5287 5288 /* verify received frame length and contents */ 5289 if (rc && 5290 ( info->tmp_rx_buf_count != count || 5291 memcmp(buf, info->tmp_rx_buf,count))) { 5292 rc = false; 5293 } 5294 5295 spin_lock_irqsave(&info->lock,flags); 5296 reset_adapter(info); 5297 spin_unlock_irqrestore(&info->lock,flags); 5298 5299 info->params.clock_speed = speed; 5300 info->port.tty = oldtty; 5301 5302 return rc; 5303} 5304 5305/* Perform diagnostics on hardware 5306 */ 5307static int adapter_test( SLMP_INFO *info ) 5308{ 5309 unsigned long flags; 5310 if ( debug_level >= DEBUG_LEVEL_INFO ) 5311 printk( "%s(%d):Testing device %s\n", 5312 __FILE__,__LINE__,info->device_name ); 5313 5314 spin_lock_irqsave(&info->lock,flags); 5315 init_adapter(info); 5316 spin_unlock_irqrestore(&info->lock,flags); 5317 5318 info->port_array[0]->port_count = 0; 5319 5320 if ( register_test(info->port_array[0]) && 5321 register_test(info->port_array[1])) { 5322 5323 info->port_array[0]->port_count = 2; 5324 5325 if ( register_test(info->port_array[2]) && 5326 register_test(info->port_array[3]) ) 5327 info->port_array[0]->port_count += 2; 5328 } 5329 else { 5330 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n", 5331 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base)); 5332 return -ENODEV; 5333 } 5334 5335 if ( !irq_test(info->port_array[0]) || 5336 !irq_test(info->port_array[1]) || 5337 (info->port_count == 4 && !irq_test(info->port_array[2])) || 5338 (info->port_count == 4 && !irq_test(info->port_array[3]))) { 5339 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n", 5340 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) ); 5341 return -ENODEV; 5342 } 5343 5344 if (!loopback_test(info->port_array[0]) || 5345 !loopback_test(info->port_array[1]) || 5346 (info->port_count == 4 && !loopback_test(info->port_array[2])) || 5347 (info->port_count == 4 && !loopback_test(info->port_array[3]))) { 5348 printk( "%s(%d):DMA test failure for device %s\n", 5349 __FILE__,__LINE__,info->device_name); 5350 return -ENODEV; 5351 } 5352 5353 if ( debug_level >= DEBUG_LEVEL_INFO ) 5354 printk( "%s(%d):device %s passed diagnostics\n", 5355 __FILE__,__LINE__,info->device_name ); 5356 5357 info->port_array[0]->init_error = 0; 5358 info->port_array[1]->init_error = 0; 5359 if ( info->port_count > 2 ) { 5360 info->port_array[2]->init_error = 0; 5361 info->port_array[3]->init_error = 0; 5362 } 5363 5364 return 0; 5365} 5366 5367/* Test the shared memory on a PCI adapter. 5368 */ 5369static bool memory_test(SLMP_INFO *info) 5370{ 5371 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa, 5372 0x66666666, 0x99999999, 0xffffffff, 0x12345678 }; 5373 unsigned long count = ARRAY_SIZE(testval); 5374 unsigned long i; 5375 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long); 5376 unsigned long * addr = (unsigned long *)info->memory_base; 5377 5378 /* Test data lines with test pattern at one location. */ 5379 5380 for ( i = 0 ; i < count ; i++ ) { 5381 *addr = testval[i]; 5382 if ( *addr != testval[i] ) 5383 return false; 5384 } 5385 5386 /* Test address lines with incrementing pattern over */ 5387 /* entire address range. */ 5388 5389 for ( i = 0 ; i < limit ; i++ ) { 5390 *addr = i * 4; 5391 addr++; 5392 } 5393 5394 addr = (unsigned long *)info->memory_base; 5395 5396 for ( i = 0 ; i < limit ; i++ ) { 5397 if ( *addr != i * 4 ) 5398 return false; 5399 addr++; 5400 } 5401 5402 memset( info->memory_base, 0, SCA_MEM_SIZE ); 5403 return true; 5404} 5405 5406/* Load data into PCI adapter shared memory. 5407 * 5408 * The PCI9050 releases control of the local bus 5409 * after completing the current read or write operation. 5410 * 5411 * While the PCI9050 write FIFO not empty, the 5412 * PCI9050 treats all of the writes as a single transaction 5413 * and does not release the bus. This causes DMA latency problems 5414 * at high speeds when copying large data blocks to the shared memory. 5415 * 5416 * This function breaks a write into multiple transations by 5417 * interleaving a read which flushes the write FIFO and 'completes' 5418 * the write transation. This allows any pending DMA request to gain control 5419 * of the local bus in a timely fasion. 5420 */ 5421static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count) 5422{ 5423 /* A load interval of 16 allows for 4 32-bit writes at */ 5424 /* 136ns each for a maximum latency of 542ns on the local bus.*/ 5425 5426 unsigned short interval = count / sca_pci_load_interval; 5427 unsigned short i; 5428 5429 for ( i = 0 ; i < interval ; i++ ) 5430 { 5431 memcpy(dest, src, sca_pci_load_interval); 5432 read_status_reg(info); 5433 dest += sca_pci_load_interval; 5434 src += sca_pci_load_interval; 5435 } 5436 5437 memcpy(dest, src, count % sca_pci_load_interval); 5438} 5439 5440static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit) 5441{ 5442 int i; 5443 int linecount; 5444 if (xmit) 5445 printk("%s tx data:\n",info->device_name); 5446 else 5447 printk("%s rx data:\n",info->device_name); 5448 5449 while(count) { 5450 if (count > 16) 5451 linecount = 16; 5452 else 5453 linecount = count; 5454 5455 for(i=0;i<linecount;i++) 5456 printk("%02X ",(unsigned char)data[i]); 5457 for(;i<17;i++) 5458 printk(" "); 5459 for(i=0;i<linecount;i++) { 5460 if (data[i]>=040 && data[i]<=0176) 5461 printk("%c",data[i]); 5462 else 5463 printk("."); 5464 } 5465 printk("\n"); 5466 5467 data += linecount; 5468 count -= linecount; 5469 } 5470} /* end of trace_block() */ 5471 5472/* called when HDLC frame times out 5473 * update stats and do tx completion processing 5474 */ 5475static void tx_timeout(unsigned long context) 5476{ 5477 SLMP_INFO *info = (SLMP_INFO*)context; 5478 unsigned long flags; 5479 5480 if ( debug_level >= DEBUG_LEVEL_INFO ) 5481 printk( "%s(%d):%s tx_timeout()\n", 5482 __FILE__,__LINE__,info->device_name); 5483 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { 5484 info->icount.txtimeout++; 5485 } 5486 spin_lock_irqsave(&info->lock,flags); 5487 info->tx_active = false; 5488 info->tx_count = info->tx_put = info->tx_get = 0; 5489 5490 spin_unlock_irqrestore(&info->lock,flags); 5491 5492#if SYNCLINK_GENERIC_HDLC 5493 if (info->netcount) 5494 hdlcdev_tx_done(info); 5495 else 5496#endif 5497 bh_transmit(info); 5498} 5499 5500/* called to periodically check the DSR/RI modem signal input status 5501 */ 5502static void status_timeout(unsigned long context) 5503{ 5504 u16 status = 0; 5505 SLMP_INFO *info = (SLMP_INFO*)context; 5506 unsigned long flags; 5507 unsigned char delta; 5508 5509 5510 spin_lock_irqsave(&info->lock,flags); 5511 get_signals(info); 5512 spin_unlock_irqrestore(&info->lock,flags); 5513 5514 /* check for DSR/RI state change */ 5515 5516 delta = info->old_signals ^ info->serial_signals; 5517 info->old_signals = info->serial_signals; 5518 5519 if (delta & SerialSignal_DSR) 5520 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR); 5521 5522 if (delta & SerialSignal_RI) 5523 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI); 5524 5525 if (delta & SerialSignal_DCD) 5526 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD); 5527 5528 if (delta & SerialSignal_CTS) 5529 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS); 5530 5531 if (status) 5532 isr_io_pin(info,status); 5533 5534 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); 5535} 5536 5537 5538/* Register Access Routines - 5539 * All registers are memory mapped 5540 */ 5541#define CALC_REGADDR() \ 5542 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ 5543 if (info->port_num > 1) \ 5544 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \ 5545 if ( info->port_num & 1) { \ 5546 if (Addr > 0x7f) \ 5547 RegAddr += 0x40; /* DMA access */ \ 5548 else if (Addr > 0x1f && Addr < 0x60) \ 5549 RegAddr += 0x20; /* MSCI access */ \ 5550 } 5551 5552 5553static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr) 5554{ 5555 CALC_REGADDR(); 5556 return *RegAddr; 5557} 5558static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value) 5559{ 5560 CALC_REGADDR(); 5561 *RegAddr = Value; 5562} 5563 5564static u16 read_reg16(SLMP_INFO * info, unsigned char Addr) 5565{ 5566 CALC_REGADDR(); 5567 return *((u16 *)RegAddr); 5568} 5569 5570static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value) 5571{ 5572 CALC_REGADDR(); 5573 *((u16 *)RegAddr) = Value; 5574} 5575 5576static unsigned char read_status_reg(SLMP_INFO * info) 5577{ 5578 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; 5579 return *RegAddr; 5580} 5581 5582static void write_control_reg(SLMP_INFO * info) 5583{ 5584 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; 5585 *RegAddr = info->port_array[0]->ctrlreg_value; 5586} 5587 5588 5589static int __devinit synclinkmp_init_one (struct pci_dev *dev, 5590 const struct pci_device_id *ent) 5591{ 5592 if (pci_enable_device(dev)) { 5593 printk("error enabling pci device %p\n", dev); 5594 return -EIO; 5595 } 5596 device_init( ++synclinkmp_adapter_count, dev ); 5597 return 0; 5598} 5599 5600static void __devexit synclinkmp_remove_one (struct pci_dev *dev) 5601{ 5602} 5603