1/* 2 * pata_via.c - VIA PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * 5 * Documentation 6 * Most chipset documentation available under NDA only 7 * 8 * VIA version guide 9 * VIA VT82C561 - early design, uses ata_generic currently 10 * VIA VT82C576 - MWDMA, 33Mhz 11 * VIA VT82C586 - MWDMA, 33Mhz 12 * VIA VT82C586a - Added UDMA to 33Mhz 13 * VIA VT82C586b - UDMA33 14 * VIA VT82C596a - Nonfunctional UDMA66 15 * VIA VT82C596b - Working UDMA66 16 * VIA VT82C686 - Nonfunctional UDMA66 17 * VIA VT82C686a - Working UDMA66 18 * VIA VT82C686b - Updated to UDMA100 19 * VIA VT8231 - UDMA100 20 * VIA VT8233 - UDMA100 21 * VIA VT8233a - UDMA133 22 * VIA VT8233c - UDMA100 23 * VIA VT8235 - UDMA133 24 * VIA VT8237 - UDMA133 25 * VIA VT8237A - UDMA133 26 * VIA VT8237S - UDMA133 27 * VIA VT8251 - UDMA133 28 * 29 * Most registers remain compatible across chips. Others start reserved 30 * and acquire sensible semantics if set to 1 (eg cable detect). A few 31 * exceptions exist, notably around the FIFO settings. 32 * 33 * One additional quirk of the VIA design is that like ALi they use few 34 * PCI IDs for a lot of chips. 35 * 36 * Based heavily on: 37 * 38 * Version 3.38 39 * 40 * VIA IDE driver for Linux. Supported southbridges: 41 * 42 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, 43 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, 44 * vt8235, vt8237 45 * 46 * Copyright (c) 2000-2002 Vojtech Pavlik 47 * 48 * Based on the work of: 49 * Michel Aubry 50 * Jeff Garzik 51 * Andre Hedrick 52 53 */ 54 55#include <linux/kernel.h> 56#include <linux/module.h> 57#include <linux/pci.h> 58#include <linux/init.h> 59#include <linux/blkdev.h> 60#include <linux/delay.h> 61#include <linux/gfp.h> 62#include <scsi/scsi_host.h> 63#include <linux/libata.h> 64#include <linux/dmi.h> 65 66#define DRV_NAME "pata_via" 67#define DRV_VERSION "0.3.4" 68 69enum { 70 VIA_BAD_PREQ = 0x01, /* Crashes if PREQ# till DDACK# set */ 71 VIA_BAD_CLK66 = 0x02, /* 66 MHz clock doesn't work correctly */ 72 VIA_SET_FIFO = 0x04, /* Needs to have FIFO split set */ 73 VIA_NO_UNMASK = 0x08, /* Doesn't work with IRQ unmasking on */ 74 VIA_BAD_ID = 0x10, /* Has wrong vendor ID (0x1107) */ 75 VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */ 76 VIA_NO_ENABLES = 0x40, /* Has no enablebits */ 77 VIA_SATA_PATA = 0x80, /* SATA/PATA combined configuration */ 78}; 79 80enum { 81 VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */ 82}; 83 84/* 85 * VIA SouthBridge chips. 86 */ 87 88static const struct via_isa_bridge { 89 const char *name; 90 u16 id; 91 u8 rev_min; 92 u8 rev_max; 93 u8 udma_mask; 94 u8 flags; 95} via_isa_bridges[] = { 96 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, 97 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, 98 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 99 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 100 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 101 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, 102 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES }, 103 { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES }, 104 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 105 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 106 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 107 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 108 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, }, 109 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, }, 110 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, }, 111 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, }, 112 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, }, 113 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, 114 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, }, 115 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, 116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO }, 117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ }, 118 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO }, 119 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO }, 120 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, 121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, 122 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, 123 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, 124 { NULL } 125}; 126 127struct via_port { 128 u8 cached_device; 129}; 130 131/* 132 * Cable special cases 133 */ 134 135static const struct dmi_system_id cable_dmi_table[] = { 136 { 137 .ident = "Acer Ferrari 3400", 138 .matches = { 139 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), 140 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), 141 }, 142 }, 143 { } 144}; 145 146static int via_cable_override(struct pci_dev *pdev) 147{ 148 /* Systems by DMI */ 149 if (dmi_check_system(cable_dmi_table)) 150 return 1; 151 /* Arima W730-K8/Targa Visionary 811/... */ 152 if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032) 153 return 1; 154 return 0; 155} 156 157 158/** 159 * via_cable_detect - cable detection 160 * @ap: ATA port 161 * 162 * Perform cable detection. Actually for the VIA case the BIOS 163 * already did this for us. We read the values provided by the 164 * BIOS. If you are using an 8235 in a non-PC configuration you 165 * may need to update this code. 166 * 167 * Hotplug also impacts on this. 168 */ 169 170static int via_cable_detect(struct ata_port *ap) { 171 const struct via_isa_bridge *config = ap->host->private_data; 172 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 173 u32 ata66; 174 175 if (via_cable_override(pdev)) 176 return ATA_CBL_PATA40_SHORT; 177 178 if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0) 179 return ATA_CBL_SATA; 180 181 /* Early chips are 40 wire */ 182 if (config->udma_mask < ATA_UDMA4) 183 return ATA_CBL_PATA40; 184 /* UDMA 66 chips have only drive side logic */ 185 else if (config->udma_mask < ATA_UDMA5) 186 return ATA_CBL_PATA_UNK; 187 /* UDMA 100 or later */ 188 pci_read_config_dword(pdev, 0x50, &ata66); 189 /* Check both the drive cable reporting bits, we might not have 190 two drives */ 191 if (ata66 & (0x10100000 >> (16 * ap->port_no))) 192 return ATA_CBL_PATA80; 193 /* Check with ACPI so we can spot BIOS reported SATA bridges */ 194 if (ata_acpi_init_gtm(ap) && 195 ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap))) 196 return ATA_CBL_PATA80; 197 return ATA_CBL_PATA40; 198} 199 200static int via_pre_reset(struct ata_link *link, unsigned long deadline) 201{ 202 struct ata_port *ap = link->ap; 203 const struct via_isa_bridge *config = ap->host->private_data; 204 205 if (!(config->flags & VIA_NO_ENABLES)) { 206 static const struct pci_bits via_enable_bits[] = { 207 { 0x40, 1, 0x02, 0x02 }, 208 { 0x40, 1, 0x01, 0x01 } 209 }; 210 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 211 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) 212 return -ENOENT; 213 } 214 215 return ata_sff_prereset(link, deadline); 216} 217 218 219 220static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, 221 int mode, int set_ast, int udma_type) 222{ 223 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 224 struct ata_device *peer = ata_dev_pair(adev); 225 struct ata_timing t, p; 226 static int via_clock = 33333; /* Bus clock in kHZ */ 227 unsigned long T = 1000000000 / via_clock; 228 unsigned long UT = T; 229 int ut; 230 int offset = 3 - (2*ap->port_no) - adev->devno; 231 232 switch (udma_type) { 233 case ATA_UDMA4: 234 UT = T / 2; break; 235 case ATA_UDMA5: 236 UT = T / 3; break; 237 case ATA_UDMA6: 238 UT = T / 4; break; 239 } 240 241 /* Calculate the timing values we require */ 242 ata_timing_compute(adev, mode, &t, T, UT); 243 244 /* We share 8bit timing so we must merge the constraints */ 245 if (peer) { 246 if (peer->pio_mode) { 247 ata_timing_compute(peer, peer->pio_mode, &p, T, UT); 248 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); 249 } 250 } 251 252 /* Address setup is programmable but breaks on UDMA133 setups */ 253 if (set_ast) { 254 u8 setup; /* 2 bits per drive */ 255 int shift = 2 * offset; 256 257 pci_read_config_byte(pdev, 0x4C, &setup); 258 setup &= ~(3 << shift); 259 setup |= (clamp_val(t.setup, 1, 4) - 1) << shift; 260 pci_write_config_byte(pdev, 0x4C, setup); 261 } 262 263 /* Load the PIO mode bits */ 264 pci_write_config_byte(pdev, 0x4F - ap->port_no, 265 ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1)); 266 pci_write_config_byte(pdev, 0x48 + offset, 267 ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1)); 268 269 /* Load the UDMA bits according to type */ 270 switch (udma_type) { 271 case ATA_UDMA2: 272 default: 273 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03; 274 break; 275 case ATA_UDMA4: 276 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f; 277 break; 278 case ATA_UDMA5: 279 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; 280 break; 281 case ATA_UDMA6: 282 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; 283 break; 284 } 285 286 /* Set UDMA unless device is not UDMA capable */ 287 if (udma_type) { 288 u8 udma_etc; 289 290 pci_read_config_byte(pdev, 0x50 + offset, &udma_etc); 291 292 /* clear transfer mode bit */ 293 udma_etc &= ~0x20; 294 295 if (t.udma) { 296 /* preserve 80-wire cable detection bit */ 297 udma_etc &= 0x10; 298 udma_etc |= ut; 299 } 300 301 pci_write_config_byte(pdev, 0x50 + offset, udma_etc); 302 } 303} 304 305static void via_set_piomode(struct ata_port *ap, struct ata_device *adev) 306{ 307 const struct via_isa_bridge *config = ap->host->private_data; 308 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 309 310 via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask); 311} 312 313static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) 314{ 315 const struct via_isa_bridge *config = ap->host->private_data; 316 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 317 318 via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask); 319} 320 321/** 322 * via_mode_filter - filter buggy device/mode pairs 323 * @dev: ATA device 324 * @mask: Mode bitmask 325 * 326 * We need to apply some minimal filtering for old controllers and at least 327 * one breed of Transcend SSD. Return the updated mask. 328 */ 329 330static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask) 331{ 332 struct ata_host *host = dev->link->ap->host; 333 const struct via_isa_bridge *config = host->private_data; 334 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 335 336 if (config->id == PCI_DEVICE_ID_VIA_82C586_0) { 337 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 338 if (strcmp(model_num, "TS64GSSD25-M") == 0) { 339 ata_dev_printk(dev, KERN_WARNING, 340 "disabling UDMA mode due to reported lockups with this device.\n"); 341 mask &= ~ ATA_MASK_UDMA; 342 } 343 } 344 return mask; 345} 346 347/** 348 * via_tf_load - send taskfile registers to host controller 349 * @ap: Port to which output is sent 350 * @tf: ATA taskfile register set 351 * 352 * Outputs ATA taskfile to standard ATA host controller. 353 * 354 * Note: This is to fix the internal bug of via chipsets, which 355 * will reset the device register after changing the IEN bit on 356 * ctl register 357 */ 358static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 359{ 360 struct ata_ioports *ioaddr = &ap->ioaddr; 361 struct via_port *vp = ap->private_data; 362 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 363 int newctl = 0; 364 365 if (tf->ctl != ap->last_ctl) { 366 iowrite8(tf->ctl, ioaddr->ctl_addr); 367 ap->last_ctl = tf->ctl; 368 ata_wait_idle(ap); 369 newctl = 1; 370 } 371 372 if (tf->flags & ATA_TFLAG_DEVICE) { 373 iowrite8(tf->device, ioaddr->device_addr); 374 vp->cached_device = tf->device; 375 } else if (newctl) 376 iowrite8(vp->cached_device, ioaddr->device_addr); 377 378 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 379 WARN_ON_ONCE(!ioaddr->ctl_addr); 380 iowrite8(tf->hob_feature, ioaddr->feature_addr); 381 iowrite8(tf->hob_nsect, ioaddr->nsect_addr); 382 iowrite8(tf->hob_lbal, ioaddr->lbal_addr); 383 iowrite8(tf->hob_lbam, ioaddr->lbam_addr); 384 iowrite8(tf->hob_lbah, ioaddr->lbah_addr); 385 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 386 tf->hob_feature, 387 tf->hob_nsect, 388 tf->hob_lbal, 389 tf->hob_lbam, 390 tf->hob_lbah); 391 } 392 393 if (is_addr) { 394 iowrite8(tf->feature, ioaddr->feature_addr); 395 iowrite8(tf->nsect, ioaddr->nsect_addr); 396 iowrite8(tf->lbal, ioaddr->lbal_addr); 397 iowrite8(tf->lbam, ioaddr->lbam_addr); 398 iowrite8(tf->lbah, ioaddr->lbah_addr); 399 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 400 tf->feature, 401 tf->nsect, 402 tf->lbal, 403 tf->lbam, 404 tf->lbah); 405 } 406 407 ata_wait_idle(ap); 408} 409 410static int via_port_start(struct ata_port *ap) 411{ 412 struct via_port *vp; 413 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 414 415 int ret = ata_bmdma_port_start(ap); 416 if (ret < 0) 417 return ret; 418 419 vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL); 420 if (vp == NULL) 421 return -ENOMEM; 422 ap->private_data = vp; 423 return 0; 424} 425 426static struct scsi_host_template via_sht = { 427 ATA_BMDMA_SHT(DRV_NAME), 428}; 429 430static struct ata_port_operations via_port_ops = { 431 .inherits = &ata_bmdma_port_ops, 432 .cable_detect = via_cable_detect, 433 .set_piomode = via_set_piomode, 434 .set_dmamode = via_set_dmamode, 435 .prereset = via_pre_reset, 436 .sff_tf_load = via_tf_load, 437 .port_start = via_port_start, 438 .mode_filter = via_mode_filter, 439}; 440 441static struct ata_port_operations via_port_ops_noirq = { 442 .inherits = &via_port_ops, 443 .sff_data_xfer = ata_sff_data_xfer_noirq, 444}; 445 446/** 447 * via_config_fifo - set up the FIFO 448 * @pdev: PCI device 449 * @flags: configuration flags 450 * 451 * Set the FIFO properties for this device if necessary. Used both on 452 * set up and on and the resume path 453 */ 454 455static void via_config_fifo(struct pci_dev *pdev, unsigned int flags) 456{ 457 u8 enable; 458 459 /* 0x40 low bits indicate enabled channels */ 460 pci_read_config_byte(pdev, 0x40 , &enable); 461 enable &= 3; 462 463 if (flags & VIA_SET_FIFO) { 464 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20}; 465 u8 fifo; 466 467 pci_read_config_byte(pdev, 0x43, &fifo); 468 469 /* Clear PREQ# until DDACK# for errata */ 470 if (flags & VIA_BAD_PREQ) 471 fifo &= 0x7F; 472 else 473 fifo &= 0x9f; 474 /* Turn on FIFO for enabled channels */ 475 fifo |= fifo_setting[enable]; 476 pci_write_config_byte(pdev, 0x43, fifo); 477 } 478} 479 480/** 481 * via_init_one - discovery callback 482 * @pdev: PCI device 483 * @id: PCI table info 484 * 485 * A VIA IDE interface has been discovered. Figure out what revision 486 * and perform configuration work before handing it to the ATA layer 487 */ 488 489static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 490{ 491 /* Early VIA without UDMA support */ 492 static const struct ata_port_info via_mwdma_info = { 493 .flags = ATA_FLAG_SLAVE_POSS, 494 .pio_mask = ATA_PIO4, 495 .mwdma_mask = ATA_MWDMA2, 496 .port_ops = &via_port_ops 497 }; 498 /* Ditto with IRQ masking required */ 499 static const struct ata_port_info via_mwdma_info_borked = { 500 .flags = ATA_FLAG_SLAVE_POSS, 501 .pio_mask = ATA_PIO4, 502 .mwdma_mask = ATA_MWDMA2, 503 .port_ops = &via_port_ops_noirq, 504 }; 505 /* VIA UDMA 33 devices (and borked 66) */ 506 static const struct ata_port_info via_udma33_info = { 507 .flags = ATA_FLAG_SLAVE_POSS, 508 .pio_mask = ATA_PIO4, 509 .mwdma_mask = ATA_MWDMA2, 510 .udma_mask = ATA_UDMA2, 511 .port_ops = &via_port_ops 512 }; 513 /* VIA UDMA 66 devices */ 514 static const struct ata_port_info via_udma66_info = { 515 .flags = ATA_FLAG_SLAVE_POSS, 516 .pio_mask = ATA_PIO4, 517 .mwdma_mask = ATA_MWDMA2, 518 .udma_mask = ATA_UDMA4, 519 .port_ops = &via_port_ops 520 }; 521 /* VIA UDMA 100 devices */ 522 static const struct ata_port_info via_udma100_info = { 523 .flags = ATA_FLAG_SLAVE_POSS, 524 .pio_mask = ATA_PIO4, 525 .mwdma_mask = ATA_MWDMA2, 526 .udma_mask = ATA_UDMA5, 527 .port_ops = &via_port_ops 528 }; 529 /* UDMA133 with bad AST (All current 133) */ 530 static const struct ata_port_info via_udma133_info = { 531 .flags = ATA_FLAG_SLAVE_POSS, 532 .pio_mask = ATA_PIO4, 533 .mwdma_mask = ATA_MWDMA2, 534 .udma_mask = ATA_UDMA6, 535 .port_ops = &via_port_ops 536 }; 537 const struct ata_port_info *ppi[] = { NULL, NULL }; 538 struct pci_dev *isa; 539 const struct via_isa_bridge *config; 540 static int printed_version; 541 u8 enable; 542 u32 timing; 543 unsigned long flags = id->driver_data; 544 int rc; 545 546 if (!printed_version++) 547 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 548 549 rc = pcim_enable_device(pdev); 550 if (rc) 551 return rc; 552 553 if (flags & VIA_IDFLAG_SINGLE) 554 ppi[1] = &ata_dummy_port_info; 555 556 /* To find out how the IDE will behave and what features we 557 actually have to look at the bridge not the IDE controller */ 558 for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON; 559 config++) 560 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + 561 !!(config->flags & VIA_BAD_ID), 562 config->id, NULL))) { 563 u8 rev = isa->revision; 564 pci_dev_put(isa); 565 566 if ((id->device == 0x0415 || id->device == 0x3164) && 567 (config->id != id->device)) 568 continue; 569 570 if (rev >= config->rev_min && rev <= config->rev_max) 571 break; 572 } 573 574 if (!(config->flags & VIA_NO_ENABLES)) { 575 /* 0x40 low bits indicate enabled channels */ 576 pci_read_config_byte(pdev, 0x40 , &enable); 577 enable &= 3; 578 if (enable == 0) 579 return -ENODEV; 580 } 581 582 /* Initialise the FIFO for the enabled channels. */ 583 via_config_fifo(pdev, config->flags); 584 585 /* Clock set up */ 586 switch (config->udma_mask) { 587 case 0x00: 588 if (config->flags & VIA_NO_UNMASK) 589 ppi[0] = &via_mwdma_info_borked; 590 else 591 ppi[0] = &via_mwdma_info; 592 break; 593 case ATA_UDMA2: 594 ppi[0] = &via_udma33_info; 595 break; 596 case ATA_UDMA4: 597 ppi[0] = &via_udma66_info; 598 break; 599 case ATA_UDMA5: 600 ppi[0] = &via_udma100_info; 601 break; 602 case ATA_UDMA6: 603 ppi[0] = &via_udma133_info; 604 break; 605 default: 606 WARN_ON(1); 607 return -ENODEV; 608 } 609 610 if (config->flags & VIA_BAD_CLK66) { 611 /* Disable the 66MHz clock on problem devices */ 612 pci_read_config_dword(pdev, 0x50, &timing); 613 timing &= ~0x80008; 614 pci_write_config_dword(pdev, 0x50, timing); 615 } 616 617 /* We have established the device type, now fire it up */ 618 return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0); 619} 620 621#ifdef CONFIG_PM 622/** 623 * via_reinit_one - reinit after resume 624 * @pdev; PCI device 625 * 626 * Called when the VIA PATA device is resumed. We must then 627 * reconfigure the fifo and other setup we may have altered. In 628 * addition the kernel needs to have the resume methods on PCI 629 * quirk supported. 630 */ 631 632static int via_reinit_one(struct pci_dev *pdev) 633{ 634 u32 timing; 635 struct ata_host *host = dev_get_drvdata(&pdev->dev); 636 const struct via_isa_bridge *config = host->private_data; 637 int rc; 638 639 rc = ata_pci_device_do_resume(pdev); 640 if (rc) 641 return rc; 642 643 via_config_fifo(pdev, config->flags); 644 645 if (config->udma_mask == ATA_UDMA4) { 646 /* The 66 MHz devices require we enable the clock */ 647 pci_read_config_dword(pdev, 0x50, &timing); 648 timing |= 0x80008; 649 pci_write_config_dword(pdev, 0x50, timing); 650 } 651 if (config->flags & VIA_BAD_CLK66) { 652 /* Disable the 66MHz clock on problem devices */ 653 pci_read_config_dword(pdev, 0x50, &timing); 654 timing &= ~0x80008; 655 pci_write_config_dword(pdev, 0x50, timing); 656 } 657 658 ata_host_resume(host); 659 return 0; 660} 661#endif 662 663static const struct pci_device_id via[] = { 664 { PCI_VDEVICE(VIA, 0x0415), }, 665 { PCI_VDEVICE(VIA, 0x0571), }, 666 { PCI_VDEVICE(VIA, 0x0581), }, 667 { PCI_VDEVICE(VIA, 0x1571), }, 668 { PCI_VDEVICE(VIA, 0x3164), }, 669 { PCI_VDEVICE(VIA, 0x5324), }, 670 { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE }, 671 { PCI_VDEVICE(VIA, 0x9001), VIA_IDFLAG_SINGLE }, 672 673 { }, 674}; 675 676static struct pci_driver via_pci_driver = { 677 .name = DRV_NAME, 678 .id_table = via, 679 .probe = via_init_one, 680 .remove = ata_pci_remove_one, 681#ifdef CONFIG_PM 682 .suspend = ata_pci_device_suspend, 683 .resume = via_reinit_one, 684#endif 685}; 686 687static int __init via_init(void) 688{ 689 return pci_register_driver(&via_pci_driver); 690} 691 692static void __exit via_exit(void) 693{ 694 pci_unregister_driver(&via_pci_driver); 695} 696 697MODULE_AUTHOR("Alan Cox"); 698MODULE_DESCRIPTION("low-level driver for VIA PATA"); 699MODULE_LICENSE("GPL"); 700MODULE_DEVICE_TABLE(pci, via); 701MODULE_VERSION(DRV_VERSION); 702 703module_init(via_init); 704module_exit(via_exit); 705