1/* 2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * Ported to libata by: 10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation 11 * 12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> 13 * Portions Copyright (C) 1999 Promise Technology, Inc. 14 * 15 * Author: Frank Tiernan (frankt@promise.com) 16 * Released under terms of General Public License 17 * 18 * 19 * libata documentation is available via 'make {ps|pdf}docs', 20 * as Documentation/DocBook/libata.* 21 * 22 * Hardware information only available under NDA. 23 * 24 */ 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/init.h> 29#include <linux/blkdev.h> 30#include <linux/delay.h> 31#include <linux/device.h> 32#include <scsi/scsi.h> 33#include <scsi/scsi_host.h> 34#include <scsi/scsi_cmnd.h> 35#include <linux/libata.h> 36 37#define DRV_NAME "pata_pdc2027x" 38#define DRV_VERSION "1.0" 39#undef PDC_DEBUG 40 41#ifdef PDC_DEBUG 42#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 43#else 44#define PDPRINTK(fmt, args...) 45#endif 46 47enum { 48 PDC_MMIO_BAR = 5, 49 50 PDC_UDMA_100 = 0, 51 PDC_UDMA_133 = 1, 52 53 PDC_100_MHZ = 100000000, 54 PDC_133_MHZ = 133333333, 55 56 PDC_SYS_CTL = 0x1100, 57 PDC_ATA_CTL = 0x1104, 58 PDC_GLOBAL_CTL = 0x1108, 59 PDC_CTCR0 = 0x110C, 60 PDC_CTCR1 = 0x1110, 61 PDC_BYTE_COUNT = 0x1120, 62 PDC_PLL_CTL = 0x1202, 63}; 64 65static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 66static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline); 67static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev); 68static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev); 69static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc); 70static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask); 71static int pdc2027x_cable_detect(struct ata_port *ap); 72static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed); 73 74/* 75 * ATA Timing Tables based on 133MHz controller clock. 76 * These tables are only used when the controller is in 133MHz clock. 77 * If the controller is in 100MHz clock, the ASIC hardware will 78 * set the timing registers automatically when "set feature" command 79 * is issued to the device. However, if the controller clock is 133MHz, 80 * the following tables must be used. 81 */ 82static struct pdc2027x_pio_timing { 83 u8 value0, value1, value2; 84} pdc2027x_pio_timing_tbl [] = { 85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ 86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */ 87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */ 88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ 89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ 90}; 91 92static struct pdc2027x_mdma_timing { 93 u8 value0, value1; 94} pdc2027x_mdma_timing_tbl [] = { 95 { 0xdf, 0x5f }, /* MDMA mode 0 */ 96 { 0x6b, 0x27 }, /* MDMA mode 1 */ 97 { 0x69, 0x25 }, /* MDMA mode 2 */ 98}; 99 100static struct pdc2027x_udma_timing { 101 u8 value0, value1, value2; 102} pdc2027x_udma_timing_tbl [] = { 103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ 104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ 105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ 106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ 107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ 108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ 109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ 110}; 111 112static const struct pci_device_id pdc2027x_pci_tbl[] = { 113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 }, 114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 }, 115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 }, 116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 }, 117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 }, 118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 }, 119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 }, 120 121 { } /* terminate list */ 122}; 123 124static struct pci_driver pdc2027x_pci_driver = { 125 .name = DRV_NAME, 126 .id_table = pdc2027x_pci_tbl, 127 .probe = pdc2027x_init_one, 128 .remove = ata_pci_remove_one, 129}; 130 131static struct scsi_host_template pdc2027x_sht = { 132 ATA_BMDMA_SHT(DRV_NAME), 133}; 134 135static struct ata_port_operations pdc2027x_pata100_ops = { 136 .inherits = &ata_bmdma_port_ops, 137 .check_atapi_dma = pdc2027x_check_atapi_dma, 138 .cable_detect = pdc2027x_cable_detect, 139 .prereset = pdc2027x_prereset, 140}; 141 142static struct ata_port_operations pdc2027x_pata133_ops = { 143 .inherits = &pdc2027x_pata100_ops, 144 .mode_filter = pdc2027x_mode_filter, 145 .set_piomode = pdc2027x_set_piomode, 146 .set_dmamode = pdc2027x_set_dmamode, 147 .set_mode = pdc2027x_set_mode, 148}; 149 150static struct ata_port_info pdc2027x_port_info[] = { 151 /* PDC_UDMA_100 */ 152 { 153 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS | 154 ATA_FLAG_MMIO, 155 .pio_mask = ATA_PIO4, 156 .mwdma_mask = ATA_MWDMA2, 157 .udma_mask = ATA_UDMA5, 158 .port_ops = &pdc2027x_pata100_ops, 159 }, 160 /* PDC_UDMA_133 */ 161 { 162 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS | 163 ATA_FLAG_MMIO, 164 .pio_mask = ATA_PIO4, 165 .mwdma_mask = ATA_MWDMA2, 166 .udma_mask = ATA_UDMA6, 167 .port_ops = &pdc2027x_pata133_ops, 168 }, 169}; 170 171MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee"); 172MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277"); 173MODULE_LICENSE("GPL"); 174MODULE_VERSION(DRV_VERSION); 175MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); 176 177/** 178 * port_mmio - Get the MMIO address of PDC2027x extended registers 179 * @ap: Port 180 * @offset: offset from mmio base 181 */ 182static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) 183{ 184 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset; 185} 186 187/** 188 * dev_mmio - Get the MMIO address of PDC2027x extended registers 189 * @ap: Port 190 * @adev: device 191 * @offset: offset from mmio base 192 */ 193static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset) 194{ 195 u8 adj = (adev->devno) ? 0x08 : 0x00; 196 return port_mmio(ap, offset) + adj; 197} 198 199/** 200 * pdc2027x_pata_cable_detect - Probe host controller cable detect info 201 * @ap: Port for which cable detect info is desired 202 * 203 * Read 80c cable indicator from Promise extended register. 204 * This register is latched when the system is reset. 205 * 206 * LOCKING: 207 * None (inherited from caller). 208 */ 209static int pdc2027x_cable_detect(struct ata_port *ap) 210{ 211 u32 cgcr; 212 213 /* check cable detect results */ 214 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL)); 215 if (cgcr & (1 << 26)) 216 goto cbl40; 217 218 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no); 219 220 return ATA_CBL_PATA80; 221cbl40: 222 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no); 223 return ATA_CBL_PATA40; 224} 225 226/** 227 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled. 228 * @ap: Port to check 229 */ 230static inline int pdc2027x_port_enabled(struct ata_port *ap) 231{ 232 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02; 233} 234 235/** 236 * pdc2027x_prereset - prereset for PATA host controller 237 * @link: Target link 238 * @deadline: deadline jiffies for the operation 239 * 240 * Probeinit including cable detection. 241 * 242 * LOCKING: 243 * None (inherited from caller). 244 */ 245 246static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline) 247{ 248 /* Check whether port enabled */ 249 if (!pdc2027x_port_enabled(link->ap)) 250 return -ENOENT; 251 return ata_sff_prereset(link, deadline); 252} 253 254/** 255 * pdc2720x_mode_filter - mode selection filter 256 * @adev: ATA device 257 * @mask: list of modes proposed 258 * 259 * Block UDMA on devices that cause trouble with this controller. 260 */ 261 262static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask) 263{ 264 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 265 struct ata_device *pair = ata_dev_pair(adev); 266 267 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL) 268 return mask; 269 270 /* Check for slave of a Maxtor at UDMA6 */ 271 ata_id_c_string(pair->id, model_num, ATA_ID_PROD, 272 ATA_ID_PROD_LEN + 1); 273 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */ 274 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6) 275 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA)); 276 277 return mask; 278} 279 280/** 281 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings 282 * @ap: Port to configure 283 * @adev: um 284 * 285 * Set PIO mode for device. 286 * 287 * LOCKING: 288 * None (inherited from caller). 289 */ 290 291static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev) 292{ 293 unsigned int pio = adev->pio_mode - XFER_PIO_0; 294 u32 ctcr0, ctcr1; 295 296 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode); 297 298 /* Sanity check */ 299 if (pio > 4) { 300 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio); 301 return; 302 303 } 304 305 /* Set the PIO timing registers using value table for 133MHz */ 306 PDPRINTK("Set pio regs... \n"); 307 308 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); 309 ctcr0 &= 0xffff0000; 310 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | 311 (pdc2027x_pio_timing_tbl[pio].value1 << 8); 312 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); 313 314 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 315 ctcr1 &= 0x00ffffff; 316 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); 317 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); 318 319 PDPRINTK("Set pio regs done\n"); 320 321 PDPRINTK("Set to pio mode[%u] \n", pio); 322} 323 324/** 325 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings 326 * @ap: Port to configure 327 * @adev: um 328 * 329 * Set UDMA mode for device. 330 * 331 * LOCKING: 332 * None (inherited from caller). 333 */ 334static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 335{ 336 unsigned int dma_mode = adev->dma_mode; 337 u32 ctcr0, ctcr1; 338 339 if ((dma_mode >= XFER_UDMA_0) && 340 (dma_mode <= XFER_UDMA_6)) { 341 /* Set the UDMA timing registers with value table for 133MHz */ 342 unsigned int udma_mode = dma_mode & 0x07; 343 344 if (dma_mode == XFER_UDMA_2) { 345 /* 346 * Turn off tHOLD. 347 * If tHOLD is '1', the hardware will add half clock for data hold time. 348 * This code segment seems to be no effect. tHOLD will be overwritten below. 349 */ 350 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 351 iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1)); 352 } 353 354 PDPRINTK("Set udma regs... \n"); 355 356 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 357 ctcr1 &= 0xff000000; 358 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 | 359 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) | 360 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16); 361 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); 362 363 PDPRINTK("Set udma regs done\n"); 364 365 PDPRINTK("Set to udma mode[%u] \n", udma_mode); 366 367 } else if ((dma_mode >= XFER_MW_DMA_0) && 368 (dma_mode <= XFER_MW_DMA_2)) { 369 /* Set the MDMA timing registers with value table for 133MHz */ 370 unsigned int mdma_mode = dma_mode & 0x07; 371 372 PDPRINTK("Set mdma regs... \n"); 373 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); 374 375 ctcr0 &= 0x0000ffff; 376 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) | 377 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24); 378 379 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); 380 PDPRINTK("Set mdma regs done\n"); 381 382 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode); 383 } else { 384 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode); 385 } 386} 387 388/** 389 * pdc2027x_set_mode - Set the timing registers back to correct values. 390 * @link: link to configure 391 * @r_failed: Returned device for failure 392 * 393 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers 394 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL. 395 * This function overwrites the possibly incorrect values set by the hardware to be correct. 396 */ 397static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed) 398{ 399 struct ata_port *ap = link->ap; 400 struct ata_device *dev; 401 int rc; 402 403 rc = ata_do_set_mode(link, r_failed); 404 if (rc < 0) 405 return rc; 406 407 ata_for_each_dev(dev, link, ENABLED) { 408 pdc2027x_set_piomode(ap, dev); 409 410 /* 411 * Enable prefetch if the device support PIO only. 412 */ 413 if (dev->xfer_shift == ATA_SHIFT_PIO) { 414 u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1)); 415 ctcr1 |= (1 << 25); 416 iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1)); 417 418 PDPRINTK("Turn on prefetch\n"); 419 } else { 420 pdc2027x_set_dmamode(ap, dev); 421 } 422 } 423 return 0; 424} 425 426/** 427 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command 428 * @qc: Metadata associated with taskfile to check 429 * 430 * LOCKING: 431 * None (inherited from caller). 432 * 433 * RETURNS: 0 when ATAPI DMA can be used 434 * 1 otherwise 435 */ 436static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc) 437{ 438 struct scsi_cmnd *cmd = qc->scsicmd; 439 u8 *scsicmd = cmd->cmnd; 440 int rc = 1; /* atapi dma off by default */ 441 442 switch (scsicmd[0]) { 443 case READ_10: 444 case WRITE_10: 445 case READ_12: 446 case WRITE_12: 447 case READ_6: 448 case WRITE_6: 449 case 0xad: /* READ_DVD_STRUCTURE */ 450 case 0xbe: /* READ_CD */ 451 /* ATAPI DMA is ok */ 452 rc = 0; 453 break; 454 default: 455 ; 456 } 457 458 return rc; 459} 460 461/** 462 * pdc_read_counter - Read the ctr counter 463 * @host: target ATA host 464 */ 465 466static long pdc_read_counter(struct ata_host *host) 467{ 468 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 469 long counter; 470 int retry = 1; 471 u32 bccrl, bccrh, bccrlv, bccrhv; 472 473retry: 474 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 475 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 476 477 /* Read the counter values again for verification */ 478 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 479 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 480 481 counter = (bccrh << 15) | bccrl; 482 483 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl); 484 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv); 485 486 /* 487 * The 30-bit decreasing counter are read by 2 pieces. 488 * Incorrect value may be read when both bccrh and bccrl are changing. 489 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read. 490 */ 491 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) { 492 retry--; 493 PDPRINTK("rereading counter\n"); 494 goto retry; 495 } 496 497 return counter; 498} 499 500/** 501 * adjust_pll - Adjust the PLL input clock in Hz. 502 * 503 * @pdc_controller: controller specific information 504 * @host: target ATA host 505 * @pll_clock: The input of PLL in HZ 506 */ 507static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx) 508{ 509 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 510 u16 pll_ctl; 511 long pll_clock_khz = pll_clock / 1000; 512 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; 513 long ratio = pout_required / pll_clock_khz; 514 int F, R; 515 516 /* Sanity check */ 517 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) { 518 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz); 519 return; 520 } 521 522#ifdef PDC_DEBUG 523 PDPRINTK("pout_required is %ld\n", pout_required); 524 525 /* Show the current clock value of PLL control register 526 * (maybe already configured by the firmware) 527 */ 528 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); 529 530 PDPRINTK("pll_ctl[%X]\n", pll_ctl); 531#endif 532 533 /* 534 * Calculate the ratio of F, R and OD 535 * POUT = (F + 2) / (( R + 2) * NO) 536 */ 537 if (ratio < 8600L) { /* 8.6x */ 538 /* Using NO = 0x01, R = 0x0D */ 539 R = 0x0d; 540 } else if (ratio < 12900L) { /* 12.9x */ 541 /* Using NO = 0x01, R = 0x08 */ 542 R = 0x08; 543 } else if (ratio < 16100L) { /* 16.1x */ 544 /* Using NO = 0x01, R = 0x06 */ 545 R = 0x06; 546 } else if (ratio < 64000L) { /* 64x */ 547 R = 0x00; 548 } else { 549 /* Invalid ratio */ 550 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio); 551 return; 552 } 553 554 F = (ratio * (R+2)) / 1000 - 2; 555 556 if (unlikely(F < 0 || F > 127)) { 557 /* Invalid F */ 558 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F); 559 return; 560 } 561 562 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); 563 564 pll_ctl = (R << 8) | F; 565 566 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl); 567 568 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); 569 ioread16(mmio_base + PDC_PLL_CTL); /* flush */ 570 571 /* Wait the PLL circuit to be stable */ 572 mdelay(30); 573 574#ifdef PDC_DEBUG 575 /* 576 * Show the current clock value of PLL control register 577 * (maybe configured by the firmware) 578 */ 579 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); 580 581 PDPRINTK("pll_ctl[%X]\n", pll_ctl); 582#endif 583 584 return; 585} 586 587/** 588 * detect_pll_input_clock - Detect the PLL input clock in Hz. 589 * @host: target ATA host 590 * Ex. 16949000 on 33MHz PCI bus for pdc20275. 591 * Half of the PCI clock. 592 */ 593static long pdc_detect_pll_input_clock(struct ata_host *host) 594{ 595 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 596 u32 scr; 597 long start_count, end_count; 598 struct timeval start_time, end_time; 599 long pll_clock, usec_elapsed; 600 601 /* Start the test mode */ 602 scr = ioread32(mmio_base + PDC_SYS_CTL); 603 PDPRINTK("scr[%X]\n", scr); 604 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL); 605 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ 606 607 /* Read current counter value */ 608 start_count = pdc_read_counter(host); 609 do_gettimeofday(&start_time); 610 611 /* Let the counter run for 100 ms. */ 612 mdelay(100); 613 614 /* Read the counter values again */ 615 end_count = pdc_read_counter(host); 616 do_gettimeofday(&end_time); 617 618 /* Stop the test mode */ 619 scr = ioread32(mmio_base + PDC_SYS_CTL); 620 PDPRINTK("scr[%X]\n", scr); 621 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL); 622 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ 623 624 /* calculate the input clock in Hz */ 625 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 + 626 (end_time.tv_usec - start_time.tv_usec); 627 628 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 * 629 (100000000 / usec_elapsed); 630 631 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count); 632 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock); 633 634 return pll_clock; 635} 636 637/** 638 * pdc_hardware_init - Initialize the hardware. 639 * @host: target ATA host 640 * @board_idx: board identifier 641 */ 642static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx) 643{ 644 long pll_clock; 645 646 /* 647 * Detect PLL input clock rate. 648 * On some system, where PCI bus is running at non-standard clock rate. 649 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time. 650 * The pdc20275 controller employs PLL circuit to help correct timing registers setting. 651 */ 652 pll_clock = pdc_detect_pll_input_clock(host); 653 654 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000); 655 656 /* Adjust PLL control register */ 657 pdc_adjust_pll(host, pll_clock, board_idx); 658 659 return 0; 660} 661 662/** 663 * pdc_ata_setup_port - setup the mmio address 664 * @port: ata ioports to setup 665 * @base: base address 666 */ 667static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) 668{ 669 port->cmd_addr = 670 port->data_addr = base; 671 port->feature_addr = 672 port->error_addr = base + 0x05; 673 port->nsect_addr = base + 0x0a; 674 port->lbal_addr = base + 0x0f; 675 port->lbam_addr = base + 0x10; 676 port->lbah_addr = base + 0x15; 677 port->device_addr = base + 0x1a; 678 port->command_addr = 679 port->status_addr = base + 0x1f; 680 port->altstatus_addr = 681 port->ctl_addr = base + 0x81a; 682} 683 684/** 685 * pdc2027x_init_one - PCI probe function 686 * Called when an instance of PCI adapter is inserted. 687 * This function checks whether the hardware is supported, 688 * initialize hardware and register an instance of ata_host to 689 * libata. (implements struct pci_driver.probe() ) 690 * 691 * @pdev: instance of pci_dev found 692 * @ent: matching entry in the id_tbl[] 693 */ 694static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 695{ 696 static int printed_version; 697 static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 }; 698 static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 }; 699 unsigned int board_idx = (unsigned int) ent->driver_data; 700 const struct ata_port_info *ppi[] = 701 { &pdc2027x_port_info[board_idx], NULL }; 702 struct ata_host *host; 703 void __iomem *mmio_base; 704 int i, rc; 705 706 if (!printed_version++) 707 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 708 709 /* alloc host */ 710 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 711 if (!host) 712 return -ENOMEM; 713 714 /* acquire resources and fill host */ 715 rc = pcim_enable_device(pdev); 716 if (rc) 717 return rc; 718 719 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 720 if (rc) 721 return rc; 722 host->iomap = pcim_iomap_table(pdev); 723 724 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 725 if (rc) 726 return rc; 727 728 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 729 if (rc) 730 return rc; 731 732 mmio_base = host->iomap[PDC_MMIO_BAR]; 733 734 for (i = 0; i < 2; i++) { 735 struct ata_port *ap = host->ports[i]; 736 737 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]); 738 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i]; 739 740 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 741 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd"); 742 } 743 744 //pci_enable_intx(pdev); 745 746 /* initialize adapter */ 747 if (pdc_hardware_init(host, board_idx) != 0) 748 return -EIO; 749 750 pci_set_master(pdev); 751 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 752 IRQF_SHARED, &pdc2027x_sht); 753} 754 755/** 756 * pdc2027x_init - Called after this module is loaded into the kernel. 757 */ 758static int __init pdc2027x_init(void) 759{ 760 return pci_register_driver(&pdc2027x_pci_driver); 761} 762 763/** 764 * pdc2027x_exit - Called before this module unloaded from the kernel 765 */ 766static void __exit pdc2027x_exit(void) 767{ 768 pci_unregister_driver(&pdc2027x_pci_driver); 769} 770 771module_init(pdc2027x_init); 772module_exit(pdc2027x_exit); 773