1/* 2 * pata_it821x.c - IT821x PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@lxorguk.ukuu.org.uk> 5 * (C) 2007 Bartlomiej Zolnierkiewicz 6 * 7 * based upon 8 * 9 * it821x.c 10 * 11 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004 12 * 13 * Copyright (C) 2004 Red Hat 14 * 15 * May be copied or modified under the terms of the GNU General Public License 16 * Based in part on the ITE vendor provided SCSI driver. 17 * 18 * Documentation available from 19 * http://www.ite.com.tw/pc/IT8212F_V04.pdf 20 * Some other documents are NDA. 21 * 22 * The ITE8212 isn't exactly a standard IDE controller. It has two 23 * modes. In pass through mode then it is an IDE controller. In its smart 24 * mode its actually quite a capable hardware raid controller disguised 25 * as an IDE controller. Smart mode only understands DMA read/write and 26 * identify, none of the fancier commands apply. The IT8211 is identical 27 * in other respects but lacks the raid mode. 28 * 29 * Errata: 30 * o Rev 0x10 also requires master/slave hold the same DMA timings and 31 * cannot do ATAPI MWDMA. 32 * o The identify data for raid volumes lacks CHS info (technically ok) 33 * but also fails to set the LBA28 and other bits. We fix these in 34 * the IDE probe quirk code. 35 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode 36 * raid then the controller firmware dies 37 * o Smart mode without RAID doesn't clear all the necessary identify 38 * bits to reduce the command set to the one used 39 * 40 * This has a few impacts on the driver 41 * - In pass through mode we do all the work you would expect 42 * - In smart mode the clocking set up is done by the controller generally 43 * but we must watch the other limits and filter. 44 * - There are a few extra vendor commands that actually talk to the 45 * controller but only work PIO with no IRQ. 46 * 47 * Vendor areas of the identify block in smart mode are used for the 48 * timing and policy set up. Each HDD in raid mode also has a serial 49 * block on the disk. The hardware extra commands are get/set chip status, 50 * rebuild, get rebuild status. 51 * 52 * In Linux the driver supports pass through mode as if the device was 53 * just another IDE controller. If the smart mode is running then 54 * volumes are managed by the controller firmware and each IDE "disk" 55 * is a raid volume. Even more cute - the controller can do automated 56 * hotplug and rebuild. 57 * 58 * The pass through controller itself is a little demented. It has a 59 * flaw that it has a single set of PIO/MWDMA timings per channel so 60 * non UDMA devices restrict each others performance. It also has a 61 * single clock source per channel so mixed UDMA100/133 performance 62 * isn't perfect and we have to pick a clock. Thankfully none of this 63 * matters in smart mode. ATAPI DMA is not currently supported. 64 * 65 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. 66 * 67 * TODO 68 * - ATAPI and other speed filtering 69 * - RAID configuration ioctls 70 */ 71 72#include <linux/kernel.h> 73#include <linux/module.h> 74#include <linux/pci.h> 75#include <linux/init.h> 76#include <linux/blkdev.h> 77#include <linux/delay.h> 78#include <linux/slab.h> 79#include <scsi/scsi_host.h> 80#include <linux/libata.h> 81 82 83#define DRV_NAME "pata_it821x" 84#define DRV_VERSION "0.4.2" 85 86struct it821x_dev 87{ 88 unsigned int smart:1, /* Are we in smart raid mode */ 89 timing10:1; /* Rev 0x10 */ 90 u8 clock_mode; /* 0, ATA_50 or ATA_66 */ 91 u8 want[2][2]; /* Mode/Pri log for master slave */ 92 /* We need these for switching the clock when DMA goes on/off 93 The high byte is the 66Mhz timing */ 94 u16 pio[2]; /* Cached PIO values */ 95 u16 mwdma[2]; /* Cached MWDMA values */ 96 u16 udma[2]; /* Cached UDMA values (per drive) */ 97 u16 last_device; /* Master or slave loaded ? */ 98}; 99 100#define ATA_66 0 101#define ATA_50 1 102#define ATA_ANY 2 103 104#define UDMA_OFF 0 105#define MWDMA_OFF 0 106 107/* 108 * We allow users to force the card into non raid mode without 109 * flashing the alternative BIOS. This is also necessary right now 110 * for embedded platforms that cannot run a PC BIOS but are using this 111 * device. 112 */ 113 114static int it8212_noraid; 115 116/** 117 * it821x_program - program the PIO/MWDMA registers 118 * @ap: ATA port 119 * @adev: Device to program 120 * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8) 121 * 122 * Program the PIO/MWDMA timing for this channel according to the 123 * current clock. These share the same register so are managed by 124 * the DMA start/stop sequence as with the old driver. 125 */ 126 127static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing) 128{ 129 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 130 struct it821x_dev *itdev = ap->private_data; 131 int channel = ap->port_no; 132 u8 conf; 133 134 /* Program PIO/MWDMA timing bits */ 135 if (itdev->clock_mode == ATA_66) 136 conf = timing >> 8; 137 else 138 conf = timing & 0xFF; 139 pci_write_config_byte(pdev, 0x54 + 4 * channel, conf); 140} 141 142 143/** 144 * it821x_program_udma - program the UDMA registers 145 * @ap: ATA port 146 * @adev: ATA device to update 147 * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz 148 * 149 * Program the UDMA timing for this drive according to the 150 * current clock. Handles the dual clocks and also knows about 151 * the errata on the 0x10 revision. The UDMA errata is partly handled 152 * here and partly in start_dma. 153 */ 154 155static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing) 156{ 157 struct it821x_dev *itdev = ap->private_data; 158 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 159 int channel = ap->port_no; 160 int unit = adev->devno; 161 u8 conf; 162 163 /* Program UDMA timing bits */ 164 if (itdev->clock_mode == ATA_66) 165 conf = timing >> 8; 166 else 167 conf = timing & 0xFF; 168 if (itdev->timing10 == 0) 169 pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf); 170 else { 171 /* Early revision must be programmed for both together */ 172 pci_write_config_byte(pdev, 0x56 + 4 * channel, conf); 173 pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf); 174 } 175} 176 177/** 178 * it821x_clock_strategy 179 * @ap: ATA interface 180 * @adev: ATA device being updated 181 * 182 * Select between the 50 and 66Mhz base clocks to get the best 183 * results for this interface. 184 */ 185 186static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev) 187{ 188 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 189 struct it821x_dev *itdev = ap->private_data; 190 u8 unit = adev->devno; 191 struct ata_device *pair = ata_dev_pair(adev); 192 193 int clock, altclock; 194 u8 v; 195 int sel = 0; 196 197 /* Look for the most wanted clocking */ 198 if (itdev->want[0][0] > itdev->want[1][0]) { 199 clock = itdev->want[0][1]; 200 altclock = itdev->want[1][1]; 201 } else { 202 clock = itdev->want[1][1]; 203 altclock = itdev->want[0][1]; 204 } 205 206 /* Master doesn't care does the slave ? */ 207 if (clock == ATA_ANY) 208 clock = altclock; 209 210 /* Nobody cares - keep the same clock */ 211 if (clock == ATA_ANY) 212 return; 213 /* No change */ 214 if (clock == itdev->clock_mode) 215 return; 216 217 /* Load this into the controller */ 218 if (clock == ATA_66) 219 itdev->clock_mode = ATA_66; 220 else { 221 itdev->clock_mode = ATA_50; 222 sel = 1; 223 } 224 pci_read_config_byte(pdev, 0x50, &v); 225 v &= ~(1 << (1 + ap->port_no)); 226 v |= sel << (1 + ap->port_no); 227 pci_write_config_byte(pdev, 0x50, v); 228 229 /* 230 * Reprogram the UDMA/PIO of the pair drive for the switch 231 * MWDMA will be dealt with by the dma switcher 232 */ 233 if (pair && itdev->udma[1-unit] != UDMA_OFF) { 234 it821x_program_udma(ap, pair, itdev->udma[1-unit]); 235 it821x_program(ap, pair, itdev->pio[1-unit]); 236 } 237 /* 238 * Reprogram the UDMA/PIO of our drive for the switch. 239 * MWDMA will be dealt with by the dma switcher 240 */ 241 if (itdev->udma[unit] != UDMA_OFF) { 242 it821x_program_udma(ap, adev, itdev->udma[unit]); 243 it821x_program(ap, adev, itdev->pio[unit]); 244 } 245} 246 247/** 248 * it821x_passthru_set_piomode - set PIO mode data 249 * @ap: ATA interface 250 * @adev: ATA device 251 * 252 * Configure for PIO mode. This is complicated as the register is 253 * shared by PIO and MWDMA and for both channels. 254 */ 255 256static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev) 257{ 258 /* Spec says 89 ref driver uses 88 */ 259 static const u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; 260 static const u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; 261 262 struct it821x_dev *itdev = ap->private_data; 263 int unit = adev->devno; 264 int mode_wanted = adev->pio_mode - XFER_PIO_0; 265 266 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ 267 itdev->want[unit][1] = pio_want[mode_wanted]; 268 itdev->want[unit][0] = 1; /* PIO is lowest priority */ 269 itdev->pio[unit] = pio[mode_wanted]; 270 it821x_clock_strategy(ap, adev); 271 it821x_program(ap, adev, itdev->pio[unit]); 272} 273 274/** 275 * it821x_passthru_set_dmamode - set initial DMA mode data 276 * @ap: ATA interface 277 * @adev: ATA device 278 * 279 * Set up the DMA modes. The actions taken depend heavily on the mode 280 * to use. If UDMA is used as is hopefully the usual case then the 281 * timing register is private and we need only consider the clock. If 282 * we are using MWDMA then we have to manage the setting ourself as 283 * we switch devices and mode. 284 */ 285 286static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev) 287{ 288 static const u16 dma[] = { 0x8866, 0x3222, 0x3121 }; 289 static const u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; 290 static const u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; 291 static const u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; 292 293 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 294 struct it821x_dev *itdev = ap->private_data; 295 int channel = ap->port_no; 296 int unit = adev->devno; 297 u8 conf; 298 299 if (adev->dma_mode >= XFER_UDMA_0) { 300 int mode_wanted = adev->dma_mode - XFER_UDMA_0; 301 302 itdev->want[unit][1] = udma_want[mode_wanted]; 303 itdev->want[unit][0] = 3; /* UDMA is high priority */ 304 itdev->mwdma[unit] = MWDMA_OFF; 305 itdev->udma[unit] = udma[mode_wanted]; 306 if (mode_wanted >= 5) 307 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ 308 309 /* UDMA on. Again revision 0x10 must do the pair */ 310 pci_read_config_byte(pdev, 0x50, &conf); 311 if (itdev->timing10) 312 conf &= channel ? 0x9F: 0xE7; 313 else 314 conf &= ~ (1 << (3 + 2 * channel + unit)); 315 pci_write_config_byte(pdev, 0x50, conf); 316 it821x_clock_strategy(ap, adev); 317 it821x_program_udma(ap, adev, itdev->udma[unit]); 318 } else { 319 int mode_wanted = adev->dma_mode - XFER_MW_DMA_0; 320 321 itdev->want[unit][1] = mwdma_want[mode_wanted]; 322 itdev->want[unit][0] = 2; /* MWDMA is low priority */ 323 itdev->mwdma[unit] = dma[mode_wanted]; 324 itdev->udma[unit] = UDMA_OFF; 325 326 /* UDMA bits off - Revision 0x10 do them in pairs */ 327 pci_read_config_byte(pdev, 0x50, &conf); 328 if (itdev->timing10) 329 conf |= channel ? 0x60: 0x18; 330 else 331 conf |= 1 << (3 + 2 * channel + unit); 332 pci_write_config_byte(pdev, 0x50, conf); 333 it821x_clock_strategy(ap, adev); 334 } 335} 336 337/** 338 * it821x_passthru_dma_start - DMA start callback 339 * @qc: Command in progress 340 * 341 * Usually drivers set the DMA timing at the point the set_dmamode call 342 * is made. IT821x however requires we load new timings on the 343 * transitions in some cases. 344 */ 345 346static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc) 347{ 348 struct ata_port *ap = qc->ap; 349 struct ata_device *adev = qc->dev; 350 struct it821x_dev *itdev = ap->private_data; 351 int unit = adev->devno; 352 353 if (itdev->mwdma[unit] != MWDMA_OFF) 354 it821x_program(ap, adev, itdev->mwdma[unit]); 355 else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10) 356 it821x_program_udma(ap, adev, itdev->udma[unit]); 357 ata_bmdma_start(qc); 358} 359 360/** 361 * it821x_passthru_dma_stop - DMA stop callback 362 * @qc: ATA command 363 * 364 * We loaded new timings in dma_start, as a result we need to restore 365 * the PIO timings in dma_stop so that the next command issue gets the 366 * right clock values. 367 */ 368 369static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc) 370{ 371 struct ata_port *ap = qc->ap; 372 struct ata_device *adev = qc->dev; 373 struct it821x_dev *itdev = ap->private_data; 374 int unit = adev->devno; 375 376 ata_bmdma_stop(qc); 377 if (itdev->mwdma[unit] != MWDMA_OFF) 378 it821x_program(ap, adev, itdev->pio[unit]); 379} 380 381 382/** 383 * it821x_passthru_dev_select - Select master/slave 384 * @ap: ATA port 385 * @device: Device number (not pointer) 386 * 387 * Device selection hook. If necessary perform clock switching 388 */ 389 390static void it821x_passthru_dev_select(struct ata_port *ap, 391 unsigned int device) 392{ 393 struct it821x_dev *itdev = ap->private_data; 394 if (itdev && device != itdev->last_device) { 395 struct ata_device *adev = &ap->link.device[device]; 396 it821x_program(ap, adev, itdev->pio[adev->devno]); 397 itdev->last_device = device; 398 } 399 ata_sff_dev_select(ap, device); 400} 401 402/** 403 * it821x_smart_qc_issue - wrap qc issue prot 404 * @qc: command 405 * 406 * Wrap the command issue sequence for the IT821x. We need to 407 * perform out own device selection timing loads before the 408 * usual happenings kick off 409 */ 410 411static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc) 412{ 413 switch(qc->tf.command) 414 { 415 /* Commands the firmware supports */ 416 case ATA_CMD_READ: 417 case ATA_CMD_READ_EXT: 418 case ATA_CMD_WRITE: 419 case ATA_CMD_WRITE_EXT: 420 case ATA_CMD_PIO_READ: 421 case ATA_CMD_PIO_READ_EXT: 422 case ATA_CMD_PIO_WRITE: 423 case ATA_CMD_PIO_WRITE_EXT: 424 case ATA_CMD_READ_MULTI: 425 case ATA_CMD_READ_MULTI_EXT: 426 case ATA_CMD_WRITE_MULTI: 427 case ATA_CMD_WRITE_MULTI_EXT: 428 case ATA_CMD_ID_ATA: 429 case ATA_CMD_INIT_DEV_PARAMS: 430 case 0xFC: /* Internal 'report rebuild state' */ 431 /* Arguably should just no-op this one */ 432 case ATA_CMD_SET_FEATURES: 433 return ata_bmdma_qc_issue(qc); 434 } 435 printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command); 436 return AC_ERR_DEV; 437} 438 439/** 440 * it821x_passthru_qc_issue - wrap qc issue prot 441 * @qc: command 442 * 443 * Wrap the command issue sequence for the IT821x. We need to 444 * perform out own device selection timing loads before the 445 * usual happenings kick off 446 */ 447 448static unsigned int it821x_passthru_qc_issue(struct ata_queued_cmd *qc) 449{ 450 it821x_passthru_dev_select(qc->ap, qc->dev->devno); 451 return ata_bmdma_qc_issue(qc); 452} 453 454/** 455 * it821x_smart_set_mode - mode setting 456 * @link: interface to set up 457 * @unused: device that failed (error only) 458 * 459 * Use a non standard set_mode function. We don't want to be tuned. 460 * The BIOS configured everything. Our job is not to fiddle. We 461 * read the dma enabled bits from the PCI configuration of the device 462 * and respect them. 463 */ 464 465static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unused) 466{ 467 struct ata_device *dev; 468 469 ata_for_each_dev(dev, link, ENABLED) { 470 /* We don't really care */ 471 dev->pio_mode = XFER_PIO_0; 472 dev->dma_mode = XFER_MW_DMA_0; 473 /* We do need the right mode information for DMA or PIO 474 and this comes from the current configuration flags */ 475 if (ata_id_has_dma(dev->id)) { 476 ata_dev_printk(dev, KERN_INFO, "configured for DMA\n"); 477 dev->xfer_mode = XFER_MW_DMA_0; 478 dev->xfer_shift = ATA_SHIFT_MWDMA; 479 dev->flags &= ~ATA_DFLAG_PIO; 480 } else { 481 ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); 482 dev->xfer_mode = XFER_PIO_0; 483 dev->xfer_shift = ATA_SHIFT_PIO; 484 dev->flags |= ATA_DFLAG_PIO; 485 } 486 } 487 return 0; 488} 489 490/** 491 * it821x_dev_config - Called each device identify 492 * @adev: Device that has just been identified 493 * 494 * Perform the initial setup needed for each device that is chip 495 * special. In our case we need to lock the sector count to avoid 496 * blowing the brains out of the firmware with large LBA48 requests 497 * 498 */ 499 500static void it821x_dev_config(struct ata_device *adev) 501{ 502 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 503 504 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 505 506 if (adev->max_sectors > 255) 507 adev->max_sectors = 255; 508 509 if (strstr(model_num, "Integrated Technology Express")) { 510 /* RAID mode */ 511 ata_dev_printk(adev, KERN_INFO, "%sRAID%d volume", 512 adev->id[147]?"Bootable ":"", 513 adev->id[129]); 514 if (adev->id[129] != 1) 515 printk("(%dK stripe)", adev->id[146]); 516 printk(".\n"); 517 } 518 /* This is a controller firmware triggered funny, don't 519 report the drive faulty! */ 520 adev->horkage &= ~ATA_HORKAGE_DIAGNOSTIC; 521 /* No HPA in 'smart' mode */ 522 adev->horkage |= ATA_HORKAGE_BROKEN_HPA; 523} 524 525/** 526 * it821x_read_id - Hack identify data up 527 * @adev: device to read 528 * @tf: proposed taskfile 529 * @id: buffer for returned ident data 530 * 531 * Query the devices on this firmware driven port and slightly 532 * mash the identify data to stop us and common tools trying to 533 * use features not firmware supported. The firmware itself does 534 * some masking (eg SMART) but not enough. 535 */ 536 537static unsigned int it821x_read_id(struct ata_device *adev, 538 struct ata_taskfile *tf, u16 *id) 539{ 540 unsigned int err_mask; 541 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 542 543 err_mask = ata_do_dev_read_id(adev, tf, id); 544 if (err_mask) 545 return err_mask; 546 ata_id_c_string(id, model_num, ATA_ID_PROD, sizeof(model_num)); 547 548 id[83] &= ~(1 << 12); /* Cache flush is firmware handled */ 549 id[83] &= ~(1 << 13); /* Ditto for LBA48 flushes */ 550 id[84] &= ~(1 << 6); /* No FUA */ 551 id[85] &= ~(1 << 10); /* No HPA */ 552 id[76] = 0; /* No NCQ/AN etc */ 553 554 if (strstr(model_num, "Integrated Technology Express")) { 555 /* Set feature bits the firmware neglects */ 556 id[49] |= 0x0300; /* LBA, DMA */ 557 id[83] &= 0x7FFF; 558 id[83] |= 0x4400; /* Word 83 is valid and LBA48 */ 559 id[86] |= 0x0400; /* LBA48 on */ 560 id[ATA_ID_MAJOR_VER] |= 0x1F; 561 /* Clear the serial number because it's different each boot 562 which breaks validation on resume */ 563 memset(&id[ATA_ID_SERNO], 0x20, ATA_ID_SERNO_LEN); 564 } 565 return err_mask; 566} 567 568/** 569 * it821x_check_atapi_dma - ATAPI DMA handler 570 * @qc: Command we are about to issue 571 * 572 * Decide if this ATAPI command can be issued by DMA on this 573 * controller. Return 0 if it can be. 574 */ 575 576static int it821x_check_atapi_dma(struct ata_queued_cmd *qc) 577{ 578 struct ata_port *ap = qc->ap; 579 struct it821x_dev *itdev = ap->private_data; 580 581 /* Only use dma for transfers to/from the media. */ 582 if (ata_qc_raw_nbytes(qc) < 2048) 583 return -EOPNOTSUPP; 584 585 /* No ATAPI DMA in smart mode */ 586 if (itdev->smart) 587 return -EOPNOTSUPP; 588 /* No ATAPI DMA on rev 10 */ 589 if (itdev->timing10) 590 return -EOPNOTSUPP; 591 /* Cool */ 592 return 0; 593} 594 595/** 596 * it821x_display_disk - display disk setup 597 * @n: Device number 598 * @buf: Buffer block from firmware 599 * 600 * Produce a nice informative display of the device setup as provided 601 * by the firmware. 602 */ 603 604static void it821x_display_disk(int n, u8 *buf) 605{ 606 unsigned char id[41]; 607 int mode = 0; 608 char *mtype = ""; 609 char mbuf[8]; 610 char *cbl = "(40 wire cable)"; 611 612 static const char *types[5] = { 613 "RAID0", "RAID1" "RAID 0+1", "JBOD", "DISK" 614 }; 615 616 if (buf[52] > 4) /* No Disk */ 617 return; 618 619 ata_id_c_string((u16 *)buf, id, 0, 41); 620 621 if (buf[51]) { 622 mode = ffs(buf[51]); 623 mtype = "UDMA"; 624 } else if (buf[49]) { 625 mode = ffs(buf[49]); 626 mtype = "MWDMA"; 627 } 628 629 if (buf[76]) 630 cbl = ""; 631 632 if (mode) 633 snprintf(mbuf, 8, "%5s%d", mtype, mode - 1); 634 else 635 strcpy(mbuf, "PIO"); 636 if (buf[52] == 4) 637 printk(KERN_INFO "%d: %-6s %-8s %s %s\n", 638 n, mbuf, types[buf[52]], id, cbl); 639 else 640 printk(KERN_INFO "%d: %-6s %-8s Volume: %1d %s %s\n", 641 n, mbuf, types[buf[52]], buf[53], id, cbl); 642 if (buf[125] < 100) 643 printk(KERN_INFO "%d: Rebuilding: %d%%\n", n, buf[125]); 644} 645 646/** 647 * it821x_firmware_command - issue firmware command 648 * @ap: IT821x port to interrogate 649 * @cmd: command 650 * @len: length 651 * 652 * Issue firmware commands expecting data back from the controller. We 653 * use this to issue commands that do not go via the normal paths. Other 654 * commands such as 0xFC can be issued normally. 655 */ 656 657static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len) 658{ 659 u8 status; 660 int n = 0; 661 u16 *buf = kmalloc(len, GFP_KERNEL); 662 if (buf == NULL) { 663 printk(KERN_ERR "it821x_firmware_command: Out of memory\n"); 664 return NULL; 665 } 666 /* This isn't quite a normal ATA command as we are talking to the 667 firmware not the drives */ 668 ap->ctl |= ATA_NIEN; 669 iowrite8(ap->ctl, ap->ioaddr.ctl_addr); 670 ata_wait_idle(ap); 671 iowrite8(ATA_DEVICE_OBS, ap->ioaddr.device_addr); 672 iowrite8(cmd, ap->ioaddr.command_addr); 673 udelay(1); 674 /* This should be almost immediate but a little paranoia goes a long 675 way. */ 676 while(n++ < 10) { 677 status = ioread8(ap->ioaddr.status_addr); 678 if (status & ATA_ERR) { 679 kfree(buf); 680 printk(KERN_ERR "it821x_firmware_command: rejected\n"); 681 return NULL; 682 } 683 if (status & ATA_DRQ) { 684 ioread16_rep(ap->ioaddr.data_addr, buf, len/2); 685 return (u8 *)buf; 686 } 687 mdelay(1); 688 } 689 kfree(buf); 690 printk(KERN_ERR "it821x_firmware_command: timeout\n"); 691 return NULL; 692} 693 694/** 695 * it821x_probe_firmware - firmware reporting/setup 696 * @ap: IT821x port being probed 697 * 698 * Probe the firmware of the controller by issuing firmware command 699 * 0xFA and analysing the returned data. 700 */ 701 702static void it821x_probe_firmware(struct ata_port *ap) 703{ 704 u8 *buf; 705 int i; 706 707 /* This is a bit ugly as we can't just issue a task file to a device 708 as this is controller magic */ 709 710 buf = it821x_firmware_command(ap, 0xFA, 512); 711 712 if (buf != NULL) { 713 printk(KERN_INFO "pata_it821x: Firmware %02X/%02X/%02X%02X\n", 714 buf[505], 715 buf[506], 716 buf[507], 717 buf[508]); 718 for (i = 0; i < 4; i++) 719 it821x_display_disk(i, buf + 128 * i); 720 kfree(buf); 721 } 722} 723 724 725 726/** 727 * it821x_port_start - port setup 728 * @ap: ATA port being set up 729 * 730 * The it821x needs to maintain private data structures and also to 731 * use the standard PCI interface which lacks support for this 732 * functionality. We instead set up the private data on the port 733 * start hook, and tear it down on port stop 734 */ 735 736static int it821x_port_start(struct ata_port *ap) 737{ 738 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 739 struct it821x_dev *itdev; 740 u8 conf; 741 742 int ret = ata_bmdma_port_start(ap); 743 if (ret < 0) 744 return ret; 745 746 itdev = devm_kzalloc(&pdev->dev, sizeof(struct it821x_dev), GFP_KERNEL); 747 if (itdev == NULL) 748 return -ENOMEM; 749 ap->private_data = itdev; 750 751 pci_read_config_byte(pdev, 0x50, &conf); 752 753 if (conf & 1) { 754 itdev->smart = 1; 755 /* Long I/O's although allowed in LBA48 space cause the 756 onboard firmware to enter the twighlight zone */ 757 /* No ATAPI DMA in this mode either */ 758 if (ap->port_no == 0) 759 it821x_probe_firmware(ap); 760 } 761 /* Pull the current clocks from 0x50 */ 762 if (conf & (1 << (1 + ap->port_no))) 763 itdev->clock_mode = ATA_50; 764 else 765 itdev->clock_mode = ATA_66; 766 767 itdev->want[0][1] = ATA_ANY; 768 itdev->want[1][1] = ATA_ANY; 769 itdev->last_device = -1; 770 771 if (pdev->revision == 0x10) { 772 itdev->timing10 = 1; 773 /* Need to disable ATAPI DMA for this case */ 774 if (!itdev->smart) 775 printk(KERN_WARNING DRV_NAME": Revision 0x10, workarounds activated.\n"); 776 } 777 778 return 0; 779} 780 781/** 782 * it821x_rdc_cable - Cable detect for RDC1010 783 * @ap: port we are checking 784 * 785 * Return the RDC1010 cable type. Unlike the IT821x we know how to do 786 * this and can do host side cable detect 787 */ 788 789static int it821x_rdc_cable(struct ata_port *ap) 790{ 791 u16 r40; 792 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 793 794 pci_read_config_word(pdev, 0x40, &r40); 795 if (r40 & (1 << (2 + ap->port_no))) 796 return ATA_CBL_PATA40; 797 return ATA_CBL_PATA80; 798} 799 800static struct scsi_host_template it821x_sht = { 801 ATA_BMDMA_SHT(DRV_NAME), 802}; 803 804static struct ata_port_operations it821x_smart_port_ops = { 805 .inherits = &ata_bmdma_port_ops, 806 807 .check_atapi_dma= it821x_check_atapi_dma, 808 .qc_issue = it821x_smart_qc_issue, 809 810 .cable_detect = ata_cable_80wire, 811 .set_mode = it821x_smart_set_mode, 812 .dev_config = it821x_dev_config, 813 .read_id = it821x_read_id, 814 815 .port_start = it821x_port_start, 816}; 817 818static struct ata_port_operations it821x_passthru_port_ops = { 819 .inherits = &ata_bmdma_port_ops, 820 821 .check_atapi_dma= it821x_check_atapi_dma, 822 .sff_dev_select = it821x_passthru_dev_select, 823 .bmdma_start = it821x_passthru_bmdma_start, 824 .bmdma_stop = it821x_passthru_bmdma_stop, 825 .qc_issue = it821x_passthru_qc_issue, 826 827 .cable_detect = ata_cable_unknown, 828 .set_piomode = it821x_passthru_set_piomode, 829 .set_dmamode = it821x_passthru_set_dmamode, 830 831 .port_start = it821x_port_start, 832}; 833 834static struct ata_port_operations it821x_rdc_port_ops = { 835 .inherits = &ata_bmdma_port_ops, 836 837 .check_atapi_dma= it821x_check_atapi_dma, 838 .sff_dev_select = it821x_passthru_dev_select, 839 .bmdma_start = it821x_passthru_bmdma_start, 840 .bmdma_stop = it821x_passthru_bmdma_stop, 841 .qc_issue = it821x_passthru_qc_issue, 842 843 .cable_detect = it821x_rdc_cable, 844 .set_piomode = it821x_passthru_set_piomode, 845 .set_dmamode = it821x_passthru_set_dmamode, 846 847 .port_start = it821x_port_start, 848}; 849 850static void it821x_disable_raid(struct pci_dev *pdev) 851{ 852 /* Neither the RDC nor the IT8211 */ 853 if (pdev->vendor != PCI_VENDOR_ID_ITE || 854 pdev->device != PCI_DEVICE_ID_ITE_8212) 855 return; 856 857 /* Reset local CPU, and set BIOS not ready */ 858 pci_write_config_byte(pdev, 0x5E, 0x01); 859 860 /* Set to bypass mode, and reset PCI bus */ 861 pci_write_config_byte(pdev, 0x50, 0x00); 862 pci_write_config_word(pdev, PCI_COMMAND, 863 PCI_COMMAND_PARITY | PCI_COMMAND_IO | 864 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 865 pci_write_config_word(pdev, 0x40, 0xA0F3); 866 867 pci_write_config_dword(pdev,0x4C, 0x02040204); 868 pci_write_config_byte(pdev, 0x42, 0x36); 869 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20); 870} 871 872 873static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 874{ 875 u8 conf; 876 877 static const struct ata_port_info info_smart = { 878 .flags = ATA_FLAG_SLAVE_POSS, 879 .pio_mask = ATA_PIO4, 880 .mwdma_mask = ATA_MWDMA2, 881 .udma_mask = ATA_UDMA6, 882 .port_ops = &it821x_smart_port_ops 883 }; 884 static const struct ata_port_info info_passthru = { 885 .flags = ATA_FLAG_SLAVE_POSS, 886 .pio_mask = ATA_PIO4, 887 .mwdma_mask = ATA_MWDMA2, 888 .udma_mask = ATA_UDMA6, 889 .port_ops = &it821x_passthru_port_ops 890 }; 891 static const struct ata_port_info info_rdc = { 892 .flags = ATA_FLAG_SLAVE_POSS, 893 .pio_mask = ATA_PIO4, 894 .mwdma_mask = ATA_MWDMA2, 895 .udma_mask = ATA_UDMA6, 896 .port_ops = &it821x_rdc_port_ops 897 }; 898 static const struct ata_port_info info_rdc_11 = { 899 .flags = ATA_FLAG_SLAVE_POSS, 900 .pio_mask = ATA_PIO4, 901 .mwdma_mask = ATA_MWDMA2, 902 /* No UDMA */ 903 .port_ops = &it821x_rdc_port_ops 904 }; 905 906 const struct ata_port_info *ppi[] = { NULL, NULL }; 907 static char *mode[2] = { "pass through", "smart" }; 908 int rc; 909 910 rc = pcim_enable_device(pdev); 911 if (rc) 912 return rc; 913 914 if (pdev->vendor == PCI_VENDOR_ID_RDC) { 915 /* Deal with Vortex86SX */ 916 if (pdev->revision == 0x11) 917 ppi[0] = &info_rdc_11; 918 else 919 ppi[0] = &info_rdc; 920 } else { 921 /* Force the card into bypass mode if so requested */ 922 if (it8212_noraid) { 923 printk(KERN_INFO DRV_NAME ": forcing bypass mode.\n"); 924 it821x_disable_raid(pdev); 925 } 926 pci_read_config_byte(pdev, 0x50, &conf); 927 conf &= 1; 928 929 printk(KERN_INFO DRV_NAME": controller in %s mode.\n", 930 mode[conf]); 931 if (conf == 0) 932 ppi[0] = &info_passthru; 933 else 934 ppi[0] = &info_smart; 935 } 936 return ata_pci_bmdma_init_one(pdev, ppi, &it821x_sht, NULL, 0); 937} 938 939#ifdef CONFIG_PM 940static int it821x_reinit_one(struct pci_dev *pdev) 941{ 942 struct ata_host *host = dev_get_drvdata(&pdev->dev); 943 int rc; 944 945 rc = ata_pci_device_do_resume(pdev); 946 if (rc) 947 return rc; 948 /* Resume - turn raid back off if need be */ 949 if (it8212_noraid) 950 it821x_disable_raid(pdev); 951 ata_host_resume(host); 952 return rc; 953} 954#endif 955 956static const struct pci_device_id it821x[] = { 957 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), }, 958 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), }, 959 { PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), }, 960 961 { }, 962}; 963 964static struct pci_driver it821x_pci_driver = { 965 .name = DRV_NAME, 966 .id_table = it821x, 967 .probe = it821x_init_one, 968 .remove = ata_pci_remove_one, 969#ifdef CONFIG_PM 970 .suspend = ata_pci_device_suspend, 971 .resume = it821x_reinit_one, 972#endif 973}; 974 975static int __init it821x_init(void) 976{ 977 return pci_register_driver(&it821x_pci_driver); 978} 979 980static void __exit it821x_exit(void) 981{ 982 pci_unregister_driver(&it821x_pci_driver); 983} 984 985MODULE_AUTHOR("Alan Cox"); 986MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller"); 987MODULE_LICENSE("GPL"); 988MODULE_DEVICE_TABLE(pci, it821x); 989MODULE_VERSION(DRV_VERSION); 990 991 992module_param_named(noraid, it8212_noraid, int, S_IRUGO); 993MODULE_PARM_DESC(noraid, "Force card into bypass mode"); 994 995module_init(it821x_init); 996module_exit(it821x_exit); 997