1/* 2 * pata_cmd64x.c - CMD64x PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@lxorguk.ukuu.org.uk> 5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz 6 * 7 * Based upon 8 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 9 * 10 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. 11 * Note, this driver is not used at all on other systems because 12 * there the "BIOS" has done all of the following already. 13 * Due to massive hardware bugs, UltraDMA is only supported 14 * on the 646U2 and not on the 646U. 15 * 16 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 17 * Copyright (C) 1998 David S. Miller (davem@redhat.com) 18 * 19 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 20 * 21 * TODO 22 * Testing work 23 */ 24 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/init.h> 29#include <linux/blkdev.h> 30#include <linux/delay.h> 31#include <scsi/scsi_host.h> 32#include <linux/libata.h> 33 34#define DRV_NAME "pata_cmd64x" 35#define DRV_VERSION "0.2.5" 36 37/* 38 * CMD64x specific registers definition. 39 */ 40 41enum { 42 CFR = 0x50, 43 CFR_INTR_CH0 = 0x04, 44 CMDTIM = 0x52, 45 ARTTIM0 = 0x53, 46 DRWTIM0 = 0x54, 47 ARTTIM1 = 0x55, 48 DRWTIM1 = 0x56, 49 ARTTIM23 = 0x57, 50 ARTTIM23_DIS_RA2 = 0x04, 51 ARTTIM23_DIS_RA3 = 0x08, 52 ARTTIM23_INTR_CH1 = 0x10, 53 DRWTIM2 = 0x58, 54 BRST = 0x59, 55 DRWTIM3 = 0x5b, 56 BMIDECR0 = 0x70, 57 MRDMODE = 0x71, 58 MRDMODE_INTR_CH0 = 0x04, 59 MRDMODE_INTR_CH1 = 0x08, 60 BMIDESR0 = 0x72, 61 UDIDETCR0 = 0x73, 62 DTPR0 = 0x74, 63 BMIDECR1 = 0x78, 64 BMIDECSR = 0x79, 65 UDIDETCR1 = 0x7B, 66 DTPR1 = 0x7C 67}; 68 69static int cmd648_cable_detect(struct ata_port *ap) 70{ 71 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 72 u8 r; 73 74 /* Check cable detect bits */ 75 pci_read_config_byte(pdev, BMIDECSR, &r); 76 if (r & (1 << ap->port_no)) 77 return ATA_CBL_PATA80; 78 return ATA_CBL_PATA40; 79} 80 81/** 82 * cmd64x_set_piomode - set PIO and MWDMA timing 83 * @ap: ATA interface 84 * @adev: ATA device 85 * @mode: mode 86 * 87 * Called to do the PIO and MWDMA mode setup. 88 */ 89 90static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode) 91{ 92 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 93 struct ata_timing t; 94 const unsigned long T = 1000000 / 33; 95 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; 96 97 u8 reg; 98 99 /* Port layout is not logical so use a table */ 100 const u8 arttim_port[2][2] = { 101 { ARTTIM0, ARTTIM1 }, 102 { ARTTIM23, ARTTIM23 } 103 }; 104 const u8 drwtim_port[2][2] = { 105 { DRWTIM0, DRWTIM1 }, 106 { DRWTIM2, DRWTIM3 } 107 }; 108 109 int arttim = arttim_port[ap->port_no][adev->devno]; 110 int drwtim = drwtim_port[ap->port_no][adev->devno]; 111 112 /* ata_timing_compute is smart and will produce timings for MWDMA 113 that don't violate the drives PIO capabilities. */ 114 if (ata_timing_compute(adev, mode, &t, T, 0) < 0) { 115 printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); 116 return; 117 } 118 if (ap->port_no) { 119 /* Slave has shared address setup */ 120 struct ata_device *pair = ata_dev_pair(adev); 121 122 if (pair) { 123 struct ata_timing tp; 124 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); 125 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 126 } 127 } 128 129 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", 130 t.active, t.recover, t.setup); 131 if (t.recover > 16) { 132 t.active += t.recover - 16; 133 t.recover = 16; 134 } 135 if (t.active > 16) 136 t.active = 16; 137 138 /* Now convert the clocks into values we can actually stuff into 139 the chip */ 140 141 if (t.recover == 16) 142 t.recover = 0; 143 else if (t.recover > 1) 144 t.recover--; 145 else 146 t.recover = 15; 147 148 if (t.setup > 4) 149 t.setup = 0xC0; 150 else 151 t.setup = setup_data[t.setup]; 152 153 t.active &= 0x0F; /* 0 = 16 */ 154 155 /* Load setup timing */ 156 pci_read_config_byte(pdev, arttim, ®); 157 reg &= 0x3F; 158 reg |= t.setup; 159 pci_write_config_byte(pdev, arttim, reg); 160 161 /* Load active/recovery */ 162 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); 163} 164 165/** 166 * cmd64x_set_piomode - set initial PIO mode data 167 * @ap: ATA interface 168 * @adev: ATA device 169 * 170 * Used when configuring the devices ot set the PIO timings. All the 171 * actual work is done by the PIO/MWDMA setting helper 172 */ 173 174static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) 175{ 176 cmd64x_set_timing(ap, adev, adev->pio_mode); 177} 178 179/** 180 * cmd64x_set_dmamode - set initial DMA mode data 181 * @ap: ATA interface 182 * @adev: ATA device 183 * 184 * Called to do the DMA mode setup. 185 */ 186 187static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 188{ 189 static const u8 udma_data[] = { 190 0x30, 0x20, 0x10, 0x20, 0x10, 0x00 191 }; 192 193 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 194 u8 regU, regD; 195 196 int pciU = UDIDETCR0 + 8 * ap->port_no; 197 int pciD = BMIDESR0 + 8 * ap->port_no; 198 int shift = 2 * adev->devno; 199 200 pci_read_config_byte(pdev, pciD, ®D); 201 pci_read_config_byte(pdev, pciU, ®U); 202 203 /* DMA bits off */ 204 regD &= ~(0x20 << adev->devno); 205 /* DMA control bits */ 206 regU &= ~(0x30 << shift); 207 /* DMA timing bits */ 208 regU &= ~(0x05 << adev->devno); 209 210 if (adev->dma_mode >= XFER_UDMA_0) { 211 /* Merge the timing value */ 212 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; 213 /* Merge the control bits */ 214 regU |= 1 << adev->devno; /* UDMA on */ 215 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */ 216 regU |= 4 << adev->devno; 217 } else { 218 regU &= ~ (1 << adev->devno); /* UDMA off */ 219 cmd64x_set_timing(ap, adev, adev->dma_mode); 220 } 221 222 regD |= 0x20 << adev->devno; 223 224 pci_write_config_byte(pdev, pciU, regU); 225 pci_write_config_byte(pdev, pciD, regD); 226} 227 228/** 229 * cmd648_dma_stop - DMA stop callback 230 * @qc: Command in progress 231 * 232 * DMA has completed. 233 */ 234 235static void cmd648_bmdma_stop(struct ata_queued_cmd *qc) 236{ 237 struct ata_port *ap = qc->ap; 238 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 239 u8 dma_intr; 240 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; 241 int dma_reg = ap->port_no ? ARTTIM23 : CFR; 242 243 ata_bmdma_stop(qc); 244 245 pci_read_config_byte(pdev, dma_reg, &dma_intr); 246 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask); 247} 248 249/** 250 * cmd646r1_dma_stop - DMA stop callback 251 * @qc: Command in progress 252 * 253 * Stub for now while investigating the r1 quirk in the old driver. 254 */ 255 256static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc) 257{ 258 ata_bmdma_stop(qc); 259} 260 261static struct scsi_host_template cmd64x_sht = { 262 ATA_BMDMA_SHT(DRV_NAME), 263}; 264 265static const struct ata_port_operations cmd64x_base_ops = { 266 .inherits = &ata_bmdma_port_ops, 267 .set_piomode = cmd64x_set_piomode, 268 .set_dmamode = cmd64x_set_dmamode, 269}; 270 271static struct ata_port_operations cmd64x_port_ops = { 272 .inherits = &cmd64x_base_ops, 273 .cable_detect = ata_cable_40wire, 274}; 275 276static struct ata_port_operations cmd646r1_port_ops = { 277 .inherits = &cmd64x_base_ops, 278 .bmdma_stop = cmd646r1_bmdma_stop, 279 .cable_detect = ata_cable_40wire, 280}; 281 282static struct ata_port_operations cmd648_port_ops = { 283 .inherits = &cmd64x_base_ops, 284 .bmdma_stop = cmd648_bmdma_stop, 285 .cable_detect = cmd648_cable_detect, 286}; 287 288static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 289{ 290 static const struct ata_port_info cmd_info[6] = { 291 { /* CMD 643 - no UDMA */ 292 .flags = ATA_FLAG_SLAVE_POSS, 293 .pio_mask = ATA_PIO4, 294 .mwdma_mask = ATA_MWDMA2, 295 .port_ops = &cmd64x_port_ops 296 }, 297 { /* CMD 646 with broken UDMA */ 298 .flags = ATA_FLAG_SLAVE_POSS, 299 .pio_mask = ATA_PIO4, 300 .mwdma_mask = ATA_MWDMA2, 301 .port_ops = &cmd64x_port_ops 302 }, 303 { /* CMD 646 with working UDMA */ 304 .flags = ATA_FLAG_SLAVE_POSS, 305 .pio_mask = ATA_PIO4, 306 .mwdma_mask = ATA_MWDMA2, 307 .udma_mask = ATA_UDMA2, 308 .port_ops = &cmd64x_port_ops 309 }, 310 { /* CMD 646 rev 1 */ 311 .flags = ATA_FLAG_SLAVE_POSS, 312 .pio_mask = ATA_PIO4, 313 .mwdma_mask = ATA_MWDMA2, 314 .port_ops = &cmd646r1_port_ops 315 }, 316 { /* CMD 648 */ 317 .flags = ATA_FLAG_SLAVE_POSS, 318 .pio_mask = ATA_PIO4, 319 .mwdma_mask = ATA_MWDMA2, 320 .udma_mask = ATA_UDMA4, 321 .port_ops = &cmd648_port_ops 322 }, 323 { /* CMD 649 */ 324 .flags = ATA_FLAG_SLAVE_POSS, 325 .pio_mask = ATA_PIO4, 326 .mwdma_mask = ATA_MWDMA2, 327 .udma_mask = ATA_UDMA5, 328 .port_ops = &cmd648_port_ops 329 } 330 }; 331 const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL }; 332 u8 mrdmode; 333 int rc; 334 335 rc = pcim_enable_device(pdev); 336 if (rc) 337 return rc; 338 339 if (id->driver_data == 0) /* 643 */ 340 ata_pci_bmdma_clear_simplex(pdev); 341 342 if (pdev->device == PCI_DEVICE_ID_CMD_646) { 343 /* Does UDMA work ? */ 344 if (pdev->revision > 4) 345 ppi[0] = &cmd_info[2]; 346 /* Early rev with other problems ? */ 347 else if (pdev->revision == 1) 348 ppi[0] = &cmd_info[3]; 349 } 350 351 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 352 pci_read_config_byte(pdev, MRDMODE, &mrdmode); 353 mrdmode &= ~ 0x30; /* IRQ set up */ 354 mrdmode |= 0x02; /* Memory read line enable */ 355 pci_write_config_byte(pdev, MRDMODE, mrdmode); 356 357 /* Force PIO 0 here.. */ 358 359 /* PPC specific fixup copied from old driver */ 360#ifdef CONFIG_PPC 361 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 362#endif 363 364 return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0); 365} 366 367#ifdef CONFIG_PM 368static int cmd64x_reinit_one(struct pci_dev *pdev) 369{ 370 struct ata_host *host = dev_get_drvdata(&pdev->dev); 371 u8 mrdmode; 372 int rc; 373 374 rc = ata_pci_device_do_resume(pdev); 375 if (rc) 376 return rc; 377 378 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 379 pci_read_config_byte(pdev, MRDMODE, &mrdmode); 380 mrdmode &= ~ 0x30; /* IRQ set up */ 381 mrdmode |= 0x02; /* Memory read line enable */ 382 pci_write_config_byte(pdev, MRDMODE, mrdmode); 383#ifdef CONFIG_PPC 384 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 385#endif 386 ata_host_resume(host); 387 return 0; 388} 389#endif 390 391static const struct pci_device_id cmd64x[] = { 392 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, 393 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, 394 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 }, 395 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 }, 396 397 { }, 398}; 399 400static struct pci_driver cmd64x_pci_driver = { 401 .name = DRV_NAME, 402 .id_table = cmd64x, 403 .probe = cmd64x_init_one, 404 .remove = ata_pci_remove_one, 405#ifdef CONFIG_PM 406 .suspend = ata_pci_device_suspend, 407 .resume = cmd64x_reinit_one, 408#endif 409}; 410 411static int __init cmd64x_init(void) 412{ 413 return pci_register_driver(&cmd64x_pci_driver); 414} 415 416static void __exit cmd64x_exit(void) 417{ 418 pci_unregister_driver(&cmd64x_pci_driver); 419} 420 421MODULE_AUTHOR("Alan Cox"); 422MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers"); 423MODULE_LICENSE("GPL"); 424MODULE_DEVICE_TABLE(pci, cmd64x); 425MODULE_VERSION(DRV_VERSION); 426 427module_init(cmd64x_init); 428module_exit(cmd64x_exit); 429