1/* 2 * pata_artop.c - ARTOP ATA controller driver 3 * 4 * (C) 2006 Red Hat 5 * (C) 2007 Bartlomiej Zolnierkiewicz 6 * 7 * Based in part on drivers/ide/pci/aec62xx.c 8 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 9 * 865/865R fixes for Macintosh card version from a patch to the old 10 * driver by Thibaut VARENE <varenet@parisc-linux.org> 11 * When setting the PCI latency we must set 0x80 or higher for burst 12 * performance Alessandro Zummo <alessandro.zummo@towertech.it> 13 * 14 * TODO 15 * Investigate no_dsc on 850R 16 * Clock detect 17 */ 18 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/pci.h> 22#include <linux/init.h> 23#include <linux/blkdev.h> 24#include <linux/delay.h> 25#include <linux/device.h> 26#include <scsi/scsi_host.h> 27#include <linux/libata.h> 28#include <linux/ata.h> 29 30#define DRV_NAME "pata_artop" 31#define DRV_VERSION "0.4.5" 32 33/* 34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we 35 * get PCI bus speed functionality we leave this as 0. Its a variable 36 * for when we get the functionality and also for folks wanting to 37 * test stuff. 38 */ 39 40static int clock = 0; 41 42static int artop6210_pre_reset(struct ata_link *link, unsigned long deadline) 43{ 44 struct ata_port *ap = link->ap; 45 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 46 const struct pci_bits artop_enable_bits[] = { 47 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 48 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 49 }; 50 51 if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) 52 return -ENOENT; 53 54 return ata_sff_prereset(link, deadline); 55} 56 57/** 58 * artop6260_pre_reset - check for 40/80 pin 59 * @link: link 60 * @deadline: deadline jiffies for the operation 61 * 62 * The ARTOP hardware reports the cable detect bits in register 0x49. 63 * Nothing complicated needed here. 64 */ 65 66static int artop6260_pre_reset(struct ata_link *link, unsigned long deadline) 67{ 68 static const struct pci_bits artop_enable_bits[] = { 69 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 70 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 71 }; 72 73 struct ata_port *ap = link->ap; 74 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 75 76 /* Odd numbered device ids are the units with enable bits (the -R cards) */ 77 if ((pdev->device & 1) && 78 !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) 79 return -ENOENT; 80 81 return ata_sff_prereset(link, deadline); 82} 83 84/** 85 * artop6260_cable_detect - identify cable type 86 * @ap: Port 87 * 88 * Identify the cable type for the ARTOP interface in question 89 */ 90 91static int artop6260_cable_detect(struct ata_port *ap) 92{ 93 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 94 u8 tmp; 95 pci_read_config_byte(pdev, 0x49, &tmp); 96 if (tmp & (1 << ap->port_no)) 97 return ATA_CBL_PATA40; 98 return ATA_CBL_PATA80; 99} 100 101/** 102 * artop6210_load_piomode - Load a set of PATA PIO timings 103 * @ap: Port whose timings we are configuring 104 * @adev: Device 105 * @pio: PIO mode 106 * 107 * Set PIO mode for device, in host controller PCI config space. This 108 * is used both to set PIO timings in PIO mode and also to set the 109 * matching PIO clocking for UDMA, as well as the MWDMA timings. 110 * 111 * LOCKING: 112 * None (inherited from caller). 113 */ 114 115static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio) 116{ 117 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 118 int dn = adev->devno + 2 * ap->port_no; 119 const u16 timing[2][5] = { 120 { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 }, 121 { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 } 122 123 }; 124 /* Load the PIO timing active/recovery bits */ 125 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); 126} 127 128/** 129 * artop6210_set_piomode - Initialize host controller PATA PIO timings 130 * @ap: Port whose timings we are configuring 131 * @adev: Device we are configuring 132 * 133 * Set PIO mode for device, in host controller PCI config space. For 134 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In 135 * the event UDMA is used the later call to set_dmamode will set the 136 * bits as required. 137 * 138 * LOCKING: 139 * None (inherited from caller). 140 */ 141 142static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev) 143{ 144 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 145 int dn = adev->devno + 2 * ap->port_no; 146 u8 ultra; 147 148 artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 149 150 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ 151 pci_read_config_byte(pdev, 0x54, &ultra); 152 ultra &= ~(3 << (2 * dn)); 153 pci_write_config_byte(pdev, 0x54, ultra); 154} 155 156/** 157 * artop6260_load_piomode - Initialize host controller PATA PIO timings 158 * @ap: Port whose timings we are configuring 159 * @adev: Device we are configuring 160 * @pio: PIO mode 161 * 162 * Set PIO mode for device, in host controller PCI config space. The 163 * ARTOP6260 and relatives store the timing data differently. 164 * 165 * LOCKING: 166 * None (inherited from caller). 167 */ 168 169static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio) 170{ 171 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 172 int dn = adev->devno + 2 * ap->port_no; 173 const u8 timing[2][5] = { 174 { 0x00, 0x0A, 0x08, 0x33, 0x31 }, 175 { 0x70, 0x7A, 0x78, 0x43, 0x41 } 176 177 }; 178 /* Load the PIO timing active/recovery bits */ 179 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]); 180} 181 182/** 183 * artop6260_set_piomode - Initialize host controller PATA PIO timings 184 * @ap: Port whose timings we are configuring 185 * @adev: Device we are configuring 186 * 187 * Set PIO mode for device, in host controller PCI config space. For 188 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In 189 * the event UDMA is used the later call to set_dmamode will set the 190 * bits as required. 191 * 192 * LOCKING: 193 * None (inherited from caller). 194 */ 195 196static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev) 197{ 198 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 199 u8 ultra; 200 201 artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 202 203 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ 204 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); 205 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ 206 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); 207} 208 209/** 210 * artop6210_set_dmamode - Initialize host controller PATA PIO timings 211 * @ap: Port whose timings we are configuring 212 * @adev: Device whose timings we are configuring 213 * 214 * Set DMA mode for device, in host controller PCI config space. 215 * 216 * LOCKING: 217 * None (inherited from caller). 218 */ 219 220static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev) 221{ 222 unsigned int pio; 223 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 224 int dn = adev->devno + 2 * ap->port_no; 225 u8 ultra; 226 227 if (adev->dma_mode == XFER_MW_DMA_0) 228 pio = 1; 229 else 230 pio = 4; 231 232 /* Load the PIO timing active/recovery bits */ 233 artop6210_load_piomode(ap, adev, pio); 234 235 pci_read_config_byte(pdev, 0x54, &ultra); 236 ultra &= ~(3 << (2 * dn)); 237 238 /* Add ultra DMA bits if in UDMA mode */ 239 if (adev->dma_mode >= XFER_UDMA_0) { 240 u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock; 241 if (mode == 0) 242 mode = 1; 243 ultra |= (mode << (2 * dn)); 244 } 245 pci_write_config_byte(pdev, 0x54, ultra); 246} 247 248/** 249 * artop6260_set_dmamode - Initialize host controller PATA PIO timings 250 * @ap: Port whose timings we are configuring 251 * @adev: Device we are configuring 252 * 253 * Set DMA mode for device, in host controller PCI config space. The 254 * ARTOP6260 and relatives store the timing data differently. 255 * 256 * LOCKING: 257 * None (inherited from caller). 258 */ 259 260static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev) 261{ 262 unsigned int pio = adev->pio_mode - XFER_PIO_0; 263 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 264 u8 ultra; 265 266 if (adev->dma_mode == XFER_MW_DMA_0) 267 pio = 1; 268 else 269 pio = 4; 270 271 /* Load the PIO timing active/recovery bits */ 272 artop6260_load_piomode(ap, adev, pio); 273 274 /* Add ultra DMA bits if in UDMA mode */ 275 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra); 276 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */ 277 if (adev->dma_mode >= XFER_UDMA_0) { 278 u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock; 279 if (mode == 0) 280 mode = 1; 281 ultra |= (mode << (4 * adev->devno)); 282 } 283 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra); 284} 285 286/** 287 * artop_6210_qc_defer - implement serialization 288 * @qc: command 289 * 290 * Issue commands per host on this chip. 291 */ 292 293static int artop6210_qc_defer(struct ata_queued_cmd *qc) 294{ 295 struct ata_host *host = qc->ap->host; 296 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no]; 297 int rc; 298 299 /* First apply the usual rules */ 300 rc = ata_std_qc_defer(qc); 301 if (rc != 0) 302 return rc; 303 304 /* Now apply serialization rules. Only allow a command if the 305 other channel state machine is idle */ 306 if (alt && alt->qc_active) 307 return ATA_DEFER_PORT; 308 return 0; 309} 310 311static struct scsi_host_template artop_sht = { 312 ATA_BMDMA_SHT(DRV_NAME), 313}; 314 315static struct ata_port_operations artop6210_ops = { 316 .inherits = &ata_bmdma_port_ops, 317 .cable_detect = ata_cable_40wire, 318 .set_piomode = artop6210_set_piomode, 319 .set_dmamode = artop6210_set_dmamode, 320 .prereset = artop6210_pre_reset, 321 .qc_defer = artop6210_qc_defer, 322}; 323 324static struct ata_port_operations artop6260_ops = { 325 .inherits = &ata_bmdma_port_ops, 326 .cable_detect = artop6260_cable_detect, 327 .set_piomode = artop6260_set_piomode, 328 .set_dmamode = artop6260_set_dmamode, 329 .prereset = artop6260_pre_reset, 330}; 331 332 333/** 334 * artop_init_one - Register ARTOP ATA PCI device with kernel services 335 * @pdev: PCI device to register 336 * @ent: Entry in artop_pci_tbl matching with @pdev 337 * 338 * Called from kernel PCI layer. 339 * 340 * LOCKING: 341 * Inherited from PCI layer (may sleep). 342 * 343 * RETURNS: 344 * Zero on success, or -ERRNO value. 345 */ 346 347static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id) 348{ 349 static int printed_version; 350 static const struct ata_port_info info_6210 = { 351 .flags = ATA_FLAG_SLAVE_POSS, 352 .pio_mask = ATA_PIO4, 353 .mwdma_mask = ATA_MWDMA2, 354 .udma_mask = ATA_UDMA2, 355 .port_ops = &artop6210_ops, 356 }; 357 static const struct ata_port_info info_626x = { 358 .flags = ATA_FLAG_SLAVE_POSS, 359 .pio_mask = ATA_PIO4, 360 .mwdma_mask = ATA_MWDMA2, 361 .udma_mask = ATA_UDMA4, 362 .port_ops = &artop6260_ops, 363 }; 364 static const struct ata_port_info info_628x = { 365 .flags = ATA_FLAG_SLAVE_POSS, 366 .pio_mask = ATA_PIO4, 367 .mwdma_mask = ATA_MWDMA2, 368 .udma_mask = ATA_UDMA5, 369 .port_ops = &artop6260_ops, 370 }; 371 static const struct ata_port_info info_628x_fast = { 372 .flags = ATA_FLAG_SLAVE_POSS, 373 .pio_mask = ATA_PIO4, 374 .mwdma_mask = ATA_MWDMA2, 375 .udma_mask = ATA_UDMA6, 376 .port_ops = &artop6260_ops, 377 }; 378 const struct ata_port_info *ppi[] = { NULL, NULL }; 379 int rc; 380 381 if (!printed_version++) 382 dev_printk(KERN_DEBUG, &pdev->dev, 383 "version " DRV_VERSION "\n"); 384 385 rc = pcim_enable_device(pdev); 386 if (rc) 387 return rc; 388 389 if (id->driver_data == 0) { /* 6210 variant */ 390 ppi[0] = &info_6210; 391 /* BIOS may have left us in UDMA, clear it before libata probe */ 392 pci_write_config_byte(pdev, 0x54, 0); 393 } 394 else if (id->driver_data == 1) /* 6260 */ 395 ppi[0] = &info_626x; 396 else if (id->driver_data == 2) { /* 6280 or 6280 + fast */ 397 unsigned long io = pci_resource_start(pdev, 4); 398 u8 reg; 399 400 ppi[0] = &info_628x; 401 if (inb(io) & 0x10) 402 ppi[0] = &info_628x_fast; 403 /* Mac systems come up with some registers not set as we 404 will need them */ 405 406 /* Clear reset & test bits */ 407 pci_read_config_byte(pdev, 0x49, ®); 408 pci_write_config_byte(pdev, 0x49, reg & ~ 0x30); 409 410 /* PCI latency must be > 0x80 for burst mode, tweak it 411 * if required. 412 */ 413 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®); 414 if (reg <= 0x80) 415 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90); 416 417 /* Enable IRQ output and burst mode */ 418 pci_read_config_byte(pdev, 0x4a, ®); 419 pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80); 420 421 } 422 423 BUG_ON(ppi[0] == NULL); 424 425 return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0); 426} 427 428static const struct pci_device_id artop_pci_tbl[] = { 429 { PCI_VDEVICE(ARTOP, 0x0005), 0 }, 430 { PCI_VDEVICE(ARTOP, 0x0006), 1 }, 431 { PCI_VDEVICE(ARTOP, 0x0007), 1 }, 432 { PCI_VDEVICE(ARTOP, 0x0008), 2 }, 433 { PCI_VDEVICE(ARTOP, 0x0009), 2 }, 434 435 { } /* terminate list */ 436}; 437 438static struct pci_driver artop_pci_driver = { 439 .name = DRV_NAME, 440 .id_table = artop_pci_tbl, 441 .probe = artop_init_one, 442 .remove = ata_pci_remove_one, 443}; 444 445static int __init artop_init(void) 446{ 447 return pci_register_driver(&artop_pci_driver); 448} 449 450static void __exit artop_exit(void) 451{ 452 pci_unregister_driver(&artop_pci_driver); 453} 454 455module_init(artop_init); 456module_exit(artop_exit); 457 458MODULE_AUTHOR("Alan Cox"); 459MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA"); 460MODULE_LICENSE("GPL"); 461MODULE_DEVICE_TABLE(pci, artop_pci_tbl); 462MODULE_VERSION(DRV_VERSION); 463