1/* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35#include <linux/kernel.h> 36#include <linux/gfp.h> 37#include <linux/module.h> 38#include <linux/init.h> 39#include <linux/blkdev.h> 40#include <linux/delay.h> 41#include <linux/interrupt.h> 42#include <linux/dma-mapping.h> 43#include <linux/device.h> 44#include <scsi/scsi_host.h> 45#include <scsi/scsi_cmnd.h> 46#include <linux/libata.h> 47#include "ahci.h" 48 49static int ahci_skip_host_reset; 50int ahci_ignore_sss; 51EXPORT_SYMBOL_GPL(ahci_ignore_sss); 52 53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 55 56module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 57MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 58 59static int ahci_enable_alpm(struct ata_port *ap, 60 enum link_pm policy); 61static void ahci_disable_alpm(struct ata_port *ap); 62static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 63static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 64 size_t size); 65static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 66 ssize_t size); 67 68 69 70static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 71static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 72static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 73static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 74static int ahci_port_start(struct ata_port *ap); 75static void ahci_port_stop(struct ata_port *ap); 76static void ahci_qc_prep(struct ata_queued_cmd *qc); 77static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 78static void ahci_freeze(struct ata_port *ap); 79static void ahci_thaw(struct ata_port *ap); 80static void ahci_enable_fbs(struct ata_port *ap); 81static void ahci_disable_fbs(struct ata_port *ap); 82static void ahci_pmp_attach(struct ata_port *ap); 83static void ahci_pmp_detach(struct ata_port *ap); 84static int ahci_softreset(struct ata_link *link, unsigned int *class, 85 unsigned long deadline); 86static int ahci_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88static void ahci_postreset(struct ata_link *link, unsigned int *class); 89static void ahci_error_handler(struct ata_port *ap); 90static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 91static int ahci_port_resume(struct ata_port *ap); 92static void ahci_dev_config(struct ata_device *dev); 93static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 94 u32 opts); 95#ifdef CONFIG_PM 96static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 97#endif 98static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 99static ssize_t ahci_activity_store(struct ata_device *dev, 100 enum sw_activity val); 101static void ahci_init_sw_activity(struct ata_link *link); 102 103static ssize_t ahci_show_host_caps(struct device *dev, 104 struct device_attribute *attr, char *buf); 105static ssize_t ahci_show_host_cap2(struct device *dev, 106 struct device_attribute *attr, char *buf); 107static ssize_t ahci_show_host_version(struct device *dev, 108 struct device_attribute *attr, char *buf); 109static ssize_t ahci_show_port_cmd(struct device *dev, 110 struct device_attribute *attr, char *buf); 111static ssize_t ahci_read_em_buffer(struct device *dev, 112 struct device_attribute *attr, char *buf); 113static ssize_t ahci_store_em_buffer(struct device *dev, 114 struct device_attribute *attr, 115 const char *buf, size_t size); 116 117static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 118static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 119static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 120static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 121static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 122 ahci_read_em_buffer, ahci_store_em_buffer); 123 124struct device_attribute *ahci_shost_attrs[] = { 125 &dev_attr_link_power_management_policy, 126 &dev_attr_em_message_type, 127 &dev_attr_em_message, 128 &dev_attr_ahci_host_caps, 129 &dev_attr_ahci_host_cap2, 130 &dev_attr_ahci_host_version, 131 &dev_attr_ahci_port_cmd, 132 &dev_attr_em_buffer, 133 NULL 134}; 135EXPORT_SYMBOL_GPL(ahci_shost_attrs); 136 137struct device_attribute *ahci_sdev_attrs[] = { 138 &dev_attr_sw_activity, 139 &dev_attr_unload_heads, 140 NULL 141}; 142EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 143 144struct ata_port_operations ahci_ops = { 145 .inherits = &sata_pmp_port_ops, 146 147 .qc_defer = ahci_pmp_qc_defer, 148 .qc_prep = ahci_qc_prep, 149 .qc_issue = ahci_qc_issue, 150 .qc_fill_rtf = ahci_qc_fill_rtf, 151 152 .freeze = ahci_freeze, 153 .thaw = ahci_thaw, 154 .softreset = ahci_softreset, 155 .hardreset = ahci_hardreset, 156 .postreset = ahci_postreset, 157 .pmp_softreset = ahci_softreset, 158 .error_handler = ahci_error_handler, 159 .post_internal_cmd = ahci_post_internal_cmd, 160 .dev_config = ahci_dev_config, 161 162 .scr_read = ahci_scr_read, 163 .scr_write = ahci_scr_write, 164 .pmp_attach = ahci_pmp_attach, 165 .pmp_detach = ahci_pmp_detach, 166 167 .enable_pm = ahci_enable_alpm, 168 .disable_pm = ahci_disable_alpm, 169 .em_show = ahci_led_show, 170 .em_store = ahci_led_store, 171 .sw_activity_show = ahci_activity_show, 172 .sw_activity_store = ahci_activity_store, 173#ifdef CONFIG_PM 174 .port_suspend = ahci_port_suspend, 175 .port_resume = ahci_port_resume, 176#endif 177 .port_start = ahci_port_start, 178 .port_stop = ahci_port_stop, 179}; 180EXPORT_SYMBOL_GPL(ahci_ops); 181 182int ahci_em_messages = 1; 183EXPORT_SYMBOL_GPL(ahci_em_messages); 184module_param(ahci_em_messages, int, 0444); 185/* add other LED protocol types when they become supported */ 186MODULE_PARM_DESC(ahci_em_messages, 187 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 188 189static void ahci_enable_ahci(void __iomem *mmio) 190{ 191 int i; 192 u32 tmp; 193 194 /* turn on AHCI_EN */ 195 tmp = readl(mmio + HOST_CTL); 196 if (tmp & HOST_AHCI_EN) 197 return; 198 199 /* Some controllers need AHCI_EN to be written multiple times. 200 * Try a few times before giving up. 201 */ 202 for (i = 0; i < 5; i++) { 203 tmp |= HOST_AHCI_EN; 204 writel(tmp, mmio + HOST_CTL); 205 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 206 if (tmp & HOST_AHCI_EN) 207 return; 208 msleep(10); 209 } 210 211 WARN_ON(1); 212} 213 214static ssize_t ahci_show_host_caps(struct device *dev, 215 struct device_attribute *attr, char *buf) 216{ 217 struct Scsi_Host *shost = class_to_shost(dev); 218 struct ata_port *ap = ata_shost_to_port(shost); 219 struct ahci_host_priv *hpriv = ap->host->private_data; 220 221 return sprintf(buf, "%x\n", hpriv->cap); 222} 223 224static ssize_t ahci_show_host_cap2(struct device *dev, 225 struct device_attribute *attr, char *buf) 226{ 227 struct Scsi_Host *shost = class_to_shost(dev); 228 struct ata_port *ap = ata_shost_to_port(shost); 229 struct ahci_host_priv *hpriv = ap->host->private_data; 230 231 return sprintf(buf, "%x\n", hpriv->cap2); 232} 233 234static ssize_t ahci_show_host_version(struct device *dev, 235 struct device_attribute *attr, char *buf) 236{ 237 struct Scsi_Host *shost = class_to_shost(dev); 238 struct ata_port *ap = ata_shost_to_port(shost); 239 struct ahci_host_priv *hpriv = ap->host->private_data; 240 void __iomem *mmio = hpriv->mmio; 241 242 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); 243} 244 245static ssize_t ahci_show_port_cmd(struct device *dev, 246 struct device_attribute *attr, char *buf) 247{ 248 struct Scsi_Host *shost = class_to_shost(dev); 249 struct ata_port *ap = ata_shost_to_port(shost); 250 void __iomem *port_mmio = ahci_port_base(ap); 251 252 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 253} 254 255static ssize_t ahci_read_em_buffer(struct device *dev, 256 struct device_attribute *attr, char *buf) 257{ 258 struct Scsi_Host *shost = class_to_shost(dev); 259 struct ata_port *ap = ata_shost_to_port(shost); 260 struct ahci_host_priv *hpriv = ap->host->private_data; 261 void __iomem *mmio = hpriv->mmio; 262 void __iomem *em_mmio = mmio + hpriv->em_loc; 263 u32 em_ctl, msg; 264 unsigned long flags; 265 size_t count; 266 int i; 267 268 spin_lock_irqsave(ap->lock, flags); 269 270 em_ctl = readl(mmio + HOST_EM_CTL); 271 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 272 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 273 spin_unlock_irqrestore(ap->lock, flags); 274 return -EINVAL; 275 } 276 277 if (!(em_ctl & EM_CTL_MR)) { 278 spin_unlock_irqrestore(ap->lock, flags); 279 return -EAGAIN; 280 } 281 282 if (!(em_ctl & EM_CTL_SMB)) 283 em_mmio += hpriv->em_buf_sz; 284 285 count = hpriv->em_buf_sz; 286 287 /* the count should not be larger than PAGE_SIZE */ 288 if (count > PAGE_SIZE) { 289 if (printk_ratelimit()) 290 ata_port_printk(ap, KERN_WARNING, 291 "EM read buffer size too large: " 292 "buffer size %u, page size %lu\n", 293 hpriv->em_buf_sz, PAGE_SIZE); 294 count = PAGE_SIZE; 295 } 296 297 for (i = 0; i < count; i += 4) { 298 msg = readl(em_mmio + i); 299 buf[i] = msg & 0xff; 300 buf[i + 1] = (msg >> 8) & 0xff; 301 buf[i + 2] = (msg >> 16) & 0xff; 302 buf[i + 3] = (msg >> 24) & 0xff; 303 } 304 305 spin_unlock_irqrestore(ap->lock, flags); 306 307 return i; 308} 309 310static ssize_t ahci_store_em_buffer(struct device *dev, 311 struct device_attribute *attr, 312 const char *buf, size_t size) 313{ 314 struct Scsi_Host *shost = class_to_shost(dev); 315 struct ata_port *ap = ata_shost_to_port(shost); 316 struct ahci_host_priv *hpriv = ap->host->private_data; 317 void __iomem *mmio = hpriv->mmio; 318 void __iomem *em_mmio = mmio + hpriv->em_loc; 319 const unsigned char *msg_buf = buf; 320 u32 em_ctl, msg; 321 unsigned long flags; 322 int i; 323 324 /* check size validity */ 325 if (!(ap->flags & ATA_FLAG_EM) || 326 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 327 size % 4 || size > hpriv->em_buf_sz) 328 return -EINVAL; 329 330 spin_lock_irqsave(ap->lock, flags); 331 332 em_ctl = readl(mmio + HOST_EM_CTL); 333 if (em_ctl & EM_CTL_TM) { 334 spin_unlock_irqrestore(ap->lock, flags); 335 return -EBUSY; 336 } 337 338 for (i = 0; i < size; i += 4) { 339 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 340 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 341 writel(msg, em_mmio + i); 342 } 343 344 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 345 346 spin_unlock_irqrestore(ap->lock, flags); 347 348 return size; 349} 350 351/** 352 * ahci_save_initial_config - Save and fixup initial config values 353 * @dev: target AHCI device 354 * @hpriv: host private area to store config values 355 * @force_port_map: force port map to a specified value 356 * @mask_port_map: mask out particular bits from port map 357 * 358 * Some registers containing configuration info might be setup by 359 * BIOS and might be cleared on reset. This function saves the 360 * initial values of those registers into @hpriv such that they 361 * can be restored after controller reset. 362 * 363 * If inconsistent, config values are fixed up by this function. 364 * 365 * LOCKING: 366 * None. 367 */ 368void ahci_save_initial_config(struct device *dev, 369 struct ahci_host_priv *hpriv, 370 unsigned int force_port_map, 371 unsigned int mask_port_map) 372{ 373 void __iomem *mmio = hpriv->mmio; 374 u32 cap, cap2, vers, port_map; 375 int i; 376 377 /* make sure AHCI mode is enabled before accessing CAP */ 378 ahci_enable_ahci(mmio); 379 380 /* Values prefixed with saved_ are written back to host after 381 * reset. Values without are used for driver operation. 382 */ 383 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 384 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 385 386 /* CAP2 register is only defined for AHCI 1.2 and later */ 387 vers = readl(mmio + HOST_VERSION); 388 if ((vers >> 16) > 1 || 389 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 390 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 391 else 392 hpriv->saved_cap2 = cap2 = 0; 393 394 /* some chips have errata preventing 64bit use */ 395 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 396 dev_printk(KERN_INFO, dev, 397 "controller can't do 64bit DMA, forcing 32bit\n"); 398 cap &= ~HOST_CAP_64; 399 } 400 401 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 402 dev_printk(KERN_INFO, dev, 403 "controller can't do NCQ, turning off CAP_NCQ\n"); 404 cap &= ~HOST_CAP_NCQ; 405 } 406 407 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 408 dev_printk(KERN_INFO, dev, 409 "controller can do NCQ, turning on CAP_NCQ\n"); 410 cap |= HOST_CAP_NCQ; 411 } 412 413 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 414 dev_printk(KERN_INFO, dev, 415 "controller can't do PMP, turning off CAP_PMP\n"); 416 cap &= ~HOST_CAP_PMP; 417 } 418 419 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 420 dev_printk(KERN_INFO, dev, 421 "controller can't do SNTF, turning off CAP_SNTF\n"); 422 cap &= ~HOST_CAP_SNTF; 423 } 424 425 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 426 dev_printk(KERN_INFO, dev, 427 "controller can do FBS, turning on CAP_FBS\n"); 428 cap |= HOST_CAP_FBS; 429 } 430 431 if (force_port_map && port_map != force_port_map) { 432 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n", 433 port_map, force_port_map); 434 port_map = force_port_map; 435 } 436 437 if (mask_port_map) { 438 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n", 439 port_map, 440 port_map & mask_port_map); 441 port_map &= mask_port_map; 442 } 443 444 /* cross check port_map and cap.n_ports */ 445 if (port_map) { 446 int map_ports = 0; 447 448 for (i = 0; i < AHCI_MAX_PORTS; i++) 449 if (port_map & (1 << i)) 450 map_ports++; 451 452 /* If PI has more ports than n_ports, whine, clear 453 * port_map and let it be generated from n_ports. 454 */ 455 if (map_ports > ahci_nr_ports(cap)) { 456 dev_printk(KERN_WARNING, dev, 457 "implemented port map (0x%x) contains more " 458 "ports than nr_ports (%u), using nr_ports\n", 459 port_map, ahci_nr_ports(cap)); 460 port_map = 0; 461 } 462 } 463 464 /* fabricate port_map from cap.nr_ports */ 465 if (!port_map) { 466 port_map = (1 << ahci_nr_ports(cap)) - 1; 467 dev_printk(KERN_WARNING, dev, 468 "forcing PORTS_IMPL to 0x%x\n", port_map); 469 470 /* write the fixed up value to the PI register */ 471 hpriv->saved_port_map = port_map; 472 } 473 474 /* record values to use during operation */ 475 hpriv->cap = cap; 476 hpriv->cap2 = cap2; 477 hpriv->port_map = port_map; 478} 479EXPORT_SYMBOL_GPL(ahci_save_initial_config); 480 481/** 482 * ahci_restore_initial_config - Restore initial config 483 * @host: target ATA host 484 * 485 * Restore initial config stored by ahci_save_initial_config(). 486 * 487 * LOCKING: 488 * None. 489 */ 490static void ahci_restore_initial_config(struct ata_host *host) 491{ 492 struct ahci_host_priv *hpriv = host->private_data; 493 void __iomem *mmio = hpriv->mmio; 494 495 writel(hpriv->saved_cap, mmio + HOST_CAP); 496 if (hpriv->saved_cap2) 497 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 498 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 499 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 500} 501 502static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 503{ 504 static const int offset[] = { 505 [SCR_STATUS] = PORT_SCR_STAT, 506 [SCR_CONTROL] = PORT_SCR_CTL, 507 [SCR_ERROR] = PORT_SCR_ERR, 508 [SCR_ACTIVE] = PORT_SCR_ACT, 509 [SCR_NOTIFICATION] = PORT_SCR_NTF, 510 }; 511 struct ahci_host_priv *hpriv = ap->host->private_data; 512 513 if (sc_reg < ARRAY_SIZE(offset) && 514 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 515 return offset[sc_reg]; 516 return 0; 517} 518 519static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 520{ 521 void __iomem *port_mmio = ahci_port_base(link->ap); 522 int offset = ahci_scr_offset(link->ap, sc_reg); 523 524 if (offset) { 525 *val = readl(port_mmio + offset); 526 return 0; 527 } 528 return -EINVAL; 529} 530 531static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 532{ 533 void __iomem *port_mmio = ahci_port_base(link->ap); 534 int offset = ahci_scr_offset(link->ap, sc_reg); 535 536 if (offset) { 537 writel(val, port_mmio + offset); 538 return 0; 539 } 540 return -EINVAL; 541} 542 543void ahci_start_engine(struct ata_port *ap) 544{ 545 void __iomem *port_mmio = ahci_port_base(ap); 546 u32 tmp; 547 548 /* start DMA */ 549 tmp = readl(port_mmio + PORT_CMD); 550 tmp |= PORT_CMD_START; 551 writel(tmp, port_mmio + PORT_CMD); 552 readl(port_mmio + PORT_CMD); /* flush */ 553} 554EXPORT_SYMBOL_GPL(ahci_start_engine); 555 556int ahci_stop_engine(struct ata_port *ap) 557{ 558 void __iomem *port_mmio = ahci_port_base(ap); 559 u32 tmp; 560 561 tmp = readl(port_mmio + PORT_CMD); 562 563 /* check if the HBA is idle */ 564 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 565 return 0; 566 567 /* setting HBA to idle */ 568 tmp &= ~PORT_CMD_START; 569 writel(tmp, port_mmio + PORT_CMD); 570 571 /* wait for engine to stop. This could be as long as 500 msec */ 572 tmp = ata_wait_register(port_mmio + PORT_CMD, 573 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 574 if (tmp & PORT_CMD_LIST_ON) 575 return -EIO; 576 577 return 0; 578} 579EXPORT_SYMBOL_GPL(ahci_stop_engine); 580 581static void ahci_start_fis_rx(struct ata_port *ap) 582{ 583 void __iomem *port_mmio = ahci_port_base(ap); 584 struct ahci_host_priv *hpriv = ap->host->private_data; 585 struct ahci_port_priv *pp = ap->private_data; 586 u32 tmp; 587 588 /* set FIS registers */ 589 if (hpriv->cap & HOST_CAP_64) 590 writel((pp->cmd_slot_dma >> 16) >> 16, 591 port_mmio + PORT_LST_ADDR_HI); 592 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 593 594 if (hpriv->cap & HOST_CAP_64) 595 writel((pp->rx_fis_dma >> 16) >> 16, 596 port_mmio + PORT_FIS_ADDR_HI); 597 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 598 599 /* enable FIS reception */ 600 tmp = readl(port_mmio + PORT_CMD); 601 tmp |= PORT_CMD_FIS_RX; 602 writel(tmp, port_mmio + PORT_CMD); 603 604 /* flush */ 605 readl(port_mmio + PORT_CMD); 606} 607 608static int ahci_stop_fis_rx(struct ata_port *ap) 609{ 610 void __iomem *port_mmio = ahci_port_base(ap); 611 u32 tmp; 612 613 /* disable FIS reception */ 614 tmp = readl(port_mmio + PORT_CMD); 615 tmp &= ~PORT_CMD_FIS_RX; 616 writel(tmp, port_mmio + PORT_CMD); 617 618 /* wait for completion, spec says 500ms, give it 1000 */ 619 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 620 PORT_CMD_FIS_ON, 10, 1000); 621 if (tmp & PORT_CMD_FIS_ON) 622 return -EBUSY; 623 624 return 0; 625} 626 627static void ahci_power_up(struct ata_port *ap) 628{ 629 struct ahci_host_priv *hpriv = ap->host->private_data; 630 void __iomem *port_mmio = ahci_port_base(ap); 631 u32 cmd; 632 633 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 634 635 /* spin up device */ 636 if (hpriv->cap & HOST_CAP_SSS) { 637 cmd |= PORT_CMD_SPIN_UP; 638 writel(cmd, port_mmio + PORT_CMD); 639 } 640 641 /* wake up link */ 642 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 643} 644 645static void ahci_disable_alpm(struct ata_port *ap) 646{ 647 struct ahci_host_priv *hpriv = ap->host->private_data; 648 void __iomem *port_mmio = ahci_port_base(ap); 649 u32 cmd; 650 struct ahci_port_priv *pp = ap->private_data; 651 652 /* IPM bits should be disabled by libata-core */ 653 /* get the existing command bits */ 654 cmd = readl(port_mmio + PORT_CMD); 655 656 /* disable ALPM and ASP */ 657 cmd &= ~PORT_CMD_ASP; 658 cmd &= ~PORT_CMD_ALPE; 659 660 /* force the interface back to active */ 661 cmd |= PORT_CMD_ICC_ACTIVE; 662 663 /* write out new cmd value */ 664 writel(cmd, port_mmio + PORT_CMD); 665 cmd = readl(port_mmio + PORT_CMD); 666 667 /* wait 10ms to be sure we've come out of any low power state */ 668 msleep(10); 669 670 /* clear out any PhyRdy stuff from interrupt status */ 671 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); 672 673 /* go ahead and clean out PhyRdy Change from Serror too */ 674 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); 675 676 /* 677 * Clear flag to indicate that we should ignore all PhyRdy 678 * state changes 679 */ 680 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; 681 682 /* 683 * Enable interrupts on Phy Ready. 684 */ 685 pp->intr_mask |= PORT_IRQ_PHYRDY; 686 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 687 688 /* 689 * don't change the link pm policy - we can be called 690 * just to turn of link pm temporarily 691 */ 692} 693 694static int ahci_enable_alpm(struct ata_port *ap, 695 enum link_pm policy) 696{ 697 struct ahci_host_priv *hpriv = ap->host->private_data; 698 void __iomem *port_mmio = ahci_port_base(ap); 699 u32 cmd; 700 struct ahci_port_priv *pp = ap->private_data; 701 u32 asp; 702 703 /* Make sure the host is capable of link power management */ 704 if (!(hpriv->cap & HOST_CAP_ALPM)) 705 return -EINVAL; 706 707 switch (policy) { 708 case MAX_PERFORMANCE: 709 case NOT_AVAILABLE: 710 /* 711 * if we came here with NOT_AVAILABLE, 712 * it just means this is the first time we 713 * have tried to enable - default to max performance, 714 * and let the user go to lower power modes on request. 715 */ 716 ahci_disable_alpm(ap); 717 return 0; 718 case MIN_POWER: 719 /* configure HBA to enter SLUMBER */ 720 asp = PORT_CMD_ASP; 721 break; 722 case MEDIUM_POWER: 723 /* configure HBA to enter PARTIAL */ 724 asp = 0; 725 break; 726 default: 727 return -EINVAL; 728 } 729 730 /* 731 * Disable interrupts on Phy Ready. This keeps us from 732 * getting woken up due to spurious phy ready interrupts 733 * TBD - Hot plug should be done via polling now, is 734 * that even supported? 735 */ 736 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 737 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 738 739 /* 740 * Set a flag to indicate that we should ignore all PhyRdy 741 * state changes since these can happen now whenever we 742 * change link state 743 */ 744 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; 745 746 /* get the existing command bits */ 747 cmd = readl(port_mmio + PORT_CMD); 748 749 /* 750 * Set ASP based on Policy 751 */ 752 cmd |= asp; 753 754 /* 755 * Setting this bit will instruct the HBA to aggressively 756 * enter a lower power link state when it's appropriate and 757 * based on the value set above for ASP 758 */ 759 cmd |= PORT_CMD_ALPE; 760 761 /* write out new cmd value */ 762 writel(cmd, port_mmio + PORT_CMD); 763 cmd = readl(port_mmio + PORT_CMD); 764 765 /* IPM bits should be set by libata-core */ 766 return 0; 767} 768 769#ifdef CONFIG_PM 770static void ahci_power_down(struct ata_port *ap) 771{ 772 struct ahci_host_priv *hpriv = ap->host->private_data; 773 void __iomem *port_mmio = ahci_port_base(ap); 774 u32 cmd, scontrol; 775 776 if (!(hpriv->cap & HOST_CAP_SSS)) 777 return; 778 779 /* put device into listen mode, first set PxSCTL.DET to 0 */ 780 scontrol = readl(port_mmio + PORT_SCR_CTL); 781 scontrol &= ~0xf; 782 writel(scontrol, port_mmio + PORT_SCR_CTL); 783 784 /* then set PxCMD.SUD to 0 */ 785 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 786 cmd &= ~PORT_CMD_SPIN_UP; 787 writel(cmd, port_mmio + PORT_CMD); 788} 789#endif 790 791static void ahci_start_port(struct ata_port *ap) 792{ 793 struct ahci_port_priv *pp = ap->private_data; 794 struct ata_link *link; 795 struct ahci_em_priv *emp; 796 ssize_t rc; 797 int i; 798 799 /* enable FIS reception */ 800 ahci_start_fis_rx(ap); 801 802 /* enable DMA */ 803 ahci_start_engine(ap); 804 805 /* turn on LEDs */ 806 if (ap->flags & ATA_FLAG_EM) { 807 ata_for_each_link(link, ap, EDGE) { 808 emp = &pp->em_priv[link->pmp]; 809 810 /* EM Transmit bit maybe busy during init */ 811 for (i = 0; i < EM_MAX_RETRY; i++) { 812 rc = ahci_transmit_led_message(ap, 813 emp->led_state, 814 4); 815 if (rc == -EBUSY) 816 msleep(1); 817 else 818 break; 819 } 820 } 821 } 822 823 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 824 ata_for_each_link(link, ap, EDGE) 825 ahci_init_sw_activity(link); 826 827} 828 829static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 830{ 831 int rc; 832 833 /* disable DMA */ 834 rc = ahci_stop_engine(ap); 835 if (rc) { 836 *emsg = "failed to stop engine"; 837 return rc; 838 } 839 840 /* disable FIS reception */ 841 rc = ahci_stop_fis_rx(ap); 842 if (rc) { 843 *emsg = "failed stop FIS RX"; 844 return rc; 845 } 846 847 return 0; 848} 849 850int ahci_reset_controller(struct ata_host *host) 851{ 852 struct ahci_host_priv *hpriv = host->private_data; 853 void __iomem *mmio = hpriv->mmio; 854 u32 tmp; 855 856 /* we must be in AHCI mode, before using anything 857 * AHCI-specific, such as HOST_RESET. 858 */ 859 ahci_enable_ahci(mmio); 860 861 /* global controller reset */ 862 if (!ahci_skip_host_reset) { 863 tmp = readl(mmio + HOST_CTL); 864 if ((tmp & HOST_RESET) == 0) { 865 writel(tmp | HOST_RESET, mmio + HOST_CTL); 866 readl(mmio + HOST_CTL); /* flush */ 867 } 868 869 /* 870 * to perform host reset, OS should set HOST_RESET 871 * and poll until this bit is read to be "0". 872 * reset must complete within 1 second, or 873 * the hardware should be considered fried. 874 */ 875 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET, 876 HOST_RESET, 10, 1000); 877 878 if (tmp & HOST_RESET) { 879 dev_printk(KERN_ERR, host->dev, 880 "controller reset failed (0x%x)\n", tmp); 881 return -EIO; 882 } 883 884 /* turn on AHCI mode */ 885 ahci_enable_ahci(mmio); 886 887 /* Some registers might be cleared on reset. Restore 888 * initial values. 889 */ 890 ahci_restore_initial_config(host); 891 } else 892 dev_printk(KERN_INFO, host->dev, 893 "skipping global host reset\n"); 894 895 return 0; 896} 897EXPORT_SYMBOL_GPL(ahci_reset_controller); 898 899static void ahci_sw_activity(struct ata_link *link) 900{ 901 struct ata_port *ap = link->ap; 902 struct ahci_port_priv *pp = ap->private_data; 903 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 904 905 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 906 return; 907 908 emp->activity++; 909 if (!timer_pending(&emp->timer)) 910 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 911} 912 913static void ahci_sw_activity_blink(unsigned long arg) 914{ 915 struct ata_link *link = (struct ata_link *)arg; 916 struct ata_port *ap = link->ap; 917 struct ahci_port_priv *pp = ap->private_data; 918 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 919 unsigned long led_message = emp->led_state; 920 u32 activity_led_state; 921 unsigned long flags; 922 923 led_message &= EM_MSG_LED_VALUE; 924 led_message |= ap->port_no | (link->pmp << 8); 925 926 /* check to see if we've had activity. If so, 927 * toggle state of LED and reset timer. If not, 928 * turn LED to desired idle state. 929 */ 930 spin_lock_irqsave(ap->lock, flags); 931 if (emp->saved_activity != emp->activity) { 932 emp->saved_activity = emp->activity; 933 /* get the current LED state */ 934 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 935 936 if (activity_led_state) 937 activity_led_state = 0; 938 else 939 activity_led_state = 1; 940 941 /* clear old state */ 942 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 943 944 /* toggle state */ 945 led_message |= (activity_led_state << 16); 946 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 947 } else { 948 /* switch to idle */ 949 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 950 if (emp->blink_policy == BLINK_OFF) 951 led_message |= (1 << 16); 952 } 953 spin_unlock_irqrestore(ap->lock, flags); 954 ahci_transmit_led_message(ap, led_message, 4); 955} 956 957static void ahci_init_sw_activity(struct ata_link *link) 958{ 959 struct ata_port *ap = link->ap; 960 struct ahci_port_priv *pp = ap->private_data; 961 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 962 963 /* init activity stats, setup timer */ 964 emp->saved_activity = emp->activity = 0; 965 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 966 967 /* check our blink policy and set flag for link if it's enabled */ 968 if (emp->blink_policy) 969 link->flags |= ATA_LFLAG_SW_ACTIVITY; 970} 971 972int ahci_reset_em(struct ata_host *host) 973{ 974 struct ahci_host_priv *hpriv = host->private_data; 975 void __iomem *mmio = hpriv->mmio; 976 u32 em_ctl; 977 978 em_ctl = readl(mmio + HOST_EM_CTL); 979 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 980 return -EINVAL; 981 982 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 983 return 0; 984} 985EXPORT_SYMBOL_GPL(ahci_reset_em); 986 987static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 988 ssize_t size) 989{ 990 struct ahci_host_priv *hpriv = ap->host->private_data; 991 struct ahci_port_priv *pp = ap->private_data; 992 void __iomem *mmio = hpriv->mmio; 993 u32 em_ctl; 994 u32 message[] = {0, 0}; 995 unsigned long flags; 996 int pmp; 997 struct ahci_em_priv *emp; 998 999 /* get the slot number from the message */ 1000 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1001 if (pmp < EM_MAX_SLOTS) 1002 emp = &pp->em_priv[pmp]; 1003 else 1004 return -EINVAL; 1005 1006 spin_lock_irqsave(ap->lock, flags); 1007 1008 /* 1009 * if we are still busy transmitting a previous message, 1010 * do not allow 1011 */ 1012 em_ctl = readl(mmio + HOST_EM_CTL); 1013 if (em_ctl & EM_CTL_TM) { 1014 spin_unlock_irqrestore(ap->lock, flags); 1015 return -EBUSY; 1016 } 1017 1018 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1019 /* 1020 * create message header - this is all zero except for 1021 * the message size, which is 4 bytes. 1022 */ 1023 message[0] |= (4 << 8); 1024 1025 /* ignore 0:4 of byte zero, fill in port info yourself */ 1026 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1027 1028 /* write message to EM_LOC */ 1029 writel(message[0], mmio + hpriv->em_loc); 1030 writel(message[1], mmio + hpriv->em_loc+4); 1031 1032 /* 1033 * tell hardware to transmit the message 1034 */ 1035 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1036 } 1037 1038 /* save off new led state for port/slot */ 1039 emp->led_state = state; 1040 1041 spin_unlock_irqrestore(ap->lock, flags); 1042 return size; 1043} 1044 1045static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1046{ 1047 struct ahci_port_priv *pp = ap->private_data; 1048 struct ata_link *link; 1049 struct ahci_em_priv *emp; 1050 int rc = 0; 1051 1052 ata_for_each_link(link, ap, EDGE) { 1053 emp = &pp->em_priv[link->pmp]; 1054 rc += sprintf(buf, "%lx\n", emp->led_state); 1055 } 1056 return rc; 1057} 1058 1059static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1060 size_t size) 1061{ 1062 int state; 1063 int pmp; 1064 struct ahci_port_priv *pp = ap->private_data; 1065 struct ahci_em_priv *emp; 1066 1067 state = simple_strtoul(buf, NULL, 0); 1068 1069 /* get the slot number from the message */ 1070 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1071 if (pmp < EM_MAX_SLOTS) 1072 emp = &pp->em_priv[pmp]; 1073 else 1074 return -EINVAL; 1075 1076 /* mask off the activity bits if we are in sw_activity 1077 * mode, user should turn off sw_activity before setting 1078 * activity led through em_message 1079 */ 1080 if (emp->blink_policy) 1081 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1082 1083 return ahci_transmit_led_message(ap, state, size); 1084} 1085 1086static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1087{ 1088 struct ata_link *link = dev->link; 1089 struct ata_port *ap = link->ap; 1090 struct ahci_port_priv *pp = ap->private_data; 1091 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1092 u32 port_led_state = emp->led_state; 1093 1094 /* save the desired Activity LED behavior */ 1095 if (val == OFF) { 1096 /* clear LFLAG */ 1097 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1098 1099 /* set the LED to OFF */ 1100 port_led_state &= EM_MSG_LED_VALUE_OFF; 1101 port_led_state |= (ap->port_no | (link->pmp << 8)); 1102 ahci_transmit_led_message(ap, port_led_state, 4); 1103 } else { 1104 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1105 if (val == BLINK_OFF) { 1106 /* set LED to ON for idle */ 1107 port_led_state &= EM_MSG_LED_VALUE_OFF; 1108 port_led_state |= (ap->port_no | (link->pmp << 8)); 1109 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1110 ahci_transmit_led_message(ap, port_led_state, 4); 1111 } 1112 } 1113 emp->blink_policy = val; 1114 return 0; 1115} 1116 1117static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1118{ 1119 struct ata_link *link = dev->link; 1120 struct ata_port *ap = link->ap; 1121 struct ahci_port_priv *pp = ap->private_data; 1122 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1123 1124 /* display the saved value of activity behavior for this 1125 * disk. 1126 */ 1127 return sprintf(buf, "%d\n", emp->blink_policy); 1128} 1129 1130static void ahci_port_init(struct device *dev, struct ata_port *ap, 1131 int port_no, void __iomem *mmio, 1132 void __iomem *port_mmio) 1133{ 1134 const char *emsg = NULL; 1135 int rc; 1136 u32 tmp; 1137 1138 /* make sure port is not active */ 1139 rc = ahci_deinit_port(ap, &emsg); 1140 if (rc) 1141 dev_warn(dev, "%s (%d)\n", emsg, rc); 1142 1143 /* clear SError */ 1144 tmp = readl(port_mmio + PORT_SCR_ERR); 1145 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1146 writel(tmp, port_mmio + PORT_SCR_ERR); 1147 1148 /* clear port IRQ */ 1149 tmp = readl(port_mmio + PORT_IRQ_STAT); 1150 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1151 if (tmp) 1152 writel(tmp, port_mmio + PORT_IRQ_STAT); 1153 1154 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1155} 1156 1157void ahci_init_controller(struct ata_host *host) 1158{ 1159 struct ahci_host_priv *hpriv = host->private_data; 1160 void __iomem *mmio = hpriv->mmio; 1161 int i; 1162 void __iomem *port_mmio; 1163 u32 tmp; 1164 1165 for (i = 0; i < host->n_ports; i++) { 1166 struct ata_port *ap = host->ports[i]; 1167 1168 port_mmio = ahci_port_base(ap); 1169 if (ata_port_is_dummy(ap)) 1170 continue; 1171 1172 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1173 } 1174 1175 tmp = readl(mmio + HOST_CTL); 1176 VPRINTK("HOST_CTL 0x%x\n", tmp); 1177 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1178 tmp = readl(mmio + HOST_CTL); 1179 VPRINTK("HOST_CTL 0x%x\n", tmp); 1180} 1181EXPORT_SYMBOL_GPL(ahci_init_controller); 1182 1183static void ahci_dev_config(struct ata_device *dev) 1184{ 1185 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1186 1187 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1188 dev->max_sectors = 255; 1189 ata_dev_printk(dev, KERN_INFO, 1190 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1191 } 1192} 1193 1194static unsigned int ahci_dev_classify(struct ata_port *ap) 1195{ 1196 void __iomem *port_mmio = ahci_port_base(ap); 1197 struct ata_taskfile tf; 1198 u32 tmp; 1199 1200 tmp = readl(port_mmio + PORT_SIG); 1201 tf.lbah = (tmp >> 24) & 0xff; 1202 tf.lbam = (tmp >> 16) & 0xff; 1203 tf.lbal = (tmp >> 8) & 0xff; 1204 tf.nsect = (tmp) & 0xff; 1205 1206 return ata_dev_classify(&tf); 1207} 1208 1209static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1210 u32 opts) 1211{ 1212 dma_addr_t cmd_tbl_dma; 1213 1214 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1215 1216 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1217 pp->cmd_slot[tag].status = 0; 1218 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1219 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1220} 1221 1222int ahci_kick_engine(struct ata_port *ap) 1223{ 1224 void __iomem *port_mmio = ahci_port_base(ap); 1225 struct ahci_host_priv *hpriv = ap->host->private_data; 1226 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1227 u32 tmp; 1228 int busy, rc; 1229 1230 /* stop engine */ 1231 rc = ahci_stop_engine(ap); 1232 if (rc) 1233 goto out_restart; 1234 1235 /* need to do CLO? 1236 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1237 */ 1238 busy = status & (ATA_BUSY | ATA_DRQ); 1239 if (!busy && !sata_pmp_attached(ap)) { 1240 rc = 0; 1241 goto out_restart; 1242 } 1243 1244 if (!(hpriv->cap & HOST_CAP_CLO)) { 1245 rc = -EOPNOTSUPP; 1246 goto out_restart; 1247 } 1248 1249 /* perform CLO */ 1250 tmp = readl(port_mmio + PORT_CMD); 1251 tmp |= PORT_CMD_CLO; 1252 writel(tmp, port_mmio + PORT_CMD); 1253 1254 rc = 0; 1255 tmp = ata_wait_register(port_mmio + PORT_CMD, 1256 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1257 if (tmp & PORT_CMD_CLO) 1258 rc = -EIO; 1259 1260 /* restart engine */ 1261 out_restart: 1262 ahci_start_engine(ap); 1263 return rc; 1264} 1265EXPORT_SYMBOL_GPL(ahci_kick_engine); 1266 1267static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1268 struct ata_taskfile *tf, int is_cmd, u16 flags, 1269 unsigned long timeout_msec) 1270{ 1271 const u32 cmd_fis_len = 5; /* five dwords */ 1272 struct ahci_port_priv *pp = ap->private_data; 1273 void __iomem *port_mmio = ahci_port_base(ap); 1274 u8 *fis = pp->cmd_tbl; 1275 u32 tmp; 1276 1277 /* prep the command */ 1278 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1279 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1280 1281 /* issue & wait */ 1282 writel(1, port_mmio + PORT_CMD_ISSUE); 1283 1284 if (timeout_msec) { 1285 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1286 1, timeout_msec); 1287 if (tmp & 0x1) { 1288 ahci_kick_engine(ap); 1289 return -EBUSY; 1290 } 1291 } else 1292 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1293 1294 return 0; 1295} 1296 1297int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1298 int pmp, unsigned long deadline, 1299 int (*check_ready)(struct ata_link *link)) 1300{ 1301 struct ata_port *ap = link->ap; 1302 struct ahci_host_priv *hpriv = ap->host->private_data; 1303 const char *reason = NULL; 1304 unsigned long now, msecs; 1305 struct ata_taskfile tf; 1306 int rc; 1307 1308 DPRINTK("ENTER\n"); 1309 1310 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1311 rc = ahci_kick_engine(ap); 1312 if (rc && rc != -EOPNOTSUPP) 1313 ata_link_printk(link, KERN_WARNING, 1314 "failed to reset engine (errno=%d)\n", rc); 1315 1316 ata_tf_init(link->device, &tf); 1317 1318 /* issue the first D2H Register FIS */ 1319 msecs = 0; 1320 now = jiffies; 1321 if (time_after(deadline, now)) 1322 msecs = jiffies_to_msecs(deadline - now); 1323 1324 tf.ctl |= ATA_SRST; 1325 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1326 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1327 rc = -EIO; 1328 reason = "1st FIS failed"; 1329 goto fail; 1330 } 1331 1332 /* spec says at least 5us, but be generous and sleep for 1ms */ 1333 msleep(1); 1334 1335 /* issue the second D2H Register FIS */ 1336 tf.ctl &= ~ATA_SRST; 1337 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1338 1339 /* wait for link to become ready */ 1340 rc = ata_wait_after_reset(link, deadline, check_ready); 1341 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1342 ata_link_printk(link, KERN_INFO, 1343 "device not ready, treating as offline\n"); 1344 *class = ATA_DEV_NONE; 1345 } else if (rc) { 1346 /* link occupied, -ENODEV too is an error */ 1347 reason = "device not ready"; 1348 goto fail; 1349 } else 1350 *class = ahci_dev_classify(ap); 1351 1352 DPRINTK("EXIT, class=%u\n", *class); 1353 return 0; 1354 1355 fail: 1356 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 1357 return rc; 1358} 1359 1360int ahci_check_ready(struct ata_link *link) 1361{ 1362 void __iomem *port_mmio = ahci_port_base(link->ap); 1363 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1364 1365 return ata_check_ready(status); 1366} 1367EXPORT_SYMBOL_GPL(ahci_check_ready); 1368 1369static int ahci_softreset(struct ata_link *link, unsigned int *class, 1370 unsigned long deadline) 1371{ 1372 int pmp = sata_srst_pmp(link); 1373 1374 DPRINTK("ENTER\n"); 1375 1376 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1377} 1378EXPORT_SYMBOL_GPL(ahci_do_softreset); 1379 1380static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1381 unsigned long deadline) 1382{ 1383 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1384 struct ata_port *ap = link->ap; 1385 struct ahci_port_priv *pp = ap->private_data; 1386 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1387 struct ata_taskfile tf; 1388 bool online; 1389 int rc; 1390 1391 DPRINTK("ENTER\n"); 1392 1393 ahci_stop_engine(ap); 1394 1395 /* clear D2H reception area to properly wait for D2H FIS */ 1396 ata_tf_init(link->device, &tf); 1397 tf.command = 0x80; 1398 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1399 1400 rc = sata_link_hardreset(link, timing, deadline, &online, 1401 ahci_check_ready); 1402 1403 ahci_start_engine(ap); 1404 1405 if (online) 1406 *class = ahci_dev_classify(ap); 1407 1408 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1409 return rc; 1410} 1411 1412static void ahci_postreset(struct ata_link *link, unsigned int *class) 1413{ 1414 struct ata_port *ap = link->ap; 1415 void __iomem *port_mmio = ahci_port_base(ap); 1416 u32 new_tmp, tmp; 1417 1418 ata_std_postreset(link, class); 1419 1420 /* Make sure port's ATAPI bit is set appropriately */ 1421 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1422 if (*class == ATA_DEV_ATAPI) 1423 new_tmp |= PORT_CMD_ATAPI; 1424 else 1425 new_tmp &= ~PORT_CMD_ATAPI; 1426 if (new_tmp != tmp) { 1427 writel(new_tmp, port_mmio + PORT_CMD); 1428 readl(port_mmio + PORT_CMD); /* flush */ 1429 } 1430} 1431 1432static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1433{ 1434 struct scatterlist *sg; 1435 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1436 unsigned int si; 1437 1438 VPRINTK("ENTER\n"); 1439 1440 /* 1441 * Next, the S/G list. 1442 */ 1443 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1444 dma_addr_t addr = sg_dma_address(sg); 1445 u32 sg_len = sg_dma_len(sg); 1446 1447 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1448 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1449 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1450 } 1451 1452 return si; 1453} 1454 1455static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1456{ 1457 struct ata_port *ap = qc->ap; 1458 struct ahci_port_priv *pp = ap->private_data; 1459 1460 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1461 return ata_std_qc_defer(qc); 1462 else 1463 return sata_pmp_qc_defer_cmd_switch(qc); 1464} 1465 1466static void ahci_qc_prep(struct ata_queued_cmd *qc) 1467{ 1468 struct ata_port *ap = qc->ap; 1469 struct ahci_port_priv *pp = ap->private_data; 1470 int is_atapi = ata_is_atapi(qc->tf.protocol); 1471 void *cmd_tbl; 1472 u32 opts; 1473 const u32 cmd_fis_len = 5; /* five dwords */ 1474 unsigned int n_elem; 1475 1476 /* 1477 * Fill in command table information. First, the header, 1478 * a SATA Register - Host to Device command FIS. 1479 */ 1480 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1481 1482 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1483 if (is_atapi) { 1484 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1485 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1486 } 1487 1488 n_elem = 0; 1489 if (qc->flags & ATA_QCFLAG_DMAMAP) 1490 n_elem = ahci_fill_sg(qc, cmd_tbl); 1491 1492 /* 1493 * Fill in command slot information. 1494 */ 1495 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1496 if (qc->tf.flags & ATA_TFLAG_WRITE) 1497 opts |= AHCI_CMD_WRITE; 1498 if (is_atapi) 1499 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1500 1501 ahci_fill_cmd_slot(pp, qc->tag, opts); 1502} 1503 1504static void ahci_fbs_dec_intr(struct ata_port *ap) 1505{ 1506 struct ahci_port_priv *pp = ap->private_data; 1507 void __iomem *port_mmio = ahci_port_base(ap); 1508 u32 fbs = readl(port_mmio + PORT_FBS); 1509 int retries = 3; 1510 1511 DPRINTK("ENTER\n"); 1512 BUG_ON(!pp->fbs_enabled); 1513 1514 /* time to wait for DEC is not specified by AHCI spec, 1515 * add a retry loop for safety. 1516 */ 1517 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1518 fbs = readl(port_mmio + PORT_FBS); 1519 while ((fbs & PORT_FBS_DEC) && retries--) { 1520 udelay(1); 1521 fbs = readl(port_mmio + PORT_FBS); 1522 } 1523 1524 if (fbs & PORT_FBS_DEC) 1525 dev_printk(KERN_ERR, ap->host->dev, 1526 "failed to clear device error\n"); 1527} 1528 1529static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1530{ 1531 struct ahci_host_priv *hpriv = ap->host->private_data; 1532 struct ahci_port_priv *pp = ap->private_data; 1533 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1534 struct ata_link *link = NULL; 1535 struct ata_queued_cmd *active_qc; 1536 struct ata_eh_info *active_ehi; 1537 bool fbs_need_dec = false; 1538 u32 serror; 1539 1540 /* determine active link with error */ 1541 if (pp->fbs_enabled) { 1542 void __iomem *port_mmio = ahci_port_base(ap); 1543 u32 fbs = readl(port_mmio + PORT_FBS); 1544 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1545 1546 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) && 1547 ata_link_online(&ap->pmp_link[pmp])) { 1548 link = &ap->pmp_link[pmp]; 1549 fbs_need_dec = true; 1550 } 1551 1552 } else 1553 ata_for_each_link(link, ap, EDGE) 1554 if (ata_link_active(link)) 1555 break; 1556 1557 if (!link) 1558 link = &ap->link; 1559 1560 active_qc = ata_qc_from_tag(ap, link->active_tag); 1561 active_ehi = &link->eh_info; 1562 1563 /* record irq stat */ 1564 ata_ehi_clear_desc(host_ehi); 1565 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1566 1567 /* AHCI needs SError cleared; otherwise, it might lock up */ 1568 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1569 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1570 host_ehi->serror |= serror; 1571 1572 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1573 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1574 irq_stat &= ~PORT_IRQ_IF_ERR; 1575 1576 if (irq_stat & PORT_IRQ_TF_ERR) { 1577 /* If qc is active, charge it; otherwise, the active 1578 * link. There's no active qc on NCQ errors. It will 1579 * be determined by EH by reading log page 10h. 1580 */ 1581 if (active_qc) 1582 active_qc->err_mask |= AC_ERR_DEV; 1583 else 1584 active_ehi->err_mask |= AC_ERR_DEV; 1585 1586 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1587 host_ehi->serror &= ~SERR_INTERNAL; 1588 } 1589 1590 if (irq_stat & PORT_IRQ_UNK_FIS) { 1591 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 1592 1593 active_ehi->err_mask |= AC_ERR_HSM; 1594 active_ehi->action |= ATA_EH_RESET; 1595 ata_ehi_push_desc(active_ehi, 1596 "unknown FIS %08x %08x %08x %08x" , 1597 unk[0], unk[1], unk[2], unk[3]); 1598 } 1599 1600 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1601 active_ehi->err_mask |= AC_ERR_HSM; 1602 active_ehi->action |= ATA_EH_RESET; 1603 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1604 } 1605 1606 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1607 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1608 host_ehi->action |= ATA_EH_RESET; 1609 ata_ehi_push_desc(host_ehi, "host bus error"); 1610 } 1611 1612 if (irq_stat & PORT_IRQ_IF_ERR) { 1613 if (fbs_need_dec) 1614 active_ehi->err_mask |= AC_ERR_DEV; 1615 else { 1616 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1617 host_ehi->action |= ATA_EH_RESET; 1618 } 1619 1620 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1621 } 1622 1623 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1624 ata_ehi_hotplugged(host_ehi); 1625 ata_ehi_push_desc(host_ehi, "%s", 1626 irq_stat & PORT_IRQ_CONNECT ? 1627 "connection status changed" : "PHY RDY changed"); 1628 } 1629 1630 /* okay, let's hand over to EH */ 1631 1632 if (irq_stat & PORT_IRQ_FREEZE) 1633 ata_port_freeze(ap); 1634 else if (fbs_need_dec) { 1635 ata_link_abort(link); 1636 ahci_fbs_dec_intr(ap); 1637 } else 1638 ata_port_abort(ap); 1639} 1640 1641static void ahci_port_intr(struct ata_port *ap) 1642{ 1643 void __iomem *port_mmio = ahci_port_base(ap); 1644 struct ata_eh_info *ehi = &ap->link.eh_info; 1645 struct ahci_port_priv *pp = ap->private_data; 1646 struct ahci_host_priv *hpriv = ap->host->private_data; 1647 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1648 u32 status, qc_active = 0; 1649 int rc; 1650 1651 status = readl(port_mmio + PORT_IRQ_STAT); 1652 writel(status, port_mmio + PORT_IRQ_STAT); 1653 1654 /* ignore BAD_PMP while resetting */ 1655 if (unlikely(resetting)) 1656 status &= ~PORT_IRQ_BAD_PMP; 1657 1658 /* If we are getting PhyRdy, this is 1659 * just a power state change, we should 1660 * clear out this, plus the PhyRdy/Comm 1661 * Wake bits from Serror 1662 */ 1663 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && 1664 (status & PORT_IRQ_PHYRDY)) { 1665 status &= ~PORT_IRQ_PHYRDY; 1666 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); 1667 } 1668 1669 if (unlikely(status & PORT_IRQ_ERROR)) { 1670 ahci_error_intr(ap, status); 1671 return; 1672 } 1673 1674 if (status & PORT_IRQ_SDB_FIS) { 1675 /* If SNotification is available, leave notification 1676 * handling to sata_async_notification(). If not, 1677 * emulate it by snooping SDB FIS RX area. 1678 * 1679 * Snooping FIS RX area is probably cheaper than 1680 * poking SNotification but some constrollers which 1681 * implement SNotification, ICH9 for example, don't 1682 * store AN SDB FIS into receive area. 1683 */ 1684 if (hpriv->cap & HOST_CAP_SNTF) 1685 sata_async_notification(ap); 1686 else { 1687 if (pp->fbs_enabled) 1688 WARN_ON_ONCE(1); 1689 else { 1690 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1691 u32 f0 = le32_to_cpu(f[0]); 1692 if (f0 & (1 << 15)) 1693 sata_async_notification(ap); 1694 } 1695 } 1696 } 1697 1698 /* pp->active_link is not reliable once FBS is enabled, both 1699 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1700 * NCQ and non-NCQ commands may be in flight at the same time. 1701 */ 1702 if (pp->fbs_enabled) { 1703 if (ap->qc_active) { 1704 qc_active = readl(port_mmio + PORT_SCR_ACT); 1705 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1706 } 1707 } else { 1708 /* pp->active_link is valid iff any command is in flight */ 1709 if (ap->qc_active && pp->active_link->sactive) 1710 qc_active = readl(port_mmio + PORT_SCR_ACT); 1711 else 1712 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1713 } 1714 1715 1716 rc = ata_qc_complete_multiple(ap, qc_active); 1717 1718 /* while resetting, invalid completions are expected */ 1719 if (unlikely(rc < 0 && !resetting)) { 1720 ehi->err_mask |= AC_ERR_HSM; 1721 ehi->action |= ATA_EH_RESET; 1722 ata_port_freeze(ap); 1723 } 1724} 1725 1726irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1727{ 1728 struct ata_host *host = dev_instance; 1729 struct ahci_host_priv *hpriv; 1730 unsigned int i, handled = 0; 1731 void __iomem *mmio; 1732 u32 irq_stat, irq_masked; 1733 1734 VPRINTK("ENTER\n"); 1735 1736 hpriv = host->private_data; 1737 mmio = hpriv->mmio; 1738 1739 /* sigh. 0xffffffff is a valid return from h/w */ 1740 irq_stat = readl(mmio + HOST_IRQ_STAT); 1741 if (!irq_stat) 1742 return IRQ_NONE; 1743 1744 irq_masked = irq_stat & hpriv->port_map; 1745 1746 spin_lock(&host->lock); 1747 1748 for (i = 0; i < host->n_ports; i++) { 1749 struct ata_port *ap; 1750 1751 if (!(irq_masked & (1 << i))) 1752 continue; 1753 1754 ap = host->ports[i]; 1755 if (ap) { 1756 ahci_port_intr(ap); 1757 VPRINTK("port %u\n", i); 1758 } else { 1759 VPRINTK("port %u (no irq)\n", i); 1760 if (ata_ratelimit()) 1761 dev_printk(KERN_WARNING, host->dev, 1762 "interrupt on disabled port %u\n", i); 1763 } 1764 1765 handled = 1; 1766 } 1767 1768 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1769 * it should be cleared after all the port events are cleared; 1770 * otherwise, it will raise a spurious interrupt after each 1771 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1772 * information. 1773 * 1774 * Also, use the unmasked value to clear interrupt as spurious 1775 * pending event on a dummy port might cause screaming IRQ. 1776 */ 1777 writel(irq_stat, mmio + HOST_IRQ_STAT); 1778 1779 spin_unlock(&host->lock); 1780 1781 VPRINTK("EXIT\n"); 1782 1783 return IRQ_RETVAL(handled); 1784} 1785EXPORT_SYMBOL_GPL(ahci_interrupt); 1786 1787static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1788{ 1789 struct ata_port *ap = qc->ap; 1790 void __iomem *port_mmio = ahci_port_base(ap); 1791 struct ahci_port_priv *pp = ap->private_data; 1792 1793 /* Keep track of the currently active link. It will be used 1794 * in completion path to determine whether NCQ phase is in 1795 * progress. 1796 */ 1797 pp->active_link = qc->dev->link; 1798 1799 if (qc->tf.protocol == ATA_PROT_NCQ) 1800 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1801 1802 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1803 u32 fbs = readl(port_mmio + PORT_FBS); 1804 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1805 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1806 writel(fbs, port_mmio + PORT_FBS); 1807 pp->fbs_last_dev = qc->dev->link->pmp; 1808 } 1809 1810 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1811 1812 ahci_sw_activity(qc->dev->link); 1813 1814 return 0; 1815} 1816 1817static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1818{ 1819 struct ahci_port_priv *pp = qc->ap->private_data; 1820 u8 *rx_fis = pp->rx_fis; 1821 1822 if (pp->fbs_enabled) 1823 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 1824 1825 /* 1826 * After a successful execution of an ATA PIO data-in command, 1827 * the device doesn't send D2H Reg FIS to update the TF and 1828 * the host should take TF and E_Status from the preceding PIO 1829 * Setup FIS. 1830 */ 1831 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 1832 !(qc->flags & ATA_QCFLAG_FAILED)) { 1833 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 1834 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 1835 } else 1836 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 1837 1838 return true; 1839} 1840 1841static void ahci_freeze(struct ata_port *ap) 1842{ 1843 void __iomem *port_mmio = ahci_port_base(ap); 1844 1845 /* turn IRQ off */ 1846 writel(0, port_mmio + PORT_IRQ_MASK); 1847} 1848 1849static void ahci_thaw(struct ata_port *ap) 1850{ 1851 struct ahci_host_priv *hpriv = ap->host->private_data; 1852 void __iomem *mmio = hpriv->mmio; 1853 void __iomem *port_mmio = ahci_port_base(ap); 1854 u32 tmp; 1855 struct ahci_port_priv *pp = ap->private_data; 1856 1857 /* clear IRQ */ 1858 tmp = readl(port_mmio + PORT_IRQ_STAT); 1859 writel(tmp, port_mmio + PORT_IRQ_STAT); 1860 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 1861 1862 /* turn IRQ back on */ 1863 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1864} 1865 1866static void ahci_error_handler(struct ata_port *ap) 1867{ 1868 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1869 /* restart engine */ 1870 ahci_stop_engine(ap); 1871 ahci_start_engine(ap); 1872 } 1873 1874 sata_pmp_error_handler(ap); 1875 1876 if (!ata_dev_enabled(ap->link.device)) 1877 ahci_stop_engine(ap); 1878} 1879 1880static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1881{ 1882 struct ata_port *ap = qc->ap; 1883 1884 /* make DMA engine forget about the failed command */ 1885 if (qc->flags & ATA_QCFLAG_FAILED) 1886 ahci_kick_engine(ap); 1887} 1888 1889static void ahci_enable_fbs(struct ata_port *ap) 1890{ 1891 struct ahci_port_priv *pp = ap->private_data; 1892 void __iomem *port_mmio = ahci_port_base(ap); 1893 u32 fbs; 1894 int rc; 1895 1896 if (!pp->fbs_supported) 1897 return; 1898 1899 fbs = readl(port_mmio + PORT_FBS); 1900 if (fbs & PORT_FBS_EN) { 1901 pp->fbs_enabled = true; 1902 pp->fbs_last_dev = -1; /* initialization */ 1903 return; 1904 } 1905 1906 rc = ahci_stop_engine(ap); 1907 if (rc) 1908 return; 1909 1910 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 1911 fbs = readl(port_mmio + PORT_FBS); 1912 if (fbs & PORT_FBS_EN) { 1913 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n"); 1914 pp->fbs_enabled = true; 1915 pp->fbs_last_dev = -1; /* initialization */ 1916 } else 1917 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n"); 1918 1919 ahci_start_engine(ap); 1920} 1921 1922static void ahci_disable_fbs(struct ata_port *ap) 1923{ 1924 struct ahci_port_priv *pp = ap->private_data; 1925 void __iomem *port_mmio = ahci_port_base(ap); 1926 u32 fbs; 1927 int rc; 1928 1929 if (!pp->fbs_supported) 1930 return; 1931 1932 fbs = readl(port_mmio + PORT_FBS); 1933 if ((fbs & PORT_FBS_EN) == 0) { 1934 pp->fbs_enabled = false; 1935 return; 1936 } 1937 1938 rc = ahci_stop_engine(ap); 1939 if (rc) 1940 return; 1941 1942 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 1943 fbs = readl(port_mmio + PORT_FBS); 1944 if (fbs & PORT_FBS_EN) 1945 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n"); 1946 else { 1947 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n"); 1948 pp->fbs_enabled = false; 1949 } 1950 1951 ahci_start_engine(ap); 1952} 1953 1954static void ahci_pmp_attach(struct ata_port *ap) 1955{ 1956 void __iomem *port_mmio = ahci_port_base(ap); 1957 struct ahci_port_priv *pp = ap->private_data; 1958 u32 cmd; 1959 1960 cmd = readl(port_mmio + PORT_CMD); 1961 cmd |= PORT_CMD_PMP; 1962 writel(cmd, port_mmio + PORT_CMD); 1963 1964 ahci_enable_fbs(ap); 1965 1966 pp->intr_mask |= PORT_IRQ_BAD_PMP; 1967 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1968} 1969 1970static void ahci_pmp_detach(struct ata_port *ap) 1971{ 1972 void __iomem *port_mmio = ahci_port_base(ap); 1973 struct ahci_port_priv *pp = ap->private_data; 1974 u32 cmd; 1975 1976 ahci_disable_fbs(ap); 1977 1978 cmd = readl(port_mmio + PORT_CMD); 1979 cmd &= ~PORT_CMD_PMP; 1980 writel(cmd, port_mmio + PORT_CMD); 1981 1982 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 1983 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1984} 1985 1986static int ahci_port_resume(struct ata_port *ap) 1987{ 1988 ahci_power_up(ap); 1989 ahci_start_port(ap); 1990 1991 if (sata_pmp_attached(ap)) 1992 ahci_pmp_attach(ap); 1993 else 1994 ahci_pmp_detach(ap); 1995 1996 return 0; 1997} 1998 1999#ifdef CONFIG_PM 2000static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2001{ 2002 const char *emsg = NULL; 2003 int rc; 2004 2005 rc = ahci_deinit_port(ap, &emsg); 2006 if (rc == 0) 2007 ahci_power_down(ap); 2008 else { 2009 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 2010 ahci_start_port(ap); 2011 } 2012 2013 return rc; 2014} 2015#endif 2016 2017static int ahci_port_start(struct ata_port *ap) 2018{ 2019 struct ahci_host_priv *hpriv = ap->host->private_data; 2020 struct device *dev = ap->host->dev; 2021 struct ahci_port_priv *pp; 2022 void *mem; 2023 dma_addr_t mem_dma; 2024 size_t dma_sz, rx_fis_sz; 2025 2026 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2027 if (!pp) 2028 return -ENOMEM; 2029 2030 /* check FBS capability */ 2031 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2032 void __iomem *port_mmio = ahci_port_base(ap); 2033 u32 cmd = readl(port_mmio + PORT_CMD); 2034 if (cmd & PORT_CMD_FBSCP) 2035 pp->fbs_supported = true; 2036 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2037 dev_printk(KERN_INFO, dev, 2038 "port %d can do FBS, forcing FBSCP\n", 2039 ap->port_no); 2040 pp->fbs_supported = true; 2041 } else 2042 dev_printk(KERN_WARNING, dev, 2043 "port %d is not capable of FBS\n", 2044 ap->port_no); 2045 } 2046 2047 if (pp->fbs_supported) { 2048 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2049 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2050 } else { 2051 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2052 rx_fis_sz = AHCI_RX_FIS_SZ; 2053 } 2054 2055 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2056 if (!mem) 2057 return -ENOMEM; 2058 memset(mem, 0, dma_sz); 2059 2060 /* 2061 * First item in chunk of DMA memory: 32-slot command table, 2062 * 32 bytes each in size 2063 */ 2064 pp->cmd_slot = mem; 2065 pp->cmd_slot_dma = mem_dma; 2066 2067 mem += AHCI_CMD_SLOT_SZ; 2068 mem_dma += AHCI_CMD_SLOT_SZ; 2069 2070 /* 2071 * Second item: Received-FIS area 2072 */ 2073 pp->rx_fis = mem; 2074 pp->rx_fis_dma = mem_dma; 2075 2076 mem += rx_fis_sz; 2077 mem_dma += rx_fis_sz; 2078 2079 /* 2080 * Third item: data area for storing a single command 2081 * and its scatter-gather table 2082 */ 2083 pp->cmd_tbl = mem; 2084 pp->cmd_tbl_dma = mem_dma; 2085 2086 /* 2087 * Save off initial list of interrupts to be enabled. 2088 * This could be changed later 2089 */ 2090 pp->intr_mask = DEF_PORT_IRQ; 2091 2092 ap->private_data = pp; 2093 2094 /* engage engines, captain */ 2095 return ahci_port_resume(ap); 2096} 2097 2098static void ahci_port_stop(struct ata_port *ap) 2099{ 2100 const char *emsg = NULL; 2101 int rc; 2102 2103 /* de-initialize port */ 2104 rc = ahci_deinit_port(ap, &emsg); 2105 if (rc) 2106 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 2107} 2108 2109void ahci_print_info(struct ata_host *host, const char *scc_s) 2110{ 2111 struct ahci_host_priv *hpriv = host->private_data; 2112 void __iomem *mmio = hpriv->mmio; 2113 u32 vers, cap, cap2, impl, speed; 2114 const char *speed_s; 2115 2116 vers = readl(mmio + HOST_VERSION); 2117 cap = hpriv->cap; 2118 cap2 = hpriv->cap2; 2119 impl = hpriv->port_map; 2120 2121 speed = (cap >> 20) & 0xf; 2122 if (speed == 1) 2123 speed_s = "1.5"; 2124 else if (speed == 2) 2125 speed_s = "3"; 2126 else if (speed == 3) 2127 speed_s = "6"; 2128 else 2129 speed_s = "?"; 2130 2131 dev_info(host->dev, 2132 "AHCI %02x%02x.%02x%02x " 2133 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2134 , 2135 2136 (vers >> 24) & 0xff, 2137 (vers >> 16) & 0xff, 2138 (vers >> 8) & 0xff, 2139 vers & 0xff, 2140 2141 ((cap >> 8) & 0x1f) + 1, 2142 (cap & 0x1f) + 1, 2143 speed_s, 2144 impl, 2145 scc_s); 2146 2147 dev_info(host->dev, 2148 "flags: " 2149 "%s%s%s%s%s%s%s" 2150 "%s%s%s%s%s%s%s" 2151 "%s%s%s%s%s%s\n" 2152 , 2153 2154 cap & HOST_CAP_64 ? "64bit " : "", 2155 cap & HOST_CAP_NCQ ? "ncq " : "", 2156 cap & HOST_CAP_SNTF ? "sntf " : "", 2157 cap & HOST_CAP_MPS ? "ilck " : "", 2158 cap & HOST_CAP_SSS ? "stag " : "", 2159 cap & HOST_CAP_ALPM ? "pm " : "", 2160 cap & HOST_CAP_LED ? "led " : "", 2161 cap & HOST_CAP_CLO ? "clo " : "", 2162 cap & HOST_CAP_ONLY ? "only " : "", 2163 cap & HOST_CAP_PMP ? "pmp " : "", 2164 cap & HOST_CAP_FBS ? "fbs " : "", 2165 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2166 cap & HOST_CAP_SSC ? "slum " : "", 2167 cap & HOST_CAP_PART ? "part " : "", 2168 cap & HOST_CAP_CCC ? "ccc " : "", 2169 cap & HOST_CAP_EMS ? "ems " : "", 2170 cap & HOST_CAP_SXS ? "sxs " : "", 2171 cap2 & HOST_CAP2_APST ? "apst " : "", 2172 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2173 cap2 & HOST_CAP2_BOH ? "boh " : "" 2174 ); 2175} 2176EXPORT_SYMBOL_GPL(ahci_print_info); 2177 2178void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2179 struct ata_port_info *pi) 2180{ 2181 u8 messages; 2182 void __iomem *mmio = hpriv->mmio; 2183 u32 em_loc = readl(mmio + HOST_EM_LOC); 2184 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2185 2186 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2187 return; 2188 2189 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2190 2191 if (messages) { 2192 /* store em_loc */ 2193 hpriv->em_loc = ((em_loc >> 16) * 4); 2194 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2195 hpriv->em_msg_type = messages; 2196 pi->flags |= ATA_FLAG_EM; 2197 if (!(em_ctl & EM_CTL_ALHD)) 2198 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2199 } 2200} 2201EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2202 2203MODULE_AUTHOR("Jeff Garzik"); 2204MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2205MODULE_LICENSE("GPL"); 2206