1/* 2 * ahci.h - Common AHCI SATA definitions and declarations 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35#ifndef _AHCI_H 36#define _AHCI_H 37 38#include <linux/libata.h> 39 40#include <linux/spinlock.h> 41extern spinlock_t l2x0_reg_lock; 42#undef readl 43#undef readw 44#undef readb 45#define readl(c) \ 46 ({ \ 47 u32 __v; \ 48 unsigned long flags = 0; \ 49 if (ACP_WAR_ENAB()) \ 50 spin_lock_irqsave(&l2x0_reg_lock, flags); \ 51 __v = readl_relaxed(c); \ 52 if (ACP_WAR_ENAB()) \ 53 spin_unlock_irqrestore(&l2x0_reg_lock, flags); \ 54 __iormb(); \ 55 __v; \ 56 }) 57 58#define readw(c) \ 59 ({ \ 60 u16 __v; \ 61 unsigned long flags = 0; \ 62 if (ACP_WAR_ENAB()) \ 63 spin_lock_irqsave(&l2x0_reg_lock, flags); \ 64 __v = readw_relaxed(c); \ 65 if (ACP_WAR_ENAB()) \ 66 spin_unlock_irqrestore(&l2x0_reg_lock, flags); \ 67 __iormb(); \ 68 __v; \ 69 }) 70 71#define readb(c) \ 72 ({ \ 73 u8 __v; \ 74 unsigned long flags = 0; \ 75 if (ACP_WAR_ENAB()) \ 76 spin_lock_irqsave(&l2x0_reg_lock, flags); \ 77 __v = readb_relaxed(c); \ 78 if (ACP_WAR_ENAB()) \ 79 spin_unlock_irqrestore(&l2x0_reg_lock, flags); \ 80 __iormb(); \ 81 __v; \ 82 }) 83 84/* Enclosure Management Control */ 85#define EM_CTRL_MSG_TYPE 0x000f0000 86 87/* Enclosure Management LED Message Type */ 88#define EM_MSG_LED_HBA_PORT 0x0000000f 89#define EM_MSG_LED_PMP_SLOT 0x0000ff00 90#define EM_MSG_LED_VALUE 0xffff0000 91#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 92#define EM_MSG_LED_VALUE_OFF 0xfff80000 93#define EM_MSG_LED_VALUE_ON 0x00010000 94 95enum { 96 AHCI_MAX_PORTS = 32, 97 AHCI_MAX_SG = 168, /* hardware max is 64K */ 98 AHCI_DMA_BOUNDARY = 0xffffffff, 99 AHCI_MAX_CMDS = 32, 100 AHCI_CMD_SZ = 32, 101 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, 102 AHCI_RX_FIS_SZ = 256, 103 AHCI_CMD_TBL_CDB = 0x40, 104 AHCI_CMD_TBL_HDR_SZ = 0x80, 105 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), 106 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, 107 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + 108 AHCI_RX_FIS_SZ, 109 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + 110 AHCI_CMD_TBL_AR_SZ + 111 (AHCI_RX_FIS_SZ * 16), 112 AHCI_IRQ_ON_SG = (1 << 31), 113 AHCI_CMD_ATAPI = (1 << 5), 114 AHCI_CMD_WRITE = (1 << 6), 115 AHCI_CMD_PREFETCH = (1 << 7), 116 AHCI_CMD_RESET = (1 << 8), 117 AHCI_CMD_CLR_BUSY = (1 << 10), 118 119 RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ 120 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ 121 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ 122 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ 123 124 /* global controller registers */ 125 HOST_CAP = 0x00, /* host capabilities */ 126 HOST_CTL = 0x04, /* global host control */ 127 HOST_IRQ_STAT = 0x08, /* interrupt status */ 128 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ 129 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ 130 HOST_EM_LOC = 0x1c, /* Enclosure Management location */ 131 HOST_EM_CTL = 0x20, /* Enclosure Management Control */ 132 HOST_CAP2 = 0x24, /* host capabilities, extended */ 133 134 /* HOST_CTL bits */ 135 HOST_RESET = (1 << 0), /* reset controller; self-clear */ 136 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ 137 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ 138 139 /* HOST_CAP bits */ 140 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ 141 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ 142 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ 143 HOST_CAP_PART = (1 << 13), /* Partial state capable */ 144 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ 145 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ 146 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ 147 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ 148 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ 149 HOST_CAP_CLO = (1 << 24), /* Command List Override support */ 150 HOST_CAP_LED = (1 << 25), /* Supports activity LED */ 151 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ 152 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ 153 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ 154 HOST_CAP_SNTF = (1 << 29), /* SNotification register */ 155 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ 156 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ 157 158 /* HOST_CAP2 bits */ 159 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ 160 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ 161 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ 162 163 /* registers for each SATA port */ 164 PORT_LST_ADDR = 0x00, /* command list DMA addr */ 165 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ 166 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ 167 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ 168 PORT_IRQ_STAT = 0x10, /* interrupt status */ 169 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ 170 PORT_CMD = 0x18, /* port command */ 171 PORT_TFDATA = 0x20, /* taskfile data */ 172 PORT_SIG = 0x24, /* device TF signature */ 173 PORT_CMD_ISSUE = 0x38, /* command issue */ 174 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ 175 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ 176 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ 177 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ 178 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ 179 PORT_FBS = 0x40, /* FIS-based Switching */ 180 181 /* PORT_IRQ_{STAT,MASK} bits */ 182 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ 183 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ 184 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ 185 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ 186 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ 187 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ 188 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ 189 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ 190 191 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ 192 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ 193 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ 194 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ 195 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ 196 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ 197 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ 198 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ 199 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ 200 201 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | 202 PORT_IRQ_IF_ERR | 203 PORT_IRQ_CONNECT | 204 PORT_IRQ_PHYRDY | 205 PORT_IRQ_UNK_FIS | 206 PORT_IRQ_BAD_PMP, 207 PORT_IRQ_ERROR = PORT_IRQ_FREEZE | 208 PORT_IRQ_TF_ERR | 209 PORT_IRQ_HBUS_DATA_ERR, 210 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | 211 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | 212 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, 213 214 /* PORT_CMD bits */ 215 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ 216 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ 217 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ 218 PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ 219 PORT_CMD_PMP = (1 << 17), /* PMP attached */ 220 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ 221 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ 222 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ 223 PORT_CMD_CLO = (1 << 3), /* Command list override */ 224 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ 225 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ 226 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ 227 228 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ 229 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ 230 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ 231 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ 232 233 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ 234 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ 235 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ 236 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ 237 PORT_FBS_SDE = (1 << 2), /* FBS single device error */ 238 PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ 239 PORT_FBS_EN = (1 << 0), /* Enable FBS */ 240 241 /* hpriv->flags bits */ 242 AHCI_HFLAG_NO_NCQ = (1 << 0), 243 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ 244 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ 245 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ 246 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ 247 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ 248 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ 249 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ 250 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ 251 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ 252 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ 253 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as 254 link offline */ 255 AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ 256 AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */ 257 AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */ 258 259 /* ap->flags bits */ 260 261 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 262 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 263 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | 264 ATA_FLAG_IPM, 265 266 ICH_MAP = 0x90, /* ICH MAP register */ 267 268 /* em constants */ 269 EM_MAX_SLOTS = 8, 270 EM_MAX_RETRY = 5, 271 272 /* em_ctl bits */ 273 EM_CTL_RST = (1 << 9), /* Reset */ 274 EM_CTL_TM = (1 << 8), /* Transmit Message */ 275 EM_CTL_MR = (1 << 0), /* Message Recieved */ 276 EM_CTL_ALHD = (1 << 26), /* Activity LED */ 277 EM_CTL_XMT = (1 << 25), /* Transmit Only */ 278 EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ 279 280 /* em message type */ 281 EM_MSG_TYPE_LED = (1 << 0), /* LED */ 282 EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */ 283 EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */ 284 EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ 285}; 286 287struct ahci_cmd_hdr { 288 __le32 opts; 289 __le32 status; 290 __le32 tbl_addr; 291 __le32 tbl_addr_hi; 292 __le32 reserved[4]; 293}; 294 295struct ahci_sg { 296 __le32 addr; 297 __le32 addr_hi; 298 __le32 reserved; 299 __le32 flags_size; 300}; 301 302struct ahci_em_priv { 303 enum sw_activity blink_policy; 304 struct timer_list timer; 305 unsigned long saved_activity; 306 unsigned long activity; 307 unsigned long led_state; 308}; 309 310struct ahci_port_priv { 311 struct ata_link *active_link; 312 struct ahci_cmd_hdr *cmd_slot; 313 dma_addr_t cmd_slot_dma; 314 void *cmd_tbl; 315 dma_addr_t cmd_tbl_dma; 316 void *rx_fis; 317 dma_addr_t rx_fis_dma; 318 /* for NCQ spurious interrupt analysis */ 319 unsigned int ncq_saw_d2h:1; 320 unsigned int ncq_saw_dmas:1; 321 unsigned int ncq_saw_sdb:1; 322 u32 intr_mask; /* interrupts to enable */ 323 bool fbs_supported; /* set iff FBS is supported */ 324 bool fbs_enabled; /* set iff FBS is enabled */ 325 int fbs_last_dev; /* save FBS.DEV of last FIS */ 326 /* enclosure management info per PM slot */ 327 struct ahci_em_priv em_priv[EM_MAX_SLOTS]; 328}; 329 330struct ahci_host_priv { 331 void __iomem * mmio; /* bus-independant mem map */ 332 unsigned int flags; /* AHCI_HFLAG_* */ 333 u32 cap; /* cap to use */ 334 u32 cap2; /* cap2 to use */ 335 u32 port_map; /* port map to use */ 336 u32 saved_cap; /* saved initial cap */ 337 u32 saved_cap2; /* saved initial cap2 */ 338 u32 saved_port_map; /* saved initial port_map */ 339 u32 em_loc; /* enclosure management location */ 340 u32 em_buf_sz; /* EM buffer size in byte */ 341 u32 em_msg_type; /* EM message type */ 342}; 343 344extern int ahci_ignore_sss; 345 346extern struct device_attribute *ahci_shost_attrs[]; 347extern struct device_attribute *ahci_sdev_attrs[]; 348 349#define AHCI_SHT(drv_name) \ 350 ATA_NCQ_SHT(drv_name), \ 351 .can_queue = AHCI_MAX_CMDS - 1, \ 352 .sg_tablesize = AHCI_MAX_SG, \ 353 .dma_boundary = AHCI_DMA_BOUNDARY, \ 354 .shost_attrs = ahci_shost_attrs, \ 355 .sdev_attrs = ahci_sdev_attrs 356 357extern struct ata_port_operations ahci_ops; 358 359void ahci_save_initial_config(struct device *dev, 360 struct ahci_host_priv *hpriv, 361 unsigned int force_port_map, 362 unsigned int mask_port_map); 363void ahci_init_controller(struct ata_host *host); 364int ahci_reset_controller(struct ata_host *host); 365 366int ahci_do_softreset(struct ata_link *link, unsigned int *class, 367 int pmp, unsigned long deadline, 368 int (*check_ready)(struct ata_link *link)); 369 370int ahci_stop_engine(struct ata_port *ap); 371void ahci_start_engine(struct ata_port *ap); 372int ahci_check_ready(struct ata_link *link); 373int ahci_kick_engine(struct ata_port *ap); 374void ahci_set_em_messages(struct ahci_host_priv *hpriv, 375 struct ata_port_info *pi); 376int ahci_reset_em(struct ata_host *host); 377irqreturn_t ahci_interrupt(int irq, void *dev_instance); 378void ahci_print_info(struct ata_host *host, const char *scc_s); 379 380static inline void __iomem *__ahci_port_base(struct ata_host *host, 381 unsigned int port_no) 382{ 383 struct ahci_host_priv *hpriv = host->private_data; 384 void __iomem *mmio = hpriv->mmio; 385 386 return mmio + 0x100 + (port_no * 0x80); 387} 388 389static inline void __iomem *ahci_port_base(struct ata_port *ap) 390{ 391 return __ahci_port_base(ap->host, ap->port_no); 392} 393 394static inline int ahci_nr_ports(u32 cap) 395{ 396 return (cap & 0x1f) + 1; 397} 398 399#endif /* _AHCI_H */ 400