1#include <linux/clocksource.h> 2#include <linux/clockchips.h> 3#include <linux/interrupt.h> 4#include <linux/sysdev.h> 5#include <linux/delay.h> 6#include <linux/errno.h> 7#include <linux/slab.h> 8#include <linux/hpet.h> 9#include <linux/init.h> 10#include <linux/cpu.h> 11#include <linux/pm.h> 12#include <linux/io.h> 13 14#include <asm/fixmap.h> 15#include <asm/i8253.h> 16#include <asm/hpet.h> 17 18#define HPET_MASK CLOCKSOURCE_MASK(32) 19 20/* FSEC = 10^-15 21 NSEC = 10^-9 */ 22#define FSEC_PER_NSEC 1000000L 23 24#define HPET_DEV_USED_BIT 2 25#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) 26#define HPET_DEV_VALID 0x8 27#define HPET_DEV_FSB_CAP 0x1000 28#define HPET_DEV_PERI_CAP 0x2000 29 30#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) 31 32/* 33 * HPET address is set in acpi/boot.c, when an ACPI entry exists 34 */ 35unsigned long hpet_address; 36u8 hpet_blockid; /* OS timer block num */ 37u8 hpet_msi_disable; 38 39#ifdef CONFIG_PCI_MSI 40static unsigned long hpet_num_timers; 41#endif 42static void __iomem *hpet_virt_address; 43 44struct hpet_dev { 45 struct clock_event_device evt; 46 unsigned int num; 47 int cpu; 48 unsigned int irq; 49 unsigned int flags; 50 char name[10]; 51}; 52 53inline unsigned int hpet_readl(unsigned int a) 54{ 55 return readl(hpet_virt_address + a); 56} 57 58static inline void hpet_writel(unsigned int d, unsigned int a) 59{ 60 writel(d, hpet_virt_address + a); 61} 62 63#ifdef CONFIG_X86_64 64#include <asm/pgtable.h> 65#endif 66 67static inline void hpet_set_mapping(void) 68{ 69 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 70#ifdef CONFIG_X86_64 71 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); 72#endif 73} 74 75static inline void hpet_clear_mapping(void) 76{ 77 iounmap(hpet_virt_address); 78 hpet_virt_address = NULL; 79} 80 81/* 82 * HPET command line enable / disable 83 */ 84static int boot_hpet_disable; 85int hpet_force_user; 86static int hpet_verbose; 87 88static int __init hpet_setup(char *str) 89{ 90 if (str) { 91 if (!strncmp("disable", str, 7)) 92 boot_hpet_disable = 1; 93 if (!strncmp("force", str, 5)) 94 hpet_force_user = 1; 95 if (!strncmp("verbose", str, 7)) 96 hpet_verbose = 1; 97 } 98 return 1; 99} 100__setup("hpet=", hpet_setup); 101 102static int __init disable_hpet(char *str) 103{ 104 boot_hpet_disable = 1; 105 return 1; 106} 107__setup("nohpet", disable_hpet); 108 109static inline int is_hpet_capable(void) 110{ 111 return !boot_hpet_disable && hpet_address; 112} 113 114/* 115 * HPET timer interrupt enable / disable 116 */ 117static int hpet_legacy_int_enabled; 118 119/** 120 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 121 */ 122int is_hpet_enabled(void) 123{ 124 return is_hpet_capable() && hpet_legacy_int_enabled; 125} 126EXPORT_SYMBOL_GPL(is_hpet_enabled); 127 128static void _hpet_print_config(const char *function, int line) 129{ 130 u32 i, timers, l, h; 131 printk(KERN_INFO "hpet: %s(%d):\n", function, line); 132 l = hpet_readl(HPET_ID); 133 h = hpet_readl(HPET_PERIOD); 134 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 135 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); 136 l = hpet_readl(HPET_CFG); 137 h = hpet_readl(HPET_STATUS); 138 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); 139 l = hpet_readl(HPET_COUNTER); 140 h = hpet_readl(HPET_COUNTER+4); 141 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 142 143 for (i = 0; i < timers; i++) { 144 l = hpet_readl(HPET_Tn_CFG(i)); 145 h = hpet_readl(HPET_Tn_CFG(i)+4); 146 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", 147 i, l, h); 148 l = hpet_readl(HPET_Tn_CMP(i)); 149 h = hpet_readl(HPET_Tn_CMP(i)+4); 150 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", 151 i, l, h); 152 l = hpet_readl(HPET_Tn_ROUTE(i)); 153 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 154 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", 155 i, l, h); 156 } 157} 158 159#define hpet_print_config() \ 160do { \ 161 if (hpet_verbose) \ 162 _hpet_print_config(__FUNCTION__, __LINE__); \ 163} while (0) 164 165/* 166 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 167 * timer 0 and timer 1 in case of RTC emulation. 168 */ 169#ifdef CONFIG_HPET 170 171static void hpet_reserve_msi_timers(struct hpet_data *hd); 172 173static void hpet_reserve_platform_timers(unsigned int id) 174{ 175 struct hpet __iomem *hpet = hpet_virt_address; 176 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 177 unsigned int nrtimers, i; 178 struct hpet_data hd; 179 180 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 181 182 memset(&hd, 0, sizeof(hd)); 183 hd.hd_phys_address = hpet_address; 184 hd.hd_address = hpet; 185 hd.hd_nirqs = nrtimers; 186 hpet_reserve_timer(&hd, 0); 187 188#ifdef CONFIG_HPET_EMULATE_RTC 189 hpet_reserve_timer(&hd, 1); 190#endif 191 192 /* 193 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 194 * is wrong for i8259!) not the output IRQ. Many BIOS writers 195 * don't bother configuring *any* comparator interrupts. 196 */ 197 hd.hd_irq[0] = HPET_LEGACY_8254; 198 hd.hd_irq[1] = HPET_LEGACY_RTC; 199 200 for (i = 2; i < nrtimers; timer++, i++) { 201 hd.hd_irq[i] = (readl(&timer->hpet_config) & 202 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 203 } 204 205 hpet_reserve_msi_timers(&hd); 206 207 hpet_alloc(&hd); 208 209} 210#else 211static void hpet_reserve_platform_timers(unsigned int id) { } 212#endif 213 214/* 215 * Common hpet info 216 */ 217static unsigned long hpet_period; 218 219static void hpet_legacy_set_mode(enum clock_event_mode mode, 220 struct clock_event_device *evt); 221static int hpet_legacy_next_event(unsigned long delta, 222 struct clock_event_device *evt); 223 224/* 225 * The hpet clock event device 226 */ 227static struct clock_event_device hpet_clockevent = { 228 .name = "hpet", 229 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 230 .set_mode = hpet_legacy_set_mode, 231 .set_next_event = hpet_legacy_next_event, 232 .shift = 32, 233 .irq = 0, 234 .rating = 50, 235}; 236 237static void hpet_stop_counter(void) 238{ 239 unsigned long cfg = hpet_readl(HPET_CFG); 240 cfg &= ~HPET_CFG_ENABLE; 241 hpet_writel(cfg, HPET_CFG); 242} 243 244static void hpet_reset_counter(void) 245{ 246 hpet_writel(0, HPET_COUNTER); 247 hpet_writel(0, HPET_COUNTER + 4); 248} 249 250static void hpet_start_counter(void) 251{ 252 unsigned int cfg = hpet_readl(HPET_CFG); 253 cfg |= HPET_CFG_ENABLE; 254 hpet_writel(cfg, HPET_CFG); 255} 256 257static void hpet_restart_counter(void) 258{ 259 hpet_stop_counter(); 260 hpet_reset_counter(); 261 hpet_start_counter(); 262} 263 264static void hpet_resume_device(void) 265{ 266 force_hpet_resume(); 267} 268 269static void hpet_resume_counter(struct clocksource *cs) 270{ 271 hpet_resume_device(); 272 hpet_restart_counter(); 273} 274 275static void hpet_enable_legacy_int(void) 276{ 277 unsigned int cfg = hpet_readl(HPET_CFG); 278 279 cfg |= HPET_CFG_LEGACY; 280 hpet_writel(cfg, HPET_CFG); 281 hpet_legacy_int_enabled = 1; 282} 283 284static void hpet_legacy_clockevent_register(void) 285{ 286 /* Start HPET legacy interrupts */ 287 hpet_enable_legacy_int(); 288 289 /* 290 * The mult factor is defined as (include/linux/clockchips.h) 291 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) 292 * hpet_period is in units of femtoseconds (per cycle), so 293 * mult/2^shift = cyc/ns = 10^6/hpet_period 294 * mult = (10^6 * 2^shift)/hpet_period 295 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period 296 */ 297 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, 298 hpet_period, hpet_clockevent.shift); 299 /* Calculate the min / max delta */ 300 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, 301 &hpet_clockevent); 302 /* 5 usec minimum reprogramming delta. */ 303 hpet_clockevent.min_delta_ns = 5000; 304 305 /* 306 * Start hpet with the boot cpu mask and make it 307 * global after the IO_APIC has been initialized. 308 */ 309 hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); 310 clockevents_register_device(&hpet_clockevent); 311 global_clock_event = &hpet_clockevent; 312 printk(KERN_DEBUG "hpet clockevent registered\n"); 313} 314 315static int hpet_setup_msi_irq(unsigned int irq); 316 317static void hpet_set_mode(enum clock_event_mode mode, 318 struct clock_event_device *evt, int timer) 319{ 320 unsigned int cfg, cmp, now; 321 uint64_t delta; 322 323 switch (mode) { 324 case CLOCK_EVT_MODE_PERIODIC: 325 hpet_stop_counter(); 326 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; 327 delta >>= evt->shift; 328 now = hpet_readl(HPET_COUNTER); 329 cmp = now + (unsigned int) delta; 330 cfg = hpet_readl(HPET_Tn_CFG(timer)); 331 /* Make sure we use edge triggered interrupts */ 332 cfg &= ~HPET_TN_LEVEL; 333 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | 334 HPET_TN_SETVAL | HPET_TN_32BIT; 335 hpet_writel(cfg, HPET_Tn_CFG(timer)); 336 hpet_writel(cmp, HPET_Tn_CMP(timer)); 337 udelay(1); 338 /* 339 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 340 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 341 * bit is automatically cleared after the first write. 342 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 343 * Publication # 24674) 344 */ 345 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); 346 hpet_start_counter(); 347 hpet_print_config(); 348 break; 349 350 case CLOCK_EVT_MODE_ONESHOT: 351 cfg = hpet_readl(HPET_Tn_CFG(timer)); 352 cfg &= ~HPET_TN_PERIODIC; 353 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 354 hpet_writel(cfg, HPET_Tn_CFG(timer)); 355 break; 356 357 case CLOCK_EVT_MODE_UNUSED: 358 case CLOCK_EVT_MODE_SHUTDOWN: 359 cfg = hpet_readl(HPET_Tn_CFG(timer)); 360 cfg &= ~HPET_TN_ENABLE; 361 hpet_writel(cfg, HPET_Tn_CFG(timer)); 362 break; 363 364 case CLOCK_EVT_MODE_RESUME: 365 if (timer == 0) { 366 hpet_enable_legacy_int(); 367 } else { 368 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 369 hpet_setup_msi_irq(hdev->irq); 370 disable_irq(hdev->irq); 371 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); 372 enable_irq(hdev->irq); 373 } 374 hpet_print_config(); 375 break; 376 } 377} 378 379static int hpet_next_event(unsigned long delta, 380 struct clock_event_device *evt, int timer) 381{ 382 u32 cnt; 383 384 cnt = hpet_readl(HPET_COUNTER); 385 cnt += (u32) delta; 386 hpet_writel(cnt, HPET_Tn_CMP(timer)); 387 388 if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) { 389 if (hpet_readl(HPET_Tn_CMP(timer)) != cnt) 390 printk_once(KERN_WARNING 391 "hpet: compare register read back failed.\n"); 392 } 393 394 return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; 395} 396 397static void hpet_legacy_set_mode(enum clock_event_mode mode, 398 struct clock_event_device *evt) 399{ 400 hpet_set_mode(mode, evt, 0); 401} 402 403static int hpet_legacy_next_event(unsigned long delta, 404 struct clock_event_device *evt) 405{ 406 return hpet_next_event(delta, evt, 0); 407} 408 409/* 410 * HPET MSI Support 411 */ 412#ifdef CONFIG_PCI_MSI 413 414static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); 415static struct hpet_dev *hpet_devs; 416 417void hpet_msi_unmask(unsigned int irq) 418{ 419 struct hpet_dev *hdev = get_irq_data(irq); 420 unsigned int cfg; 421 422 /* unmask it */ 423 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 424 cfg |= HPET_TN_FSB; 425 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 426} 427 428void hpet_msi_mask(unsigned int irq) 429{ 430 unsigned int cfg; 431 struct hpet_dev *hdev = get_irq_data(irq); 432 433 /* mask it */ 434 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 435 cfg &= ~HPET_TN_FSB; 436 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 437} 438 439void hpet_msi_write(unsigned int irq, struct msi_msg *msg) 440{ 441 struct hpet_dev *hdev = get_irq_data(irq); 442 443 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); 444 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); 445} 446 447void hpet_msi_read(unsigned int irq, struct msi_msg *msg) 448{ 449 struct hpet_dev *hdev = get_irq_data(irq); 450 451 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); 452 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); 453 msg->address_hi = 0; 454} 455 456static void hpet_msi_set_mode(enum clock_event_mode mode, 457 struct clock_event_device *evt) 458{ 459 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 460 hpet_set_mode(mode, evt, hdev->num); 461} 462 463static int hpet_msi_next_event(unsigned long delta, 464 struct clock_event_device *evt) 465{ 466 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 467 return hpet_next_event(delta, evt, hdev->num); 468} 469 470static int hpet_setup_msi_irq(unsigned int irq) 471{ 472 if (arch_setup_hpet_msi(irq, hpet_blockid)) { 473 destroy_irq(irq); 474 return -EINVAL; 475 } 476 return 0; 477} 478 479static int hpet_assign_irq(struct hpet_dev *dev) 480{ 481 unsigned int irq; 482 483 irq = create_irq_nr(0, -1); 484 if (!irq) 485 return -EINVAL; 486 487 set_irq_data(irq, dev); 488 489 if (hpet_setup_msi_irq(irq)) 490 return -EINVAL; 491 492 dev->irq = irq; 493 return 0; 494} 495 496static irqreturn_t hpet_interrupt_handler(int irq, void *data) 497{ 498 struct hpet_dev *dev = (struct hpet_dev *)data; 499 struct clock_event_device *hevt = &dev->evt; 500 501 if (!hevt->event_handler) { 502 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", 503 dev->num); 504 return IRQ_HANDLED; 505 } 506 507 hevt->event_handler(hevt); 508 return IRQ_HANDLED; 509} 510 511static int hpet_setup_irq(struct hpet_dev *dev) 512{ 513 514 if (request_irq(dev->irq, hpet_interrupt_handler, 515 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, 516 dev->name, dev)) 517 return -1; 518 519 disable_irq(dev->irq); 520 irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); 521 enable_irq(dev->irq); 522 523 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", 524 dev->name, dev->irq); 525 526 return 0; 527} 528 529/* This should be called in specific @cpu */ 530static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) 531{ 532 struct clock_event_device *evt = &hdev->evt; 533 uint64_t hpet_freq; 534 535 WARN_ON(cpu != smp_processor_id()); 536 if (!(hdev->flags & HPET_DEV_VALID)) 537 return; 538 539 if (hpet_setup_msi_irq(hdev->irq)) 540 return; 541 542 hdev->cpu = cpu; 543 per_cpu(cpu_hpet_dev, cpu) = hdev; 544 evt->name = hdev->name; 545 hpet_setup_irq(hdev); 546 evt->irq = hdev->irq; 547 548 evt->rating = 110; 549 evt->features = CLOCK_EVT_FEAT_ONESHOT; 550 if (hdev->flags & HPET_DEV_PERI_CAP) 551 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 552 553 evt->set_mode = hpet_msi_set_mode; 554 evt->set_next_event = hpet_msi_next_event; 555 evt->shift = 32; 556 557 /* 558 * The period is a femto seconds value. We need to calculate the 559 * scaled math multiplication factor for nanosecond to hpet tick 560 * conversion. 561 */ 562 hpet_freq = FSEC_PER_SEC; 563 do_div(hpet_freq, hpet_period); 564 evt->mult = div_sc((unsigned long) hpet_freq, 565 NSEC_PER_SEC, evt->shift); 566 /* Calculate the max delta */ 567 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); 568 /* 5 usec minimum reprogramming delta. */ 569 evt->min_delta_ns = 5000; 570 571 evt->cpumask = cpumask_of(hdev->cpu); 572 clockevents_register_device(evt); 573} 574 575#ifdef CONFIG_HPET 576/* Reserve at least one timer for userspace (/dev/hpet) */ 577#define RESERVE_TIMERS 1 578#else 579#define RESERVE_TIMERS 0 580#endif 581 582static void hpet_msi_capability_lookup(unsigned int start_timer) 583{ 584 unsigned int id; 585 unsigned int num_timers; 586 unsigned int num_timers_used = 0; 587 int i; 588 589 if (hpet_msi_disable) 590 return; 591 592 if (boot_cpu_has(X86_FEATURE_ARAT)) 593 return; 594 id = hpet_readl(HPET_ID); 595 596 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 597 num_timers++; /* Value read out starts from 0 */ 598 hpet_print_config(); 599 600 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); 601 if (!hpet_devs) 602 return; 603 604 hpet_num_timers = num_timers; 605 606 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { 607 struct hpet_dev *hdev = &hpet_devs[num_timers_used]; 608 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); 609 610 /* Only consider HPET timer with MSI support */ 611 if (!(cfg & HPET_TN_FSB_CAP)) 612 continue; 613 614 hdev->flags = 0; 615 if (cfg & HPET_TN_PERIODIC_CAP) 616 hdev->flags |= HPET_DEV_PERI_CAP; 617 hdev->num = i; 618 619 sprintf(hdev->name, "hpet%d", i); 620 if (hpet_assign_irq(hdev)) 621 continue; 622 623 hdev->flags |= HPET_DEV_FSB_CAP; 624 hdev->flags |= HPET_DEV_VALID; 625 num_timers_used++; 626 if (num_timers_used == num_possible_cpus()) 627 break; 628 } 629 630 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", 631 num_timers, num_timers_used); 632} 633 634#ifdef CONFIG_HPET 635static void hpet_reserve_msi_timers(struct hpet_data *hd) 636{ 637 int i; 638 639 if (!hpet_devs) 640 return; 641 642 for (i = 0; i < hpet_num_timers; i++) { 643 struct hpet_dev *hdev = &hpet_devs[i]; 644 645 if (!(hdev->flags & HPET_DEV_VALID)) 646 continue; 647 648 hd->hd_irq[hdev->num] = hdev->irq; 649 hpet_reserve_timer(hd, hdev->num); 650 } 651} 652#endif 653 654static struct hpet_dev *hpet_get_unused_timer(void) 655{ 656 int i; 657 658 if (!hpet_devs) 659 return NULL; 660 661 for (i = 0; i < hpet_num_timers; i++) { 662 struct hpet_dev *hdev = &hpet_devs[i]; 663 664 if (!(hdev->flags & HPET_DEV_VALID)) 665 continue; 666 if (test_and_set_bit(HPET_DEV_USED_BIT, 667 (unsigned long *)&hdev->flags)) 668 continue; 669 return hdev; 670 } 671 return NULL; 672} 673 674struct hpet_work_struct { 675 struct delayed_work work; 676 struct completion complete; 677}; 678 679static void hpet_work(struct work_struct *w) 680{ 681 struct hpet_dev *hdev; 682 int cpu = smp_processor_id(); 683 struct hpet_work_struct *hpet_work; 684 685 hpet_work = container_of(w, struct hpet_work_struct, work.work); 686 687 hdev = hpet_get_unused_timer(); 688 if (hdev) 689 init_one_hpet_msi_clockevent(hdev, cpu); 690 691 complete(&hpet_work->complete); 692} 693 694static int hpet_cpuhp_notify(struct notifier_block *n, 695 unsigned long action, void *hcpu) 696{ 697 unsigned long cpu = (unsigned long)hcpu; 698 struct hpet_work_struct work; 699 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); 700 701 switch (action & 0xf) { 702 case CPU_ONLINE: 703 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work); 704 init_completion(&work.complete); 705 schedule_delayed_work_on(cpu, &work.work, 0); 706 wait_for_completion(&work.complete); 707 destroy_timer_on_stack(&work.work.timer); 708 break; 709 case CPU_DEAD: 710 if (hdev) { 711 free_irq(hdev->irq, hdev); 712 hdev->flags &= ~HPET_DEV_USED; 713 per_cpu(cpu_hpet_dev, cpu) = NULL; 714 } 715 break; 716 } 717 return NOTIFY_OK; 718} 719#else 720 721static int hpet_setup_msi_irq(unsigned int irq) 722{ 723 return 0; 724} 725static void hpet_msi_capability_lookup(unsigned int start_timer) 726{ 727 return; 728} 729 730#ifdef CONFIG_HPET 731static void hpet_reserve_msi_timers(struct hpet_data *hd) 732{ 733 return; 734} 735#endif 736 737static int hpet_cpuhp_notify(struct notifier_block *n, 738 unsigned long action, void *hcpu) 739{ 740 return NOTIFY_OK; 741} 742 743#endif 744 745/* 746 * Clock source related code 747 */ 748static cycle_t read_hpet(struct clocksource *cs) 749{ 750 return (cycle_t)hpet_readl(HPET_COUNTER); 751} 752 753#ifdef CONFIG_X86_64 754static cycle_t __vsyscall_fn vread_hpet(void) 755{ 756 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); 757} 758#endif 759 760static struct clocksource clocksource_hpet = { 761 .name = "hpet", 762 .rating = 250, 763 .read = read_hpet, 764 .mask = HPET_MASK, 765 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 766 .resume = hpet_resume_counter, 767#ifdef CONFIG_X86_64 768 .vread = vread_hpet, 769#endif 770}; 771 772static int hpet_clocksource_register(void) 773{ 774 u64 start, now; 775 u64 hpet_freq; 776 cycle_t t1; 777 778 /* Start the counter */ 779 hpet_restart_counter(); 780 781 /* Verify whether hpet counter works */ 782 t1 = hpet_readl(HPET_COUNTER); 783 rdtscll(start); 784 785 /* 786 * We don't know the TSC frequency yet, but waiting for 787 * 200000 TSC cycles is safe: 788 * 4 GHz == 50us 789 * 1 GHz == 200us 790 */ 791 do { 792 rep_nop(); 793 rdtscll(now); 794 } while ((now - start) < 200000UL); 795 796 if (t1 == hpet_readl(HPET_COUNTER)) { 797 printk(KERN_WARNING 798 "HPET counter not counting. HPET disabled\n"); 799 return -ENODEV; 800 } 801 802 /* 803 * The definition of mult is (include/linux/clocksource.h) 804 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc 805 * so we first need to convert hpet_period to ns/cyc units: 806 * mult/2^shift = ns/cyc = hpet_period/10^6 807 * mult = (hpet_period * 2^shift)/10^6 808 * mult = (hpet_period << shift)/FSEC_PER_NSEC 809 */ 810 811 /* Need to convert hpet_period (fsec/cyc) to cyc/sec: 812 * 813 * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc) 814 * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period 815 */ 816 hpet_freq = FSEC_PER_SEC; 817 do_div(hpet_freq, hpet_period); 818 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); 819 820 return 0; 821} 822 823/** 824 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 825 */ 826int __init hpet_enable(void) 827{ 828 unsigned int id; 829 int i; 830 831 if (!is_hpet_capable()) 832 return 0; 833 834 hpet_set_mapping(); 835 836 /* 837 * Read the period and check for a sane value: 838 */ 839 hpet_period = hpet_readl(HPET_PERIOD); 840 841 /* 842 * AMD SB700 based systems with spread spectrum enabled use a 843 * SMM based HPET emulation to provide proper frequency 844 * setting. The SMM code is initialized with the first HPET 845 * register access and takes some time to complete. During 846 * this time the config register reads 0xffffffff. We check 847 * for max. 1000 loops whether the config register reads a non 848 * 0xffffffff value to make sure that HPET is up and running 849 * before we go further. A counting loop is safe, as the HPET 850 * access takes thousands of CPU cycles. On non SB700 based 851 * machines this check is only done once and has no side 852 * effects. 853 */ 854 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { 855 if (i == 1000) { 856 printk(KERN_WARNING 857 "HPET config register value = 0xFFFFFFFF. " 858 "Disabling HPET\n"); 859 goto out_nohpet; 860 } 861 } 862 863 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 864 goto out_nohpet; 865 866 /* 867 * Read the HPET ID register to retrieve the IRQ routing 868 * information and the number of channels 869 */ 870 id = hpet_readl(HPET_ID); 871 hpet_print_config(); 872 873#ifdef CONFIG_HPET_EMULATE_RTC 874 /* 875 * The legacy routing mode needs at least two channels, tick timer 876 * and the rtc emulation channel. 877 */ 878 if (!(id & HPET_ID_NUMBER)) 879 goto out_nohpet; 880#endif 881 882 if (hpet_clocksource_register()) 883 goto out_nohpet; 884 885 if (id & HPET_ID_LEGSUP) { 886 hpet_legacy_clockevent_register(); 887 return 1; 888 } 889 return 0; 890 891out_nohpet: 892 hpet_clear_mapping(); 893 hpet_address = 0; 894 return 0; 895} 896 897/* 898 * Needs to be late, as the reserve_timer code calls kalloc ! 899 * 900 * Not a problem on i386 as hpet_enable is called from late_time_init, 901 * but on x86_64 it is necessary ! 902 */ 903static __init int hpet_late_init(void) 904{ 905 int cpu; 906 907 if (boot_hpet_disable) 908 return -ENODEV; 909 910 if (!hpet_address) { 911 if (!force_hpet_address) 912 return -ENODEV; 913 914 hpet_address = force_hpet_address; 915 hpet_enable(); 916 } 917 918 if (!hpet_virt_address) 919 return -ENODEV; 920 921 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) 922 hpet_msi_capability_lookup(2); 923 else 924 hpet_msi_capability_lookup(0); 925 926 hpet_reserve_platform_timers(hpet_readl(HPET_ID)); 927 hpet_print_config(); 928 929 if (hpet_msi_disable) 930 return 0; 931 932 if (boot_cpu_has(X86_FEATURE_ARAT)) 933 return 0; 934 935 for_each_online_cpu(cpu) { 936 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); 937 } 938 939 /* This notifier should be called after workqueue is ready */ 940 hotcpu_notifier(hpet_cpuhp_notify, -20); 941 942 return 0; 943} 944fs_initcall(hpet_late_init); 945 946void hpet_disable(void) 947{ 948 if (is_hpet_capable() && hpet_virt_address) { 949 unsigned int cfg = hpet_readl(HPET_CFG); 950 951 if (hpet_legacy_int_enabled) { 952 cfg &= ~HPET_CFG_LEGACY; 953 hpet_legacy_int_enabled = 0; 954 } 955 cfg &= ~HPET_CFG_ENABLE; 956 hpet_writel(cfg, HPET_CFG); 957 } 958} 959 960#ifdef CONFIG_HPET_EMULATE_RTC 961 962/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 963 * is enabled, we support RTC interrupt functionality in software. 964 * RTC has 3 kinds of interrupts: 965 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 966 * is updated 967 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 968 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 969 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 970 * (1) and (2) above are implemented using polling at a frequency of 971 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 972 * overhead. (DEFAULT_RTC_INT_FREQ) 973 * For (3), we use interrupts at 64Hz or user specified periodic 974 * frequency, whichever is higher. 975 */ 976#include <linux/mc146818rtc.h> 977#include <linux/rtc.h> 978#include <asm/rtc.h> 979 980#define DEFAULT_RTC_INT_FREQ 64 981#define DEFAULT_RTC_SHIFT 6 982#define RTC_NUM_INTS 1 983 984static unsigned long hpet_rtc_flags; 985static int hpet_prev_update_sec; 986static struct rtc_time hpet_alarm_time; 987static unsigned long hpet_pie_count; 988static u32 hpet_t1_cmp; 989static u32 hpet_default_delta; 990static u32 hpet_pie_delta; 991static unsigned long hpet_pie_limit; 992 993static rtc_irq_handler irq_handler; 994 995/* 996 * Check that the hpet counter c1 is ahead of the c2 997 */ 998static inline int hpet_cnt_ahead(u32 c1, u32 c2) 999{ 1000 return (s32)(c2 - c1) < 0; 1001} 1002 1003/* 1004 * Registers a IRQ handler. 1005 */ 1006int hpet_register_irq_handler(rtc_irq_handler handler) 1007{ 1008 if (!is_hpet_enabled()) 1009 return -ENODEV; 1010 if (irq_handler) 1011 return -EBUSY; 1012 1013 irq_handler = handler; 1014 1015 return 0; 1016} 1017EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 1018 1019/* 1020 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 1021 * and does cleanup. 1022 */ 1023void hpet_unregister_irq_handler(rtc_irq_handler handler) 1024{ 1025 if (!is_hpet_enabled()) 1026 return; 1027 1028 irq_handler = NULL; 1029 hpet_rtc_flags = 0; 1030} 1031EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1032 1033/* 1034 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 1035 * is not supported by all HPET implementations for timer 1. 1036 * 1037 * hpet_rtc_timer_init() is called when the rtc is initialized. 1038 */ 1039int hpet_rtc_timer_init(void) 1040{ 1041 unsigned int cfg, cnt, delta; 1042 unsigned long flags; 1043 1044 if (!is_hpet_enabled()) 1045 return 0; 1046 1047 if (!hpet_default_delta) { 1048 uint64_t clc; 1049 1050 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1051 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 1052 hpet_default_delta = clc; 1053 } 1054 1055 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1056 delta = hpet_default_delta; 1057 else 1058 delta = hpet_pie_delta; 1059 1060 local_irq_save(flags); 1061 1062 cnt = delta + hpet_readl(HPET_COUNTER); 1063 hpet_writel(cnt, HPET_T1_CMP); 1064 hpet_t1_cmp = cnt; 1065 1066 cfg = hpet_readl(HPET_T1_CFG); 1067 cfg &= ~HPET_TN_PERIODIC; 1068 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1069 hpet_writel(cfg, HPET_T1_CFG); 1070 1071 local_irq_restore(flags); 1072 1073 return 1; 1074} 1075EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1076 1077/* 1078 * The functions below are called from rtc driver. 1079 * Return 0 if HPET is not being used. 1080 * Otherwise do the necessary changes and return 1. 1081 */ 1082int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1083{ 1084 if (!is_hpet_enabled()) 1085 return 0; 1086 1087 hpet_rtc_flags &= ~bit_mask; 1088 return 1; 1089} 1090EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1091 1092int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1093{ 1094 unsigned long oldbits = hpet_rtc_flags; 1095 1096 if (!is_hpet_enabled()) 1097 return 0; 1098 1099 hpet_rtc_flags |= bit_mask; 1100 1101 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1102 hpet_prev_update_sec = -1; 1103 1104 if (!oldbits) 1105 hpet_rtc_timer_init(); 1106 1107 return 1; 1108} 1109EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1110 1111int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 1112 unsigned char sec) 1113{ 1114 if (!is_hpet_enabled()) 1115 return 0; 1116 1117 hpet_alarm_time.tm_hour = hrs; 1118 hpet_alarm_time.tm_min = min; 1119 hpet_alarm_time.tm_sec = sec; 1120 1121 return 1; 1122} 1123EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1124 1125int hpet_set_periodic_freq(unsigned long freq) 1126{ 1127 uint64_t clc; 1128 1129 if (!is_hpet_enabled()) 1130 return 0; 1131 1132 if (freq <= DEFAULT_RTC_INT_FREQ) 1133 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1134 else { 1135 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1136 do_div(clc, freq); 1137 clc >>= hpet_clockevent.shift; 1138 hpet_pie_delta = clc; 1139 hpet_pie_limit = 0; 1140 } 1141 return 1; 1142} 1143EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1144 1145int hpet_rtc_dropped_irq(void) 1146{ 1147 return is_hpet_enabled(); 1148} 1149EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1150 1151static void hpet_rtc_timer_reinit(void) 1152{ 1153 unsigned int cfg, delta; 1154 int lost_ints = -1; 1155 1156 if (unlikely(!hpet_rtc_flags)) { 1157 cfg = hpet_readl(HPET_T1_CFG); 1158 cfg &= ~HPET_TN_ENABLE; 1159 hpet_writel(cfg, HPET_T1_CFG); 1160 return; 1161 } 1162 1163 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1164 delta = hpet_default_delta; 1165 else 1166 delta = hpet_pie_delta; 1167 1168 /* 1169 * Increment the comparator value until we are ahead of the 1170 * current count. 1171 */ 1172 do { 1173 hpet_t1_cmp += delta; 1174 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1175 lost_ints++; 1176 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1177 1178 if (lost_ints) { 1179 if (hpet_rtc_flags & RTC_PIE) 1180 hpet_pie_count += lost_ints; 1181 if (printk_ratelimit()) 1182 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", 1183 lost_ints); 1184 } 1185} 1186 1187irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1188{ 1189 struct rtc_time curr_time; 1190 unsigned long rtc_int_flag = 0; 1191 1192 hpet_rtc_timer_reinit(); 1193 memset(&curr_time, 0, sizeof(struct rtc_time)); 1194 1195 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 1196 get_rtc_time(&curr_time); 1197 1198 if (hpet_rtc_flags & RTC_UIE && 1199 curr_time.tm_sec != hpet_prev_update_sec) { 1200 if (hpet_prev_update_sec >= 0) 1201 rtc_int_flag = RTC_UF; 1202 hpet_prev_update_sec = curr_time.tm_sec; 1203 } 1204 1205 if (hpet_rtc_flags & RTC_PIE && 1206 ++hpet_pie_count >= hpet_pie_limit) { 1207 rtc_int_flag |= RTC_PF; 1208 hpet_pie_count = 0; 1209 } 1210 1211 if (hpet_rtc_flags & RTC_AIE && 1212 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1213 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1214 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1215 rtc_int_flag |= RTC_AF; 1216 1217 if (rtc_int_flag) { 1218 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1219 if (irq_handler) 1220 irq_handler(rtc_int_flag, dev_id); 1221 } 1222 return IRQ_HANDLED; 1223} 1224EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1225#endif 1226