1/* 2 * (c) 2003-2006 Advanced Micro Devices, Inc. 3 * Your use of this code is subject to the terms and conditions of the 4 * GNU general public license version 2. See "COPYING" or 5 * http://www.gnu.org/licenses/gpl.html 6 */ 7 8enum pstate { 9 HW_PSTATE_INVALID = 0xff, 10 HW_PSTATE_0 = 0, 11 HW_PSTATE_1 = 1, 12 HW_PSTATE_2 = 2, 13 HW_PSTATE_3 = 3, 14 HW_PSTATE_4 = 4, 15 HW_PSTATE_5 = 5, 16 HW_PSTATE_6 = 6, 17 HW_PSTATE_7 = 7, 18}; 19 20struct powernow_k8_data { 21 unsigned int cpu; 22 23 u32 numps; /* number of p-states */ 24 u32 batps; /* number of p-states supported on battery */ 25 u32 max_hw_pstate; /* maximum legal hardware pstate */ 26 27 /* these values are constant when the PSB is used to determine 28 * vid/fid pairings, but are modified during the ->target() call 29 * when ACPI is used */ 30 u32 rvo; /* ramp voltage offset */ 31 u32 irt; /* isochronous relief time */ 32 u32 vidmvs; /* usable value calculated from mvs */ 33 u32 vstable; /* voltage stabilization time, units 20 us */ 34 u32 plllock; /* pll lock time, units 1 us */ 35 u32 exttype; /* extended interface = 1 */ 36 37 /* keep track of the current fid / vid or pstate */ 38 u32 currvid; 39 u32 currfid; 40 enum pstate currpstate; 41 42 /* the powernow_table includes all frequency and vid/fid pairings: 43 * fid are the lower 8 bits of the index, vid are the upper 8 bits. 44 * frequency is in kHz */ 45 struct cpufreq_frequency_table *powernow_table; 46 47 /* the acpi table needs to be kept. it's only available if ACPI was 48 * used to determine valid frequency/vid/fid states */ 49 struct acpi_processor_performance acpi_data; 50 51 /* we need to keep track of associated cores, but let cpufreq 52 * handle hotplug events - so just point at cpufreq pol->cpus 53 * structure */ 54 struct cpumask *available_cores; 55}; 56 57/* processor's cpuid instruction support */ 58#define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */ 59#define CPUID_XFAM 0x0ff00000 /* extended family */ 60#define CPUID_XFAM_K8 0 61#define CPUID_XMOD 0x000f0000 /* extended model */ 62#define CPUID_XMOD_REV_MASK 0x000c0000 63#define CPUID_XFAM_10H 0x00100000 /* family 0x10 */ 64#define CPUID_USE_XFAM_XMOD 0x00000f00 65#define CPUID_GET_MAX_CAPABILITIES 0x80000000 66#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 67#define P_STATE_TRANSITION_CAPABLE 6 68 69/* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */ 70/* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ 71/* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */ 72/* the register number is placed in ecx, and the data is returned in edx:eax. */ 73 74#define MSR_FIDVID_CTL 0xc0010041 75#define MSR_FIDVID_STATUS 0xc0010042 76 77/* Field definitions within the FID VID Low Control MSR : */ 78#define MSR_C_LO_INIT_FID_VID 0x00010000 79#define MSR_C_LO_NEW_VID 0x00003f00 80#define MSR_C_LO_NEW_FID 0x0000003f 81#define MSR_C_LO_VID_SHIFT 8 82 83/* Field definitions within the FID VID High Control MSR : */ 84#define MSR_C_HI_STP_GNT_TO 0x000fffff 85 86/* Field definitions within the FID VID Low Status MSR : */ 87#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */ 88#define MSR_S_LO_MAX_RAMP_VID 0x3f000000 89#define MSR_S_LO_MAX_FID 0x003f0000 90#define MSR_S_LO_START_FID 0x00003f00 91#define MSR_S_LO_CURRENT_FID 0x0000003f 92 93/* Field definitions within the FID VID High Status MSR : */ 94#define MSR_S_HI_MIN_WORKING_VID 0x3f000000 95#define MSR_S_HI_MAX_WORKING_VID 0x003f0000 96#define MSR_S_HI_START_VID 0x00003f00 97#define MSR_S_HI_CURRENT_VID 0x0000003f 98#define MSR_C_HI_STP_GNT_BENIGN 0x00000001 99 100 101/* Hardware Pstate _PSS and MSR definitions */ 102#define USE_HW_PSTATE 0x00000080 103#define HW_PSTATE_MASK 0x00000007 104#define HW_PSTATE_VALID_MASK 0x80000000 105#define HW_PSTATE_MAX_MASK 0x000000f0 106#define HW_PSTATE_MAX_SHIFT 4 107#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */ 108#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */ 109#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */ 110#define MSR_PSTATE_CUR_LIMIT 0xc0010061 /* pstate current limit MSR */ 111 112/* define the two driver architectures */ 113#define CPU_OPTERON 0 114#define CPU_HW_PSTATE 1 115 116 117/* 118 * There are restrictions frequencies have to follow: 119 * - only 1 entry in the low fid table ( <=1.4GHz ) 120 * - lowest entry in the high fid table must be >= 2 * the entry in the 121 * low fid table 122 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry 123 * in the low fid table 124 * - the parts can only step at <= 200 MHz intervals, odd fid values are 125 * supported in revision G and later revisions. 126 * - lowest frequency must be >= interprocessor hypertransport link speed 127 * (only applies to MP systems obviously) 128 */ 129 130/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */ 131#define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */ 132#define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */ 133 134#define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */ 135#define HI_VCOFREQ_TABLE_BOTTOM 1600 136 137#define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */ 138 139#define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */ 140#define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */ 141 142#define MIN_FREQ 800 /* Min and max freqs, per spec */ 143#define MAX_FREQ 5000 144 145#define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */ 146#define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */ 147 148#define VID_OFF 0x3f 149 150#define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */ 151 152#define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */ 153 154#define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */ 155#define VST_UNITS_20US 20 /* Voltage Stabilization Time is in units of 20us */ 156 157/* 158 * Most values of interest are encoded in a single field of the _PSS 159 * entries: the "control" value. 160 */ 161 162#define IRT_SHIFT 30 163#define RVO_SHIFT 28 164#define EXT_TYPE_SHIFT 27 165#define PLL_L_SHIFT 20 166#define MVS_SHIFT 18 167#define VST_SHIFT 11 168#define VID_SHIFT 6 169#define IRT_MASK 3 170#define RVO_MASK 3 171#define EXT_TYPE_MASK 1 172#define PLL_L_MASK 0x7f 173#define MVS_MASK 3 174#define VST_MASK 0x7f 175#define VID_MASK 0x1f 176#define FID_MASK 0x1f 177#define EXT_VID_MASK 0x3f 178#define EXT_FID_MASK 0x3f 179 180 181/* 182 * Version 1.4 of the PSB table. This table is constructed by BIOS and is 183 * to tell the OS's power management driver which VIDs and FIDs are 184 * supported by this particular processor. 185 * If the data in the PSB / PST is wrong, then this driver will program the 186 * wrong values into hardware, which is very likely to lead to a crash. 187 */ 188 189#define PSB_ID_STRING "AMDK7PNOW!" 190#define PSB_ID_STRING_LEN 10 191 192#define PSB_VERSION_1_4 0x14 193 194struct psb_s { 195 u8 signature[10]; 196 u8 tableversion; 197 u8 flags1; 198 u16 vstable; 199 u8 flags2; 200 u8 num_tables; 201 u32 cpuid; 202 u8 plllocktime; 203 u8 maxfid; 204 u8 maxvid; 205 u8 numps; 206}; 207 208/* Pairs of fid/vid values are appended to the version 1.4 PSB table. */ 209struct pst_s { 210 u8 fid; 211 u8 vid; 212}; 213 214#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "powernow-k8", msg) 215 216static int core_voltage_pre_transition(struct powernow_k8_data *data, 217 u32 reqvid, u32 regfid); 218static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid); 219static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid); 220 221static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); 222 223static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); 224static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); 225