1/* 2 * IBM Summit-Specific Code 3 * 4 * Written By: Matthew Dobson, IBM Corporation 5 * 6 * Copyright (c) 2003 IBM Corp. 7 * 8 * All rights reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 18 * NON INFRINGEMENT. See the GNU General Public License for more 19 * details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * Send feedback to <colpatch@us.ibm.com> 26 * 27 */ 28 29#include <linux/mm.h> 30#include <linux/init.h> 31#include <asm/io.h> 32#include <asm/bios_ebda.h> 33 34/* 35 * APIC driver for the IBM "Summit" chipset. 36 */ 37#include <linux/threads.h> 38#include <linux/cpumask.h> 39#include <asm/mpspec.h> 40#include <asm/apic.h> 41#include <asm/smp.h> 42#include <asm/fixmap.h> 43#include <asm/apicdef.h> 44#include <asm/ipi.h> 45#include <linux/kernel.h> 46#include <linux/string.h> 47#include <linux/gfp.h> 48#include <linux/smp.h> 49 50static unsigned summit_get_apic_id(unsigned long x) 51{ 52 return (x >> 24) & 0xFF; 53} 54 55static inline void summit_send_IPI_mask(const struct cpumask *mask, int vector) 56{ 57 default_send_IPI_mask_sequence_logical(mask, vector); 58} 59 60static void summit_send_IPI_allbutself(int vector) 61{ 62 default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector); 63} 64 65static void summit_send_IPI_all(int vector) 66{ 67 summit_send_IPI_mask(cpu_online_mask, vector); 68} 69 70#include <asm/tsc.h> 71 72extern int use_cyclone; 73 74#ifdef CONFIG_X86_SUMMIT_NUMA 75static void setup_summit(void); 76#else 77static inline void setup_summit(void) {} 78#endif 79 80static int summit_mps_oem_check(struct mpc_table *mpc, char *oem, 81 char *productid) 82{ 83 if (!strncmp(oem, "IBM ENSW", 8) && 84 (!strncmp(productid, "VIGIL SMP", 9) 85 || !strncmp(productid, "EXA", 3) 86 || !strncmp(productid, "RUTHLESS SMP", 12))){ 87 mark_tsc_unstable("Summit based system"); 88 use_cyclone = 1; /*enable cyclone-timer*/ 89 setup_summit(); 90 return 1; 91 } 92 return 0; 93} 94 95/* Hook from generic ACPI tables.c */ 96static int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 97{ 98 if (!strncmp(oem_id, "IBM", 3) && 99 (!strncmp(oem_table_id, "SERVIGIL", 8) 100 || !strncmp(oem_table_id, "EXA", 3))){ 101 mark_tsc_unstable("Summit based system"); 102 use_cyclone = 1; /*enable cyclone-timer*/ 103 setup_summit(); 104 return 1; 105 } 106 return 0; 107} 108 109struct rio_table_hdr { 110 unsigned char version; /* Version number of this data structure */ 111 /* Version 3 adds chassis_num & WP_index */ 112 unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil) */ 113 unsigned char num_rio_dev; /* # of RIO I/O devices (Cyclones and Winnipegs) */ 114} __attribute__((packed)); 115 116struct scal_detail { 117 unsigned char node_id; /* Scalability Node ID */ 118 unsigned long CBAR; /* Address of 1MB register space */ 119 unsigned char port0node; /* Node ID port connected to: 0xFF=None */ 120 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */ 121 unsigned char port1node; /* Node ID port connected to: 0xFF = None */ 122 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */ 123 unsigned char port2node; /* Node ID port connected to: 0xFF = None */ 124 unsigned char port2port; /* Port num port connected to: 0,1,2, or 0xFF=None */ 125 unsigned char chassis_num; /* 1 based Chassis number (1 = boot node) */ 126} __attribute__((packed)); 127 128struct rio_detail { 129 unsigned char node_id; /* RIO Node ID */ 130 unsigned long BBAR; /* Address of 1MB register space */ 131 unsigned char type; /* Type of device */ 132 unsigned char owner_id; /* For WPEG: Node ID of Cyclone that owns this WPEG*/ 133 /* For CYC: Node ID of Twister that owns this CYC */ 134 unsigned char port0node; /* Node ID port connected to: 0xFF=None */ 135 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */ 136 unsigned char port1node; /* Node ID port connected to: 0xFF=None */ 137 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */ 138 unsigned char first_slot; /* For WPEG: Lowest slot number below this WPEG */ 139 /* For CYC: 0 */ 140 unsigned char status; /* For WPEG: Bit 0 = 1 : the XAPIC is used */ 141 /* = 0 : the XAPIC is not used, ie:*/ 142 /* ints fwded to another XAPIC */ 143 /* Bits1:7 Reserved */ 144 /* For CYC: Bits0:7 Reserved */ 145 unsigned char WP_index; /* For WPEG: WPEG instance index - lower ones have */ 146 /* lower slot numbers/PCI bus numbers */ 147 /* For CYC: No meaning */ 148 unsigned char chassis_num; /* 1 based Chassis number */ 149 /* For LookOut WPEGs this field indicates the */ 150 /* Expansion Chassis #, enumerated from Boot */ 151 /* Node WPEG external port, then Boot Node CYC */ 152 /* external port, then Next Vigil chassis WPEG */ 153 /* external port, etc. */ 154 /* Shared Lookouts have only 1 chassis number (the */ 155 /* first one assigned) */ 156} __attribute__((packed)); 157 158 159typedef enum { 160 CompatTwister = 0, /* Compatibility Twister */ 161 AltTwister = 1, /* Alternate Twister of internal 8-way */ 162 CompatCyclone = 2, /* Compatibility Cyclone */ 163 AltCyclone = 3, /* Alternate Cyclone of internal 8-way */ 164 CompatWPEG = 4, /* Compatibility WPEG */ 165 AltWPEG = 5, /* Second Planar WPEG */ 166 LookOutAWPEG = 6, /* LookOut WPEG */ 167 LookOutBWPEG = 7, /* LookOut WPEG */ 168} node_type; 169 170static inline int is_WPEG(struct rio_detail *rio){ 171 return (rio->type == CompatWPEG || rio->type == AltWPEG || 172 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG); 173} 174 175#define SUMMIT_APIC_DFR_VALUE (APIC_DFR_CLUSTER) 176 177static const struct cpumask *summit_target_cpus(void) 178{ 179 /* CPU_MASK_ALL (0xff) has undefined behaviour with 180 * dest_LowestPrio mode logical clustered apic interrupt routing 181 * Just start on cpu 0. IRQ balancing will spread load 182 */ 183 return cpumask_of(0); 184} 185 186static unsigned long summit_check_apicid_used(physid_mask_t *map, int apicid) 187{ 188 return 0; 189} 190 191/* we don't use the phys_cpu_present_map to indicate apicid presence */ 192static unsigned long summit_check_apicid_present(int bit) 193{ 194 return 1; 195} 196 197static void summit_init_apic_ldr(void) 198{ 199 unsigned long val, id; 200 int count = 0; 201 u8 my_id = (u8)hard_smp_processor_id(); 202 u8 my_cluster = APIC_CLUSTER(my_id); 203#ifdef CONFIG_SMP 204 u8 lid; 205 int i; 206 207 /* Create logical APIC IDs by counting CPUs already in cluster. */ 208 for (count = 0, i = nr_cpu_ids; --i >= 0; ) { 209 lid = cpu_2_logical_apicid[i]; 210 if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster) 211 ++count; 212 } 213#endif 214 /* We only have a 4 wide bitmap in cluster mode. If a deranged 215 * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */ 216 BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT); 217 id = my_cluster | (1UL << count); 218 apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE); 219 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 220 val |= SET_APIC_LOGICAL_ID(id); 221 apic_write(APIC_LDR, val); 222} 223 224static int summit_apic_id_registered(void) 225{ 226 return 1; 227} 228 229static void summit_setup_apic_routing(void) 230{ 231 printk("Enabling APIC mode: Summit. Using %d I/O APICs\n", 232 nr_ioapics); 233} 234 235static int summit_apicid_to_node(int logical_apicid) 236{ 237#ifdef CONFIG_SMP 238 return apicid_2_node[hard_smp_processor_id()]; 239#else 240 return 0; 241#endif 242} 243 244/* Mapping from cpu number to logical apicid */ 245static inline int summit_cpu_to_logical_apicid(int cpu) 246{ 247#ifdef CONFIG_SMP 248 if (cpu >= nr_cpu_ids) 249 return BAD_APICID; 250 return cpu_2_logical_apicid[cpu]; 251#else 252 return logical_smp_processor_id(); 253#endif 254} 255 256static int summit_cpu_present_to_apicid(int mps_cpu) 257{ 258 if (mps_cpu < nr_cpu_ids) 259 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); 260 else 261 return BAD_APICID; 262} 263 264static void summit_ioapic_phys_id_map(physid_mask_t *phys_id_map, physid_mask_t *retmap) 265{ 266 /* For clustered we don't have a good way to do this yet - hack */ 267 physids_promote(0x0FL, retmap); 268} 269 270static void summit_apicid_to_cpu_present(int apicid, physid_mask_t *retmap) 271{ 272 physid_set_mask_of_physid(0, retmap); 273} 274 275static int summit_check_phys_apicid_present(int physical_apicid) 276{ 277 return 1; 278} 279 280static unsigned int summit_cpu_mask_to_apicid(const struct cpumask *cpumask) 281{ 282 unsigned int round = 0; 283 int cpu, apicid = 0; 284 285 /* 286 * The cpus in the mask must all be on the apic cluster. 287 */ 288 for_each_cpu(cpu, cpumask) { 289 int new_apicid = summit_cpu_to_logical_apicid(cpu); 290 291 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) { 292 printk("%s: Not a valid mask!\n", __func__); 293 return BAD_APICID; 294 } 295 apicid |= new_apicid; 296 round++; 297 } 298 return apicid; 299} 300 301static unsigned int summit_cpu_mask_to_apicid_and(const struct cpumask *inmask, 302 const struct cpumask *andmask) 303{ 304 int apicid = summit_cpu_to_logical_apicid(0); 305 cpumask_var_t cpumask; 306 307 if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) 308 return apicid; 309 310 cpumask_and(cpumask, inmask, andmask); 311 cpumask_and(cpumask, cpumask, cpu_online_mask); 312 apicid = summit_cpu_mask_to_apicid(cpumask); 313 314 free_cpumask_var(cpumask); 315 316 return apicid; 317} 318 319/* 320 * cpuid returns the value latched in the HW at reset, not the APIC ID 321 * register's value. For any box whose BIOS changes APIC IDs, like 322 * clustered APIC systems, we must use hard_smp_processor_id. 323 * 324 * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID. 325 */ 326static int summit_phys_pkg_id(int cpuid_apic, int index_msb) 327{ 328 return hard_smp_processor_id() >> index_msb; 329} 330 331static int probe_summit(void) 332{ 333 /* probed later in mptable/ACPI hooks */ 334 return 0; 335} 336 337static void summit_vector_allocation_domain(int cpu, struct cpumask *retmask) 338{ 339 /* Careful. Some cpus do not strictly honor the set of cpus 340 * specified in the interrupt destination when using lowest 341 * priority interrupt delivery mode. 342 * 343 * In particular there was a hyperthreading cpu observed to 344 * deliver interrupts to the wrong hyperthread when only one 345 * hyperthread was specified in the interrupt desitination. 346 */ 347 cpumask_clear(retmask); 348 cpumask_bits(retmask)[0] = APIC_ALL_CPUS; 349} 350 351#ifdef CONFIG_X86_SUMMIT_NUMA 352static struct rio_table_hdr *rio_table_hdr; 353static struct scal_detail *scal_devs[MAX_NUMNODES]; 354static struct rio_detail *rio_devs[MAX_NUMNODES*4]; 355 356#ifndef CONFIG_X86_NUMAQ 357static int mp_bus_id_to_node[MAX_MP_BUSSES]; 358#endif 359 360static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus) 361{ 362 int twister = 0, node = 0; 363 int i, bus, num_buses; 364 365 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) { 366 if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) { 367 twister = rio_devs[i]->owner_id; 368 break; 369 } 370 } 371 if (i == rio_table_hdr->num_rio_dev) { 372 printk(KERN_ERR "%s: Couldn't find owner Cyclone for Winnipeg!\n", __func__); 373 return last_bus; 374 } 375 376 for (i = 0; i < rio_table_hdr->num_scal_dev; i++) { 377 if (scal_devs[i]->node_id == twister) { 378 node = scal_devs[i]->node_id; 379 break; 380 } 381 } 382 if (i == rio_table_hdr->num_scal_dev) { 383 printk(KERN_ERR "%s: Couldn't find owner Twister for Cyclone!\n", __func__); 384 return last_bus; 385 } 386 387 switch (rio_devs[wpeg_num]->type) { 388 case CompatWPEG: 389 /* 390 * The Compatibility Winnipeg controls the 2 legacy buses, 391 * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case 392 * a PCI-PCI bridge card is used in either slot: total 5 buses. 393 */ 394 num_buses = 5; 395 break; 396 case AltWPEG: 397 /* 398 * The Alternate Winnipeg controls the 2 133MHz buses [1 slot 399 * each], their 2 "extra" buses, the 100MHz bus [2 slots] and 400 * the "extra" buses for each of those slots: total 7 buses. 401 */ 402 num_buses = 7; 403 break; 404 case LookOutAWPEG: 405 case LookOutBWPEG: 406 /* 407 * A Lookout Winnipeg controls 3 100MHz buses [2 slots each] 408 * & the "extra" buses for each of those slots: total 9 buses. 409 */ 410 num_buses = 9; 411 break; 412 default: 413 printk(KERN_INFO "%s: Unsupported Winnipeg type!\n", __func__); 414 return last_bus; 415 } 416 417 for (bus = last_bus; bus < last_bus + num_buses; bus++) 418 mp_bus_id_to_node[bus] = node; 419 return bus; 420} 421 422static int build_detail_arrays(void) 423{ 424 unsigned long ptr; 425 int i, scal_detail_size, rio_detail_size; 426 427 if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) { 428 printk(KERN_WARNING "%s: MAX_NUMNODES too low! Defined as %d, but system has %d nodes.\n", __func__, MAX_NUMNODES, rio_table_hdr->num_scal_dev); 429 return 0; 430 } 431 432 switch (rio_table_hdr->version) { 433 default: 434 printk(KERN_WARNING "%s: Invalid Rio Grande Table Version: %d\n", __func__, rio_table_hdr->version); 435 return 0; 436 case 2: 437 scal_detail_size = 11; 438 rio_detail_size = 13; 439 break; 440 case 3: 441 scal_detail_size = 12; 442 rio_detail_size = 15; 443 break; 444 } 445 446 ptr = (unsigned long)rio_table_hdr + 3; 447 for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size) 448 scal_devs[i] = (struct scal_detail *)ptr; 449 450 for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size) 451 rio_devs[i] = (struct rio_detail *)ptr; 452 453 return 1; 454} 455 456void setup_summit(void) 457{ 458 unsigned long ptr; 459 unsigned short offset; 460 int i, next_wpeg, next_bus = 0; 461 462 /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */ 463 ptr = get_bios_ebda(); 464 ptr = (unsigned long)phys_to_virt(ptr); 465 466 rio_table_hdr = NULL; 467 offset = 0x180; 468 while (offset) { 469 /* The block id is stored in the 2nd word */ 470 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) { 471 /* set the pointer past the offset & block id */ 472 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); 473 break; 474 } 475 /* The next offset is stored in the 1st word. 0 means no more */ 476 offset = *((unsigned short *)(ptr + offset)); 477 } 478 if (!rio_table_hdr) { 479 printk(KERN_ERR "%s: Unable to locate Rio Grande Table in EBDA - bailing!\n", __func__); 480 return; 481 } 482 483 if (!build_detail_arrays()) 484 return; 485 486 /* The first Winnipeg we're looking for has an index of 0 */ 487 next_wpeg = 0; 488 do { 489 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) { 490 if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) { 491 /* It's the Winnipeg we're looking for! */ 492 next_bus = setup_pci_node_map_for_wpeg(i, next_bus); 493 next_wpeg++; 494 break; 495 } 496 } 497 /* 498 * If we go through all Rio devices and don't find one with 499 * the next index, it means we've found all the Winnipegs, 500 * and thus all the PCI buses. 501 */ 502 if (i == rio_table_hdr->num_rio_dev) 503 next_wpeg = 0; 504 } while (next_wpeg != 0); 505} 506#endif 507 508struct apic apic_summit = { 509 510 .name = "summit", 511 .probe = probe_summit, 512 .acpi_madt_oem_check = summit_acpi_madt_oem_check, 513 .apic_id_registered = summit_apic_id_registered, 514 515 .irq_delivery_mode = dest_LowestPrio, 516 /* logical delivery broadcast to all CPUs: */ 517 .irq_dest_mode = 1, 518 519 .target_cpus = summit_target_cpus, 520 .disable_esr = 1, 521 .dest_logical = APIC_DEST_LOGICAL, 522 .check_apicid_used = summit_check_apicid_used, 523 .check_apicid_present = summit_check_apicid_present, 524 525 .vector_allocation_domain = summit_vector_allocation_domain, 526 .init_apic_ldr = summit_init_apic_ldr, 527 528 .ioapic_phys_id_map = summit_ioapic_phys_id_map, 529 .setup_apic_routing = summit_setup_apic_routing, 530 .multi_timer_check = NULL, 531 .apicid_to_node = summit_apicid_to_node, 532 .cpu_to_logical_apicid = summit_cpu_to_logical_apicid, 533 .cpu_present_to_apicid = summit_cpu_present_to_apicid, 534 .apicid_to_cpu_present = summit_apicid_to_cpu_present, 535 .setup_portio_remap = NULL, 536 .check_phys_apicid_present = summit_check_phys_apicid_present, 537 .enable_apic_mode = NULL, 538 .phys_pkg_id = summit_phys_pkg_id, 539 .mps_oem_check = summit_mps_oem_check, 540 541 .get_apic_id = summit_get_apic_id, 542 .set_apic_id = NULL, 543 .apic_id_mask = 0xFF << 24, 544 545 .cpu_mask_to_apicid = summit_cpu_mask_to_apicid, 546 .cpu_mask_to_apicid_and = summit_cpu_mask_to_apicid_and, 547 548 .send_IPI_mask = summit_send_IPI_mask, 549 .send_IPI_mask_allbutself = NULL, 550 .send_IPI_allbutself = summit_send_IPI_allbutself, 551 .send_IPI_all = summit_send_IPI_all, 552 .send_IPI_self = default_send_IPI_self, 553 554 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, 555 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, 556 557 .wait_for_init_deassert = default_wait_for_init_deassert, 558 559 .smp_callin_clear_local_apic = NULL, 560 .inquire_remote_apic = default_inquire_remote_apic, 561 562 .read = native_apic_mem_read, 563 .write = native_apic_mem_write, 564 .icr_read = native_apic_icr_read, 565 .icr_write = native_apic_icr_write, 566 .wait_icr_idle = native_apic_wait_icr_idle, 567 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, 568}; 569