1/* 2 * Shared SH3 Setup code 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11#include <linux/init.h> 12#include <linux/irq.h> 13#include <linux/io.h> 14 15/* All SH3 devices are equipped with IRQ0->5 (except sh7708) */ 16 17enum { 18 UNUSED = 0, 19 20 /* interrupt sources */ 21 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 22}; 23 24static struct intc_vect vectors_irq0123[] __initdata = { 25 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 26 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 27}; 28 29static struct intc_vect vectors_irq45[] __initdata = { 30 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 31}; 32 33static struct intc_prio_reg prio_registers[] __initdata = { 34 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 35 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 36}; 37 38static struct intc_mask_reg ack_registers[] __initdata = { 39 { 0xa4000004, 0, 8, /* IRR0 */ 40 { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } }, 41}; 42 43static struct intc_sense_reg sense_registers[] __initdata = { 44 { 0xa4000010, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } }, 45}; 46 47static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh3-irq0123", 48 vectors_irq0123, NULL, NULL, 49 prio_registers, sense_registers, ack_registers); 50 51static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45", 52 vectors_irq45, NULL, NULL, 53 prio_registers, sense_registers, ack_registers); 54 55#define INTC_ICR1 0xa4000010UL 56#define INTC_ICR1_IRQLVL (1<<14) 57 58void __init plat_irq_setup_pins(int mode) 59{ 60 if (mode == IRQ_MODE_IRQ) { 61 __raw_writew(__raw_readw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1); 62 register_intc_controller(&intc_desc_irq0123); 63 return; 64 } 65 BUG(); 66} 67 68void __init plat_irq_setup_sh3(void) 69{ 70 register_intc_controller(&intc_desc_irq45); 71} 72