• Home
  • History
  • Annotate
  • Line#
  • Navigate
  • Raw
  • Download
  • only in /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/include/mach-common/mach/
1/*
2 *  include/asm-sh/magicpanelr2.h
3 *
4 *  Copyright (C) 2007  Markus Brunner, Mark Jonas
5 *
6 *  I/O addresses and bitmasks for Magic Panel Release 2 board
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License.  See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#ifndef __ASM_SH_MAGICPANELR2_H
14#define __ASM_SH_MAGICPANELR2_H
15
16#include <asm/gpio.h>
17
18#define __IO_PREFIX mpr2
19#include <asm/io_generic.h>
20
21
22#define SETBITS_OUTB(mask, reg)   __raw_writeb(__raw_readb(reg) | mask, reg)
23#define SETBITS_OUTW(mask, reg)   __raw_writew(__raw_readw(reg) | mask, reg)
24#define SETBITS_OUTL(mask, reg)   __raw_writel(__raw_readl(reg) | mask, reg)
25#define CLRBITS_OUTB(mask, reg)   __raw_writeb(__raw_readb(reg) & ~mask, reg)
26#define CLRBITS_OUTW(mask, reg)   __raw_writew(__raw_readw(reg) & ~mask, reg)
27#define CLRBITS_OUTL(mask, reg)   __raw_writel(__raw_readl(reg) & ~mask, reg)
28
29
30#define PA_LED          PORT_PADR      /* LED */
31
32
33/* BSC */
34#define CMNCR           0xA4FD0000UL
35#define CS0BCR          0xA4FD0004UL
36#define CS2BCR          0xA4FD0008UL
37#define CS3BCR          0xA4FD000CUL
38#define CS4BCR          0xA4FD0010UL
39#define CS5ABCR         0xA4FD0014UL
40#define CS5BBCR         0xA4FD0018UL
41#define CS6ABCR         0xA4FD001CUL
42#define CS6BBCR         0xA4FD0020UL
43#define CS0WCR          0xA4FD0024UL
44#define CS2WCR          0xA4FD0028UL
45#define CS3WCR          0xA4FD002CUL
46#define CS4WCR          0xA4FD0030UL
47#define CS5AWCR         0xA4FD0034UL
48#define CS5BWCR         0xA4FD0038UL
49#define CS6AWCR         0xA4FD003CUL
50#define CS6BWCR         0xA4FD0040UL
51
52
53/* usb */
54
55#define PORT_UTRCTL		0xA405012CUL
56#define PORT_UCLKCR_W		0xA40A0008UL
57
58#define INTC_ICR0		0xA414FEE0UL
59#define INTC_ICR1		0xA4140010UL
60#define INTC_ICR2		0xA4140012UL
61
62/* MTD */
63
64#define MPR2_MTD_BOOTLOADER_SIZE	0x00060000UL
65#define MPR2_MTD_KERNEL_SIZE		0x00200000UL
66
67#endif  /* __ASM_SH_MAGICPANELR2_H */
68