1#ifndef __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H 3 4#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 5 defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 6#define SH_DMAC_BASE0 0xa4010020 7#else /* SH7705/06/07/09 */ 8#define SH_DMAC_BASE0 0xa4000020 9#endif 10 11#define DMTE0_IRQ 48 12#define DMTE4_IRQ 76 13 14/* Definitions for the SuperH DMAC */ 15#define TM_BURST 0x00000020 16#define TS_8 0x00000000 17#define TS_16 0x00000008 18#define TS_32 0x00000010 19#define TS_128 0x00000018 20 21#endif /* __ASM_CPU_SH3_DMA_H */ 22