1/* 2 * arch/sh/include/asm/dma-sh.h 3 * 4 * Copyright (C) 2000 Takashi YOSHII 5 * Copyright (C) 2003 Paul Mundt 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11#ifndef __DMA_SH_H 12#define __DMA_SH_H 13 14#include <asm/dma-register.h> 15#include <cpu/dma-register.h> 16#include <cpu/dma.h> 17 18/* DMAOR contorl: The DMAOR access size is different by CPU.*/ 19#if defined(CONFIG_CPU_SUBTYPE_SH7723) || defined(CONFIG_CPU_SUBTYPE_SH7724) || \ 20 defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785) 21#define dmaor_read_reg(n) \ 22 (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \ 23 : __raw_readw(SH_DMAC_BASE0 + DMAOR)) 24#define dmaor_write_reg(n, data) \ 25 (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \ 26 : __raw_writew(data, SH_DMAC_BASE0 + DMAOR)) 27#else /* Other CPU */ 28#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR) 29#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR) 30#endif 31 32static int dmte_irq_map[] __maybe_unused = { 33#if (MAX_DMA_CHANNELS >= 4) 34 DMTE0_IRQ, 35 DMTE0_IRQ + 1, 36 DMTE0_IRQ + 2, 37 DMTE0_IRQ + 3, 38#endif 39#if (MAX_DMA_CHANNELS >= 6) 40 DMTE4_IRQ, 41 DMTE4_IRQ + 1, 42#endif 43#if (MAX_DMA_CHANNELS >= 8) 44 DMTE6_IRQ, 45 DMTE6_IRQ + 1, 46#endif 47#if (MAX_DMA_CHANNELS >= 12) 48 DMTE8_IRQ, 49 DMTE9_IRQ, 50 DMTE10_IRQ, 51 DMTE11_IRQ, 52#endif 53}; 54 55/* 56 * Define the default configuration for dual address memory-memory transfer. 57 * The 0x400 value represents auto-request, external->external. 58 */ 59#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT)) 60 61/* DMA base address */ 62static u32 dma_base_addr[] __maybe_unused = { 63#if (MAX_DMA_CHANNELS >= 4) 64 SH_DMAC_BASE0 + 0x00, /* channel 0 */ 65 SH_DMAC_BASE0 + 0x10, 66 SH_DMAC_BASE0 + 0x20, 67 SH_DMAC_BASE0 + 0x30, 68#endif 69#if (MAX_DMA_CHANNELS >= 6) 70 SH_DMAC_BASE0 + 0x50, 71 SH_DMAC_BASE0 + 0x60, 72#endif 73#if (MAX_DMA_CHANNELS >= 8) 74 SH_DMAC_BASE1 + 0x00, 75 SH_DMAC_BASE1 + 0x10, 76#endif 77#if (MAX_DMA_CHANNELS >= 12) 78 SH_DMAC_BASE1 + 0x20, 79 SH_DMAC_BASE1 + 0x30, 80 SH_DMAC_BASE1 + 0x50, 81 SH_DMAC_BASE1 + 0x60, /* channel 11 */ 82#endif 83}; 84 85#endif /* __DMA_SH_H */ 86