1/* 2 * arch/powerpc/sysdev/dart_iommu.c 3 * 4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 5 * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, 6 * IBM Corporation 7 * 8 * Based on pSeries_iommu.c: 9 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 10 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 11 * 12 * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. 13 * 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30#include <linux/init.h> 31#include <linux/types.h> 32#include <linux/mm.h> 33#include <linux/spinlock.h> 34#include <linux/string.h> 35#include <linux/pci.h> 36#include <linux/dma-mapping.h> 37#include <linux/vmalloc.h> 38#include <linux/suspend.h> 39#include <linux/memblock.h> 40#include <linux/gfp.h> 41#include <asm/io.h> 42#include <asm/prom.h> 43#include <asm/iommu.h> 44#include <asm/pci-bridge.h> 45#include <asm/machdep.h> 46#include <asm/abs_addr.h> 47#include <asm/cacheflush.h> 48#include <asm/ppc-pci.h> 49 50#include "dart.h" 51 52/* Physical base address and size of the DART table */ 53unsigned long dart_tablebase; /* exported to htab_initialize */ 54static unsigned long dart_tablesize; 55 56/* Virtual base address of the DART table */ 57static u32 *dart_vbase; 58#ifdef CONFIG_PM 59static u32 *dart_copy; 60#endif 61 62/* Mapped base address for the dart */ 63static unsigned int __iomem *dart; 64 65/* Dummy val that entries are set to when unused */ 66static unsigned int dart_emptyval; 67 68static struct iommu_table iommu_table_dart; 69static int iommu_table_dart_inited; 70static int dart_dirty; 71static int dart_is_u4; 72 73#define DBG(...) 74 75static inline void dart_tlb_invalidate_all(void) 76{ 77 unsigned long l = 0; 78 unsigned int reg, inv_bit; 79 unsigned long limit; 80 81 DBG("dart: flush\n"); 82 83 /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the 84 * control register and wait for it to clear. 85 * 86 * Gotcha: Sometimes, the DART won't detect that the bit gets 87 * set. If so, clear it and set it again. 88 */ 89 90 limit = 0; 91 92 inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; 93retry: 94 l = 0; 95 reg = DART_IN(DART_CNTL); 96 reg |= inv_bit; 97 DART_OUT(DART_CNTL, reg); 98 99 while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) 100 l++; 101 if (l == (1L << limit)) { 102 if (limit < 4) { 103 limit++; 104 reg = DART_IN(DART_CNTL); 105 reg &= ~inv_bit; 106 DART_OUT(DART_CNTL, reg); 107 goto retry; 108 } else 109 panic("DART: TLB did not flush after waiting a long " 110 "time. Buggy U3 ?"); 111 } 112} 113 114static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) 115{ 116 unsigned int reg; 117 unsigned int l, limit; 118 119 reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | 120 (bus_rpn & DART_CNTL_U4_IONE_MASK); 121 DART_OUT(DART_CNTL, reg); 122 123 limit = 0; 124wait_more: 125 l = 0; 126 while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { 127 rmb(); 128 l++; 129 } 130 131 if (l == (1L << limit)) { 132 if (limit < 4) { 133 limit++; 134 goto wait_more; 135 } else 136 panic("DART: TLB did not flush after waiting a long " 137 "time. Buggy U4 ?"); 138 } 139} 140 141static void dart_flush(struct iommu_table *tbl) 142{ 143 mb(); 144 if (dart_dirty) { 145 dart_tlb_invalidate_all(); 146 dart_dirty = 0; 147 } 148} 149 150static int dart_build(struct iommu_table *tbl, long index, 151 long npages, unsigned long uaddr, 152 enum dma_data_direction direction, 153 struct dma_attrs *attrs) 154{ 155 unsigned int *dp; 156 unsigned int rpn; 157 long l; 158 159 DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); 160 161 dp = ((unsigned int*)tbl->it_base) + index; 162 163 /* On U3, all memory is contiguous, so we can move this 164 * out of the loop. 165 */ 166 l = npages; 167 while (l--) { 168 rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT; 169 170 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); 171 172 uaddr += DART_PAGE_SIZE; 173 } 174 175 /* make sure all updates have reached memory */ 176 mb(); 177 in_be32((unsigned __iomem *)dp); 178 mb(); 179 180 if (dart_is_u4) { 181 rpn = index; 182 while (npages--) 183 dart_tlb_invalidate_one(rpn++); 184 } else { 185 dart_dirty = 1; 186 } 187 return 0; 188} 189 190 191static void dart_free(struct iommu_table *tbl, long index, long npages) 192{ 193 unsigned int *dp; 194 195 /* We don't worry about flushing the TLB cache. The only drawback of 196 * not doing it is that we won't catch buggy device drivers doing 197 * bad DMAs, but then no 32-bit architecture ever does either. 198 */ 199 200 DBG("dart: free at: %lx, %lx\n", index, npages); 201 202 dp = ((unsigned int *)tbl->it_base) + index; 203 204 while (npages--) 205 *(dp++) = dart_emptyval; 206} 207 208 209static int __init dart_init(struct device_node *dart_node) 210{ 211 unsigned int i; 212 unsigned long tmp, base, size; 213 struct resource r; 214 215 if (dart_tablebase == 0 || dart_tablesize == 0) { 216 printk(KERN_INFO "DART: table not allocated, using " 217 "direct DMA\n"); 218 return -ENODEV; 219 } 220 221 if (of_address_to_resource(dart_node, 0, &r)) 222 panic("DART: can't get register base ! "); 223 224 /* Make sure nothing from the DART range remains in the CPU cache 225 * from a previous mapping that existed before the kernel took 226 * over 227 */ 228 flush_dcache_phys_range(dart_tablebase, 229 dart_tablebase + dart_tablesize); 230 231 tmp = memblock_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); 232 dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & 233 DARTMAP_RPNMASK); 234 235 /* Map in DART registers */ 236 dart = ioremap(r.start, r.end - r.start + 1); 237 if (dart == NULL) 238 panic("DART: Cannot map registers!"); 239 240 /* Map in DART table */ 241 dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize); 242 243 /* Fill initial table */ 244 for (i = 0; i < dart_tablesize/4; i++) 245 dart_vbase[i] = dart_emptyval; 246 247 /* Initialize DART with table base and enable it. */ 248 base = dart_tablebase >> DART_PAGE_SHIFT; 249 size = dart_tablesize >> DART_PAGE_SHIFT; 250 if (dart_is_u4) { 251 size &= DART_SIZE_U4_SIZE_MASK; 252 DART_OUT(DART_BASE_U4, base); 253 DART_OUT(DART_SIZE_U4, size); 254 DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); 255 } else { 256 size &= DART_CNTL_U3_SIZE_MASK; 257 DART_OUT(DART_CNTL, 258 DART_CNTL_U3_ENABLE | 259 (base << DART_CNTL_U3_BASE_SHIFT) | 260 (size << DART_CNTL_U3_SIZE_SHIFT)); 261 } 262 263 /* Invalidate DART to get rid of possible stale TLBs */ 264 dart_tlb_invalidate_all(); 265 266 printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", 267 dart_is_u4 ? "U4" : "U3"); 268 269 return 0; 270} 271 272static void iommu_table_dart_setup(void) 273{ 274 iommu_table_dart.it_busno = 0; 275 iommu_table_dart.it_offset = 0; 276 /* it_size is in number of entries */ 277 iommu_table_dart.it_size = dart_tablesize / sizeof(u32); 278 279 /* Initialize the common IOMMU code */ 280 iommu_table_dart.it_base = (unsigned long)dart_vbase; 281 iommu_table_dart.it_index = 0; 282 iommu_table_dart.it_blocksize = 1; 283 iommu_init_table(&iommu_table_dart, -1); 284 285 /* Reserve the last page of the DART to avoid possible prefetch 286 * past the DART mapped area 287 */ 288 set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); 289} 290 291static void pci_dma_dev_setup_dart(struct pci_dev *dev) 292{ 293 /* We only have one iommu table on the mac for now, which makes 294 * things simple. Setup all PCI devices to point to this table 295 */ 296 set_iommu_table_base(&dev->dev, &iommu_table_dart); 297} 298 299static void pci_dma_bus_setup_dart(struct pci_bus *bus) 300{ 301 struct device_node *dn; 302 303 if (!iommu_table_dart_inited) { 304 iommu_table_dart_inited = 1; 305 iommu_table_dart_setup(); 306 } 307 308 dn = pci_bus_to_OF_node(bus); 309 310 if (dn) 311 PCI_DN(dn)->iommu_table = &iommu_table_dart; 312} 313 314void __init iommu_init_early_dart(void) 315{ 316 struct device_node *dn; 317 318 /* Find the DART in the device-tree */ 319 dn = of_find_compatible_node(NULL, "dart", "u3-dart"); 320 if (dn == NULL) { 321 dn = of_find_compatible_node(NULL, "dart", "u4-dart"); 322 if (dn == NULL) 323 goto bail; 324 dart_is_u4 = 1; 325 } 326 327 /* Setup low level TCE operations for the core IOMMU code */ 328 ppc_md.tce_build = dart_build; 329 ppc_md.tce_free = dart_free; 330 ppc_md.tce_flush = dart_flush; 331 332 /* Initialize the DART HW */ 333 if (dart_init(dn) == 0) { 334 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart; 335 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart; 336 337 /* Setup pci_dma ops */ 338 set_pci_dma_ops(&dma_iommu_ops); 339 return; 340 } 341 342 bail: 343 /* If init failed, use direct iommu and null setup functions */ 344 ppc_md.pci_dma_dev_setup = NULL; 345 ppc_md.pci_dma_bus_setup = NULL; 346 347 /* Setup pci_dma ops */ 348 set_pci_dma_ops(&dma_direct_ops); 349} 350 351#ifdef CONFIG_PM 352static void iommu_dart_save(void) 353{ 354 memcpy(dart_copy, dart_vbase, 2*1024*1024); 355} 356 357static void iommu_dart_restore(void) 358{ 359 memcpy(dart_vbase, dart_copy, 2*1024*1024); 360 dart_tlb_invalidate_all(); 361} 362 363static int __init iommu_init_late_dart(void) 364{ 365 unsigned long tbasepfn; 366 struct page *p; 367 368 /* if no dart table exists then we won't need to save it 369 * and the area has also not been reserved */ 370 if (!dart_tablebase) 371 return 0; 372 373 tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT; 374 register_nosave_region_late(tbasepfn, 375 tbasepfn + ((1<<24) >> PAGE_SHIFT)); 376 377 /* For suspend we need to copy the dart contents because 378 * it is not part of the regular mapping (see above) and 379 * thus not saved automatically. The memory for this copy 380 * must be allocated early because we need 2 MB. */ 381 p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT); 382 BUG_ON(!p); 383 dart_copy = page_address(p); 384 385 ppc_md.iommu_save = iommu_dart_save; 386 ppc_md.iommu_restore = iommu_dart_restore; 387 388 return 0; 389} 390 391late_initcall(iommu_init_late_dart); 392#endif 393 394void __init alloc_dart_table(void) 395{ 396 /* Only reserve DART space if machine has more than 1GB of RAM 397 * or if requested with iommu=on on cmdline. 398 * 399 * 1GB of RAM is picked as limit because some default devices 400 * (i.e. Airport Extreme) have 30 bit address range limits. 401 */ 402 403 if (iommu_is_off) 404 return; 405 406 if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull) 407 return; 408 409 /* 512 pages (2MB) is max DART tablesize. */ 410 dart_tablesize = 1UL << 21; 411 /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we 412 * will blow up an entire large page anyway in the kernel mapping 413 */ 414 dart_tablebase = (unsigned long) 415 abs_to_virt(memblock_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); 416 417 printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase); 418} 419