1/* 2 * Support for the interrupt controllers found on Power Macintosh, 3 * currently Apple's "Grand Central" interrupt controller in all 4 * it's incarnations. OpenPIC support used on newer machines is 5 * in a separate file 6 * 7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org) 9 * IBM, Corp. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 * 16 */ 17 18#include <linux/stddef.h> 19#include <linux/init.h> 20#include <linux/sched.h> 21#include <linux/signal.h> 22#include <linux/pci.h> 23#include <linux/interrupt.h> 24#include <linux/sysdev.h> 25#include <linux/adb.h> 26#include <linux/pmu.h> 27#include <linux/module.h> 28 29#include <asm/sections.h> 30#include <asm/io.h> 31#include <asm/smp.h> 32#include <asm/prom.h> 33#include <asm/pci-bridge.h> 34#include <asm/time.h> 35#include <asm/pmac_feature.h> 36#include <asm/mpic.h> 37#include <asm/xmon.h> 38 39#include "pmac.h" 40 41#ifdef CONFIG_PPC32 42struct pmac_irq_hw { 43 unsigned int event; 44 unsigned int enable; 45 unsigned int ack; 46 unsigned int level; 47}; 48 49unsigned int of_irq_workarounds; 50struct device_node *of_irq_dflt_pic; 51 52/* Default addresses */ 53static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; 54 55#define GC_LEVEL_MASK 0x3ff00000 56#define OHARE_LEVEL_MASK 0x1ff00000 57#define HEATHROW_LEVEL_MASK 0x1ff00000 58 59static int max_irqs; 60static int max_real_irqs; 61static u32 level_mask[4]; 62 63static DEFINE_RAW_SPINLOCK(pmac_pic_lock); 64 65#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) 66static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; 67static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; 68static int pmac_irq_cascade = -1; 69static struct irq_host *pmac_pic_host; 70 71static void __pmac_retrigger(unsigned int irq_nr) 72{ 73 if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) { 74 __set_bit(irq_nr, ppc_lost_interrupts); 75 irq_nr = pmac_irq_cascade; 76 mb(); 77 } 78 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) { 79 atomic_inc(&ppc_n_lost_interrupts); 80 set_dec(1); 81 } 82} 83 84static void pmac_mask_and_ack_irq(unsigned int virq) 85{ 86 unsigned int src = irq_map[virq].hwirq; 87 unsigned long bit = 1UL << (src & 0x1f); 88 int i = src >> 5; 89 unsigned long flags; 90 91 raw_spin_lock_irqsave(&pmac_pic_lock, flags); 92 __clear_bit(src, ppc_cached_irq_mask); 93 if (__test_and_clear_bit(src, ppc_lost_interrupts)) 94 atomic_dec(&ppc_n_lost_interrupts); 95 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); 96 out_le32(&pmac_irq_hw[i]->ack, bit); 97 do { 98 /* make sure ack gets to controller before we enable 99 interrupts */ 100 mb(); 101 } while((in_le32(&pmac_irq_hw[i]->enable) & bit) 102 != (ppc_cached_irq_mask[i] & bit)); 103 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); 104} 105 106static void pmac_ack_irq(unsigned int virq) 107{ 108 unsigned int src = irq_map[virq].hwirq; 109 unsigned long bit = 1UL << (src & 0x1f); 110 int i = src >> 5; 111 unsigned long flags; 112 113 raw_spin_lock_irqsave(&pmac_pic_lock, flags); 114 if (__test_and_clear_bit(src, ppc_lost_interrupts)) 115 atomic_dec(&ppc_n_lost_interrupts); 116 out_le32(&pmac_irq_hw[i]->ack, bit); 117 (void)in_le32(&pmac_irq_hw[i]->ack); 118 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); 119} 120 121static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) 122{ 123 unsigned long bit = 1UL << (irq_nr & 0x1f); 124 int i = irq_nr >> 5; 125 126 if ((unsigned)irq_nr >= max_irqs) 127 return; 128 129 /* enable unmasked interrupts */ 130 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); 131 132 do { 133 /* make sure mask gets to controller before we 134 return to user */ 135 mb(); 136 } while((in_le32(&pmac_irq_hw[i]->enable) & bit) 137 != (ppc_cached_irq_mask[i] & bit)); 138 139 /* 140 * Unfortunately, setting the bit in the enable register 141 * when the device interrupt is already on *doesn't* set 142 * the bit in the flag register or request another interrupt. 143 */ 144 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) 145 __pmac_retrigger(irq_nr); 146} 147 148/* When an irq gets requested for the first client, if it's an 149 * edge interrupt, we clear any previous one on the controller 150 */ 151static unsigned int pmac_startup_irq(unsigned int virq) 152{ 153 unsigned long flags; 154 unsigned int src = irq_map[virq].hwirq; 155 unsigned long bit = 1UL << (src & 0x1f); 156 int i = src >> 5; 157 158 raw_spin_lock_irqsave(&pmac_pic_lock, flags); 159 if ((irq_to_desc(virq)->status & IRQ_LEVEL) == 0) 160 out_le32(&pmac_irq_hw[i]->ack, bit); 161 __set_bit(src, ppc_cached_irq_mask); 162 __pmac_set_irq_mask(src, 0); 163 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); 164 165 return 0; 166} 167 168static void pmac_mask_irq(unsigned int virq) 169{ 170 unsigned long flags; 171 unsigned int src = irq_map[virq].hwirq; 172 173 raw_spin_lock_irqsave(&pmac_pic_lock, flags); 174 __clear_bit(src, ppc_cached_irq_mask); 175 __pmac_set_irq_mask(src, 1); 176 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); 177} 178 179static void pmac_unmask_irq(unsigned int virq) 180{ 181 unsigned long flags; 182 unsigned int src = irq_map[virq].hwirq; 183 184 raw_spin_lock_irqsave(&pmac_pic_lock, flags); 185 __set_bit(src, ppc_cached_irq_mask); 186 __pmac_set_irq_mask(src, 0); 187 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); 188} 189 190static int pmac_retrigger(unsigned int virq) 191{ 192 unsigned long flags; 193 194 raw_spin_lock_irqsave(&pmac_pic_lock, flags); 195 __pmac_retrigger(irq_map[virq].hwirq); 196 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); 197 return 1; 198} 199 200static struct irq_chip pmac_pic = { 201 .name = "PMAC-PIC", 202 .startup = pmac_startup_irq, 203 .mask = pmac_mask_irq, 204 .ack = pmac_ack_irq, 205 .mask_ack = pmac_mask_and_ack_irq, 206 .unmask = pmac_unmask_irq, 207 .retrigger = pmac_retrigger, 208}; 209 210static irqreturn_t gatwick_action(int cpl, void *dev_id) 211{ 212 unsigned long flags; 213 int irq, bits; 214 int rc = IRQ_NONE; 215 216 raw_spin_lock_irqsave(&pmac_pic_lock, flags); 217 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { 218 int i = irq >> 5; 219 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; 220 /* We must read level interrupts from the level register */ 221 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); 222 bits &= ppc_cached_irq_mask[i]; 223 if (bits == 0) 224 continue; 225 irq += __ilog2(bits); 226 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); 227 generic_handle_irq(irq); 228 raw_spin_lock_irqsave(&pmac_pic_lock, flags); 229 rc = IRQ_HANDLED; 230 } 231 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); 232 return rc; 233} 234 235static unsigned int pmac_pic_get_irq(void) 236{ 237 int irq; 238 unsigned long bits = 0; 239 unsigned long flags; 240 241#ifdef CONFIG_SMP 242 void psurge_smp_message_recv(void); 243 244 /* IPI's are a hack on the powersurge -- Cort */ 245 if ( smp_processor_id() != 0 ) { 246 psurge_smp_message_recv(); 247 return NO_IRQ_IGNORE; /* ignore, already handled */ 248 } 249#endif /* CONFIG_SMP */ 250 raw_spin_lock_irqsave(&pmac_pic_lock, flags); 251 for (irq = max_real_irqs; (irq -= 32) >= 0; ) { 252 int i = irq >> 5; 253 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; 254 /* We must read level interrupts from the level register */ 255 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); 256 bits &= ppc_cached_irq_mask[i]; 257 if (bits == 0) 258 continue; 259 irq += __ilog2(bits); 260 break; 261 } 262 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); 263 if (unlikely(irq < 0)) 264 return NO_IRQ; 265 return irq_linear_revmap(pmac_pic_host, irq); 266} 267 268#ifdef CONFIG_XMON 269static struct irqaction xmon_action = { 270 .handler = xmon_irq, 271 .flags = 0, 272 .name = "NMI - XMON" 273}; 274#endif 275 276static struct irqaction gatwick_cascade_action = { 277 .handler = gatwick_action, 278 .flags = IRQF_DISABLED, 279 .name = "cascade", 280}; 281 282static int pmac_pic_host_match(struct irq_host *h, struct device_node *node) 283{ 284 /* We match all, we don't always have a node anyway */ 285 return 1; 286} 287 288static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, 289 irq_hw_number_t hw) 290{ 291 struct irq_desc *desc = irq_to_desc(virq); 292 int level; 293 294 if (hw >= max_irqs) 295 return -EINVAL; 296 297 /* Mark level interrupts, set delayed disable for edge ones and set 298 * handlers 299 */ 300 level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); 301 if (level) 302 desc->status |= IRQ_LEVEL; 303 set_irq_chip_and_handler(virq, &pmac_pic, level ? 304 handle_level_irq : handle_edge_irq); 305 return 0; 306} 307 308static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct, 309 const u32 *intspec, unsigned int intsize, 310 irq_hw_number_t *out_hwirq, 311 unsigned int *out_flags) 312 313{ 314 *out_flags = IRQ_TYPE_NONE; 315 *out_hwirq = *intspec; 316 return 0; 317} 318 319static struct irq_host_ops pmac_pic_host_ops = { 320 .match = pmac_pic_host_match, 321 .map = pmac_pic_host_map, 322 .xlate = pmac_pic_host_xlate, 323}; 324 325static void __init pmac_pic_probe_oldstyle(void) 326{ 327 int i; 328 struct device_node *master = NULL; 329 struct device_node *slave = NULL; 330 u8 __iomem *addr; 331 struct resource r; 332 333 /* Set our get_irq function */ 334 ppc_md.get_irq = pmac_pic_get_irq; 335 336 /* 337 * Find the interrupt controller type & node 338 */ 339 340 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { 341 max_irqs = max_real_irqs = 32; 342 level_mask[0] = GC_LEVEL_MASK; 343 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { 344 max_irqs = max_real_irqs = 32; 345 level_mask[0] = OHARE_LEVEL_MASK; 346 347 /* We might have a second cascaded ohare */ 348 slave = of_find_node_by_name(NULL, "pci106b,7"); 349 if (slave) { 350 max_irqs = 64; 351 level_mask[1] = OHARE_LEVEL_MASK; 352 } 353 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { 354 max_irqs = max_real_irqs = 64; 355 level_mask[0] = HEATHROW_LEVEL_MASK; 356 level_mask[1] = 0; 357 358 /* We might have a second cascaded heathrow */ 359 slave = of_find_node_by_name(master, "mac-io"); 360 361 /* Check ordering of master & slave */ 362 if (of_device_is_compatible(master, "gatwick")) { 363 struct device_node *tmp; 364 BUG_ON(slave == NULL); 365 tmp = master; 366 master = slave; 367 slave = tmp; 368 } 369 370 /* We found a slave */ 371 if (slave) { 372 max_irqs = 128; 373 level_mask[2] = HEATHROW_LEVEL_MASK; 374 level_mask[3] = 0; 375 } 376 } 377 BUG_ON(master == NULL); 378 379 /* 380 * Allocate an irq host 381 */ 382 pmac_pic_host = irq_alloc_host(master, IRQ_HOST_MAP_LINEAR, max_irqs, 383 &pmac_pic_host_ops, 384 max_irqs); 385 BUG_ON(pmac_pic_host == NULL); 386 irq_set_default_host(pmac_pic_host); 387 388 /* Get addresses of first controller if we have a node for it */ 389 BUG_ON(of_address_to_resource(master, 0, &r)); 390 391 /* Map interrupts of primary controller */ 392 addr = (u8 __iomem *) ioremap(r.start, 0x40); 393 i = 0; 394 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) 395 (addr + 0x20); 396 if (max_real_irqs > 32) 397 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) 398 (addr + 0x10); 399 of_node_put(master); 400 401 printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n", 402 master->full_name, max_real_irqs); 403 404 /* Map interrupts of cascaded controller */ 405 if (slave && !of_address_to_resource(slave, 0, &r)) { 406 addr = (u8 __iomem *)ioremap(r.start, 0x40); 407 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) 408 (addr + 0x20); 409 if (max_irqs > 64) 410 pmac_irq_hw[i++] = 411 (volatile struct pmac_irq_hw __iomem *) 412 (addr + 0x10); 413 pmac_irq_cascade = irq_of_parse_and_map(slave, 0); 414 415 printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs" 416 " cascade: %d\n", slave->full_name, 417 max_irqs - max_real_irqs, pmac_irq_cascade); 418 } 419 of_node_put(slave); 420 421 /* Disable all interrupts in all controllers */ 422 for (i = 0; i * 32 < max_irqs; ++i) 423 out_le32(&pmac_irq_hw[i]->enable, 0); 424 425 /* Hookup cascade irq */ 426 if (slave && pmac_irq_cascade != NO_IRQ) 427 setup_irq(pmac_irq_cascade, &gatwick_cascade_action); 428 429 printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); 430#ifdef CONFIG_XMON 431 setup_irq(irq_create_mapping(NULL, 20), &xmon_action); 432#endif 433} 434 435int of_irq_map_oldworld(struct device_node *device, int index, 436 struct of_irq *out_irq) 437{ 438 const u32 *ints = NULL; 439 int intlen; 440 441 /* 442 * Old machines just have a list of interrupt numbers 443 * and no interrupt-controller nodes. We also have dodgy 444 * cases where the APPL,interrupts property is completely 445 * missing behind pci-pci bridges and we have to get it 446 * from the parent (the bridge itself, as apple just wired 447 * everything together on these) 448 */ 449 while (device) { 450 ints = of_get_property(device, "AAPL,interrupts", &intlen); 451 if (ints != NULL) 452 break; 453 device = device->parent; 454 if (device && strcmp(device->type, "pci") != 0) 455 break; 456 } 457 if (ints == NULL) 458 return -EINVAL; 459 intlen /= sizeof(u32); 460 461 if (index >= intlen) 462 return -EINVAL; 463 464 out_irq->controller = NULL; 465 out_irq->specifier[0] = ints[index]; 466 out_irq->size = 1; 467 468 return 0; 469} 470#endif /* CONFIG_PPC32 */ 471 472static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) 473{ 474 struct mpic *mpic = desc->handler_data; 475 476 unsigned int cascade_irq = mpic_get_one_irq(mpic); 477 if (cascade_irq != NO_IRQ) 478 generic_handle_irq(cascade_irq); 479 desc->chip->eoi(irq); 480} 481 482static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) 483{ 484#if defined(CONFIG_XMON) && defined(CONFIG_PPC32) 485 struct device_node* pswitch; 486 int nmi_irq; 487 488 pswitch = of_find_node_by_name(NULL, "programmer-switch"); 489 if (pswitch) { 490 nmi_irq = irq_of_parse_and_map(pswitch, 0); 491 if (nmi_irq != NO_IRQ) { 492 mpic_irq_set_priority(nmi_irq, 9); 493 setup_irq(nmi_irq, &xmon_action); 494 } 495 of_node_put(pswitch); 496 } 497#endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */ 498} 499 500static struct mpic * __init pmac_setup_one_mpic(struct device_node *np, 501 int master) 502{ 503 const char *name = master ? " MPIC 1 " : " MPIC 2 "; 504 struct resource r; 505 struct mpic *mpic; 506 unsigned int flags = master ? MPIC_PRIMARY : 0; 507 int rc; 508 509 rc = of_address_to_resource(np, 0, &r); 510 if (rc) 511 return NULL; 512 513 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); 514 515 flags |= MPIC_WANTS_RESET; 516 if (of_get_property(np, "big-endian", NULL)) 517 flags |= MPIC_BIG_ENDIAN; 518 519 /* Primary Big Endian means HT interrupts. This is quite dodgy 520 * but works until I find a better way 521 */ 522 if (master && (flags & MPIC_BIG_ENDIAN)) 523 flags |= MPIC_U3_HT_IRQS; 524 525 mpic = mpic_alloc(np, r.start, flags, 0, 0, name); 526 if (mpic == NULL) 527 return NULL; 528 529 mpic_init(mpic); 530 531 return mpic; 532 } 533 534static int __init pmac_pic_probe_mpic(void) 535{ 536 struct mpic *mpic1, *mpic2; 537 struct device_node *np, *master = NULL, *slave = NULL; 538 unsigned int cascade; 539 540 /* We can have up to 2 MPICs cascaded */ 541 for (np = NULL; (np = of_find_node_by_type(np, "open-pic")) 542 != NULL;) { 543 if (master == NULL && 544 of_get_property(np, "interrupts", NULL) == NULL) 545 master = of_node_get(np); 546 else if (slave == NULL) 547 slave = of_node_get(np); 548 if (master && slave) 549 break; 550 } 551 552 /* Check for bogus setups */ 553 if (master == NULL && slave != NULL) { 554 master = slave; 555 slave = NULL; 556 } 557 558 /* Not found, default to good old pmac pic */ 559 if (master == NULL) 560 return -ENODEV; 561 562 /* Set master handler */ 563 ppc_md.get_irq = mpic_get_irq; 564 565 /* Setup master */ 566 mpic1 = pmac_setup_one_mpic(master, 1); 567 BUG_ON(mpic1 == NULL); 568 569 /* Install NMI if any */ 570 pmac_pic_setup_mpic_nmi(mpic1); 571 572 of_node_put(master); 573 574 /* No slave, let's go out */ 575 if (slave == NULL) 576 return 0; 577 578 /* Get/Map slave interrupt */ 579 cascade = irq_of_parse_and_map(slave, 0); 580 if (cascade == NO_IRQ) { 581 printk(KERN_ERR "Failed to map cascade IRQ\n"); 582 return 0; 583 } 584 585 mpic2 = pmac_setup_one_mpic(slave, 0); 586 if (mpic2 == NULL) { 587 printk(KERN_ERR "Failed to setup slave MPIC\n"); 588 of_node_put(slave); 589 return 0; 590 } 591 set_irq_data(cascade, mpic2); 592 set_irq_chained_handler(cascade, pmac_u3_cascade); 593 594 of_node_put(slave); 595 return 0; 596} 597 598 599void __init pmac_pic_init(void) 600{ 601 /* We configure the OF parsing based on our oldworld vs. newworld 602 * platform type and wether we were booted by BootX. 603 */ 604#ifdef CONFIG_PPC32 605 if (!pmac_newworld) 606 of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC; 607 if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL) 608 of_irq_workarounds |= OF_IMAP_NO_PHANDLE; 609 610 /* If we don't have phandles on a newworld, then try to locate a 611 * default interrupt controller (happens when booting with BootX). 612 * We do a first match here, hopefully, that only ever happens on 613 * machines with one controller. 614 */ 615 if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) { 616 struct device_node *np; 617 618 for_each_node_with_property(np, "interrupt-controller") { 619 /* Skip /chosen/interrupt-controller */ 620 if (strcmp(np->name, "chosen") == 0) 621 continue; 622 /* It seems like at least one person wants 623 * to use BootX on a machine with an AppleKiwi 624 * controller which happens to pretend to be an 625 * interrupt controller too. */ 626 if (strcmp(np->name, "AppleKiwi") == 0) 627 continue; 628 /* I think we found one ! */ 629 of_irq_dflt_pic = np; 630 break; 631 } 632 } 633#endif /* CONFIG_PPC32 */ 634 635 /* We first try to detect Apple's new Core99 chipset, since mac-io 636 * is quite different on those machines and contains an IBM MPIC2. 637 */ 638 if (pmac_pic_probe_mpic() == 0) 639 return; 640 641#ifdef CONFIG_PPC32 642 pmac_pic_probe_oldstyle(); 643#endif 644} 645 646#if defined(CONFIG_PM) && defined(CONFIG_PPC32) 647/* 648 * These procedures are used in implementing sleep on the powerbooks. 649 * sleep_save_intrs() saves the states of all interrupt enables 650 * and disables all interrupts except for the nominated one. 651 * sleep_restore_intrs() restores the states of all interrupt enables. 652 */ 653unsigned long sleep_save_mask[2]; 654 655/* This used to be passed by the PMU driver but that link got 656 * broken with the new driver model. We use this tweak for now... 657 * We really want to do things differently though... 658 */ 659static int pmacpic_find_viaint(void) 660{ 661 int viaint = -1; 662 663#ifdef CONFIG_ADB_PMU 664 struct device_node *np; 665 666 if (pmu_get_model() != PMU_OHARE_BASED) 667 goto not_found; 668 np = of_find_node_by_name(NULL, "via-pmu"); 669 if (np == NULL) 670 goto not_found; 671 viaint = irq_of_parse_and_map(np, 0); 672 673not_found: 674#endif /* CONFIG_ADB_PMU */ 675 return viaint; 676} 677 678static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state) 679{ 680 int viaint = pmacpic_find_viaint(); 681 682 sleep_save_mask[0] = ppc_cached_irq_mask[0]; 683 sleep_save_mask[1] = ppc_cached_irq_mask[1]; 684 ppc_cached_irq_mask[0] = 0; 685 ppc_cached_irq_mask[1] = 0; 686 if (viaint > 0) 687 set_bit(viaint, ppc_cached_irq_mask); 688 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); 689 if (max_real_irqs > 32) 690 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); 691 (void)in_le32(&pmac_irq_hw[0]->event); 692 /* make sure mask gets to controller before we return to caller */ 693 mb(); 694 (void)in_le32(&pmac_irq_hw[0]->enable); 695 696 return 0; 697} 698 699static int pmacpic_resume(struct sys_device *sysdev) 700{ 701 int i; 702 703 out_le32(&pmac_irq_hw[0]->enable, 0); 704 if (max_real_irqs > 32) 705 out_le32(&pmac_irq_hw[1]->enable, 0); 706 mb(); 707 for (i = 0; i < max_real_irqs; ++i) 708 if (test_bit(i, sleep_save_mask)) 709 pmac_unmask_irq(i); 710 711 return 0; 712} 713 714#endif /* CONFIG_PM && CONFIG_PPC32 */ 715 716static struct sysdev_class pmacpic_sysclass = { 717 .name = "pmac_pic", 718}; 719 720static struct sys_device device_pmacpic = { 721 .id = 0, 722 .cls = &pmacpic_sysclass, 723}; 724 725static struct sysdev_driver driver_pmacpic = { 726#if defined(CONFIG_PM) && defined(CONFIG_PPC32) 727 .suspend = &pmacpic_suspend, 728 .resume = &pmacpic_resume, 729#endif /* CONFIG_PM && CONFIG_PPC32 */ 730}; 731 732static int __init init_pmacpic_sysfs(void) 733{ 734#ifdef CONFIG_PPC32 735 if (max_irqs == 0) 736 return -ENODEV; 737#endif 738 printk(KERN_DEBUG "Registering pmac pic with sysfs...\n"); 739 sysdev_class_register(&pmacpic_sysclass); 740 sysdev_register(&device_pmacpic); 741 sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic); 742 return 0; 743} 744machine_subsys_initcall(powermac, init_pmacpic_sysfs); 745