1/* 2 * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved. 3 * Dave Liu <daveliu@freescale.com> 4 * copy from idle_6xx.S and modify for e500 based processor, 5 * implement the power_save function in idle. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#include <linux/threads.h> 14#include <asm/reg.h> 15#include <asm/page.h> 16#include <asm/cputable.h> 17#include <asm/thread_info.h> 18#include <asm/ppc_asm.h> 19#include <asm/asm-offsets.h> 20 21 .text 22 23_GLOBAL(e500_idle) 24 rlwinm r3,r1,0,0,31-THREAD_SHIFT /* current thread_info */ 25 lwz r4,TI_LOCAL_FLAGS(r3) /* set napping bit */ 26 ori r4,r4,_TLF_NAPPING /* so when we take an exception */ 27 stw r4,TI_LOCAL_FLAGS(r3) /* it will return to our caller */ 28 29 /* Check if we can nap or doze, put HID0 mask in r3 */ 30 lis r3,0 31BEGIN_FTR_SECTION 32 lis r3,HID0_DOZE@h 33END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) 34 35BEGIN_FTR_SECTION 36 /* Now check if user enabled NAP mode */ 37 lis r4,powersave_nap@ha 38 lwz r4,powersave_nap@l(r4) 39 cmpwi 0,r4,0 40 beq 1f 41 stwu r1,-16(r1) 42 mflr r0 43 stw r0,20(r1) 44 bl flush_dcache_L1 45 lwz r0,20(r1) 46 addi r1,r1,16 47 mtlr r0 48 lis r3,HID0_NAP@h 49END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 50BEGIN_FTR_SECTION 51 msync 52 li r7,L2CSR0_L2FL@l 53 mtspr SPRN_L2CSR0,r7 542: 55 mfspr r7,SPRN_L2CSR0 56 andi. r4,r7,L2CSR0_L2FL@l 57 bne 2b 58END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP) 591: 60 /* Go to NAP or DOZE now */ 61 mfspr r4,SPRN_HID0 62 rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP) 63 or r4,r4,r3 64 isync 65 mtspr SPRN_HID0,r4 66 isync 67 68 mfmsr r7 69 oris r7,r7,MSR_WE@h 70 ori r7,r7,MSR_EE 71 msync 72 mtmsr r7 73 isync 742: b 2b 75 76/* 77 * Return from NAP/DOZE mode, restore some CPU specific registers, 78 * r2 containing physical address of current. 79 * r11 points to the exception frame (physical address). 80 * We have to preserve r10. 81 */ 82_GLOBAL(power_save_ppc32_restore) 83 lwz r9,_LINK(r11) /* interrupted in e500_idle */ 84 stw r9,_NIP(r11) /* make it do a blr */ 85 86#ifdef CONFIG_SMP 87 rlwinm r12,r1,0,0,31-THREAD_SHIFT 88 lwz r11,TI_CPU(r12) /* get cpu number * 4 */ 89 slwi r11,r11,2 90#else 91 li r11,0 92#endif 93 94 b transfer_to_handler_cont 95