1/* 2 * Contains register definitions common to the Book E PowerPC 3 * specification. Notice that while the IBM-40x series of CPUs 4 * are not true Book E PowerPCs, they borrowed a number of features 5 * before Book E was finalized, and are included here as well. Unfortunatly, 6 * they sometimes used different locations than true Book E CPUs did. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License version 2 10 * as published by the Free Software Foundation. 11 * 12 * Copyright 2009-2010 Freescale Semiconductor, Inc. 13 */ 14#ifdef __KERNEL__ 15#ifndef __ASM_POWERPC_REG_BOOKE_H__ 16#define __ASM_POWERPC_REG_BOOKE_H__ 17 18/* Machine State Register (MSR) Fields */ 19#define MSR_GS (1<<28) /* Guest state */ 20#define MSR_UCLE (1<<26) /* User-mode cache lock enable */ 21#define MSR_SPE (1<<25) /* Enable SPE */ 22#define MSR_DWE (1<<10) /* Debug Wait Enable */ 23#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ 24#define MSR_IS MSR_IR /* Instruction Space */ 25#define MSR_DS MSR_DR /* Data Space */ 26#define MSR_PMM (1<<2) /* Performance monitor mark bit */ 27#define MSR_CM (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */ 28 29#if defined(CONFIG_PPC_BOOK3E_64) 30#define MSR_ MSR_ME | MSR_CE 31#define MSR_KERNEL MSR_ | MSR_CM 32#define MSR_USER32 MSR_ | MSR_PR | MSR_EE | MSR_DE 33#define MSR_USER64 MSR_USER32 | MSR_CM | MSR_DE 34#elif defined(CONFIG_40x) 35#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) 36#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 37#else 38#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) 39#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 40#endif 41 42/* Special Purpose Registers (SPRNs)*/ 43#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ 44#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ 45#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ 46#define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */ 47#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ 48#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ 49#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ 50#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ 51#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ 52#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ 53#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ 54#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ 55#define SPRN_EPCR 0x133 /* Embedded Processor Control Register */ 56#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ 57#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ 58#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ 59#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ 60#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ 61#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ 62#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ 63#define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */ 64#define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */ 65#define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */ 66#define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */ 67#define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */ 68#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ 69#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ 70#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ 71#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ 72#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ 73#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ 74#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ 75#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ 76#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ 77#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ 78#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ 79#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ 80#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ 81#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ 82#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ 83#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ 84#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 85#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 86#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 87#define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */ 88#define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */ 89#define SPRN_ATB 0x20E /* Alternate Time Base */ 90#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ 91#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ 92#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ 93#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ 94#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ 95#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ 96#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ 97#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ 98#define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */ 99#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ 100#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 101#define SPRN_MCSR 0x23C /* Machine Check Status Register */ 102#define SPRN_MCAR 0x23D /* Machine Check Address Register */ 103#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ 104#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ 105#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */ 106#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */ 107#define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */ 108#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 109#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 110#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 111#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ 112#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ 113#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ 114#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ 115#define SPRN_PID1 0x279 /* Process ID Register 1 */ 116#define SPRN_PID2 0x27A /* Process ID Register 2 */ 117#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ 118#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ 119#define SPRN_TLB2CFG 0x2B2 /* TLB 2 Config Register */ 120#define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */ 121#define SPRN_EPR 0x2BE /* External Proxy Register */ 122#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ 123#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ 124#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ 125#define SPRN_MMUCR 0x3B2 /* MMU Control Register */ 126#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ 127#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */ 128#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */ 129#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ 130#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ 131#define SPRN_SLER 0x3BB /* Little-endian real mode */ 132#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ 133#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ 134#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ 135#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ 136#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ 137#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ 138#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */ 139#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */ 140#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 141#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ 142#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */ 143#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ 144#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 145#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 146#define SPRN_SVR 0x3FF /* System Version Register */ 147 148/* 149 * SPRs which have conflicting definitions on true Book E versus classic, 150 * or IBM 40x. 151 */ 152#ifdef CONFIG_BOOKE 153#define SPRN_PID 0x030 /* Process ID */ 154#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ 155#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ 156#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ 157#define SPRN_DEAR 0x03D /* Data Error Address Register */ 158#define SPRN_ESR 0x03E /* Exception Syndrome Register */ 159#define SPRN_PIR 0x11E /* Processor Identification Register */ 160#define SPRN_DBSR 0x130 /* Debug Status Register */ 161#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ 162#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ 163#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ 164#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ 165#define SPRN_DAC1 0x13C /* Data Address Compare 1 */ 166#define SPRN_DAC2 0x13D /* Data Address Compare 2 */ 167#define SPRN_TSR 0x150 /* Timer Status Register */ 168#define SPRN_TCR 0x154 /* Timer Control Register */ 169#endif /* Book E */ 170#ifdef CONFIG_40x 171#define SPRN_PID 0x3B1 /* Process ID */ 172#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ 173#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ 174#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ 175#define SPRN_TSR 0x3D8 /* Timer Status Register */ 176#define SPRN_TCR 0x3DA /* Timer Control Register */ 177#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ 178#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ 179#define SPRN_DBSR 0x3F0 /* Debug Status Register */ 180#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ 181#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ 182#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ 183#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ 184#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ 185#endif 186 187/* Bit definitions for CCR1. */ 188#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ 189#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 190 191/* Bit definitions for the MCSR. */ 192#define MCSR_MCS 0x80000000 /* Machine Check Summary */ 193#define MCSR_IB 0x40000000 /* Instruction PLB Error */ 194#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ 195#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ 196#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ 197#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ 198#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ 199#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ 200#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ 201 202#define PPC47x_MCSR_GPR 0x01000000 /* GPR parity error */ 203#define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */ 204#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */ 205 206#ifdef CONFIG_E500 207/* All e500 */ 208#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 209#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ 210 211/* e500v1/v2 */ 212#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ 213#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ 214#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ 215#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ 216#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ 217#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ 218#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ 219#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ 220#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ 221#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ 222 223/* e500mc */ 224#define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */ 225#define MCSR_L2MMU_MHIT 0x04000000UL /* Hit on multiple TLB entries */ 226#define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */ 227#define MCSR_MAV 0x00080000UL /* MCAR address valid */ 228#define MCSR_MEA 0x00040000UL /* MCAR is effective address */ 229#define MCSR_IF 0x00010000UL /* Instruction Fetch */ 230#define MCSR_LD 0x00008000UL /* Load */ 231#define MCSR_ST 0x00004000UL /* Store */ 232#define MCSR_LDG 0x00002000UL /* Guarded Load */ 233#define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */ 234#define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */ 235#endif 236 237#ifdef CONFIG_E200 238#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 239#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ 240#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ 241#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn 242 fetch for an exception handler */ 243#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ 244#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ 245#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered 246 store or cache line push */ 247#endif 248 249/* Bit definitions for the DBSR. */ 250/* 251 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. 252 */ 253#ifdef CONFIG_BOOKE 254#define DBSR_IC 0x08000000 /* Instruction Completion */ 255#define DBSR_BT 0x04000000 /* Branch Taken */ 256#define DBSR_IRPT 0x02000000 /* Exception Debug Event */ 257#define DBSR_TIE 0x01000000 /* Trap Instruction Event */ 258#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ 259#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ 260#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ 261#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ 262#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ 263#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ 264#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ 265#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ 266#define DBSR_RET 0x00008000 /* Return Debug Event */ 267#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ 268#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */ 269#define DBSR_IAC12ATS 0x00000002 /* Instr Address Compare 1/2 Toggle */ 270#define DBSR_IAC34ATS 0x00000001 /* Instr Address Compare 3/4 Toggle */ 271#endif 272#ifdef CONFIG_40x 273#define DBSR_IC 0x80000000 /* Instruction Completion */ 274#define DBSR_BT 0x40000000 /* Branch taken */ 275#define DBSR_IRPT 0x20000000 /* Exception Debug Event */ 276#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ 277#define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ 278#define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ 279#define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ 280#define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ 281#define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ 282#define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ 283#define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ 284#define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ 285#endif 286 287/* Bit definitions related to the ESR. */ 288#define ESR_MCI 0x80000000 /* Machine Check - Instruction */ 289#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ 290#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ 291#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ 292#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ 293#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ 294#define ESR_PPR 0x04000000 /* Program Exception - Privileged */ 295#define ESR_PTR 0x02000000 /* Program Exception - Trap */ 296#define ESR_FP 0x01000000 /* Floating Point Operation */ 297#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ 298#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ 299#define ESR_ST 0x00800000 /* Store Operation */ 300#define ESR_DLK 0x00200000 /* Data Cache Locking */ 301#define ESR_ILK 0x00100000 /* Instr. Cache Locking */ 302#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ 303#define ESR_BO 0x00020000 /* Byte Ordering */ 304 305/* Bit definitions related to the DBCR0. */ 306#if defined(CONFIG_40x) 307#define DBCR0_EDM 0x80000000 /* External Debug Mode */ 308#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 309#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ 310#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ 311#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ 312#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ 313#define DBCR0_RST_NONE 0x00000000 /* No Reset */ 314#define DBCR0_IC 0x08000000 /* Instruction Completion */ 315#define DBCR0_ICMP DBCR0_IC 316#define DBCR0_BT 0x04000000 /* Branch Taken */ 317#define DBCR0_BRT DBCR0_BT 318#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 319#define DBCR0_IRPT DBCR0_EDE 320#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ 321#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ 322#define DBCR0_IAC1 DBCR0_IA1 323#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ 324#define DBCR0_IAC2 DBCR0_IA2 325#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ 326#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ 327#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ 328#define DBCR0_IAC3 DBCR0_IA3 329#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ 330#define DBCR0_IAC4 DBCR0_IA4 331#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ 332#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ 333#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ 334#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ 335#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 336 337#define dbcr_iac_range(task) ((task)->thread.dbcr0) 338#define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */ 339#define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */ 340#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */ 341#define DBCR_IAC34I DBCR0_IA34 /* Range Inclusive */ 342#define DBCR_IAC34X (DBCR0_IA34 | DBCR0_IA34X) /* Range Exclusive */ 343#define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X) /* IAC 3-4 Mode Bits */ 344 345/* Bit definitions related to the DBCR1. */ 346#define DBCR1_DAC1R 0x80000000 /* DAC1 Read Debug Event */ 347#define DBCR1_DAC2R 0x40000000 /* DAC2 Read Debug Event */ 348#define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */ 349#define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */ 350 351#define dbcr_dac(task) ((task)->thread.dbcr1) 352#define DBCR_DAC1R DBCR1_DAC1R 353#define DBCR_DAC1W DBCR1_DAC1W 354#define DBCR_DAC2R DBCR1_DAC2R 355#define DBCR_DAC2W DBCR1_DAC2W 356 357/* 358 * Are there any active Debug Events represented in the 359 * Debug Control Registers? 360 */ 361#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \ 362 DBCR0_IAC3 | DBCR0_IAC4) 363#define DBCR1_ACTIVE_EVENTS (DBCR1_DAC1R | DBCR1_DAC2R | \ 364 DBCR1_DAC1W | DBCR1_DAC2W) 365#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \ 366 ((dbcr1) & DBCR1_ACTIVE_EVENTS)) 367 368#elif defined(CONFIG_BOOKE) 369#define DBCR0_EDM 0x80000000 /* External Debug Mode */ 370#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 371#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ 372/* DBCR0_RST_* is 44x specific and not followed in fsl booke */ 373#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ 374#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ 375#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ 376#define DBCR0_RST_NONE 0x00000000 /* No Reset */ 377#define DBCR0_ICMP 0x08000000 /* Instruction Completion */ 378#define DBCR0_IC DBCR0_ICMP 379#define DBCR0_BRT 0x04000000 /* Branch Taken */ 380#define DBCR0_BT DBCR0_BRT 381#define DBCR0_IRPT 0x02000000 /* Exception Debug Event */ 382#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ 383#define DBCR0_TIE DBCR0_TDE 384#define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */ 385#define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */ 386#define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */ 387#define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */ 388#define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */ 389#define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */ 390#define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */ 391#define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */ 392#define DBCR0_RET 0x00008000 /* Return Debug Event */ 393#define DBCR0_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ 394#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */ 395#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 396 397#define dbcr_dac(task) ((task)->thread.dbcr0) 398#define DBCR_DAC1R DBCR0_DAC1R 399#define DBCR_DAC1W DBCR0_DAC1W 400#define DBCR_DAC2R DBCR0_DAC2R 401#define DBCR_DAC2W DBCR0_DAC2W 402 403/* Bit definitions related to the DBCR1. */ 404#define DBCR1_IAC1US 0xC0000000 /* Instr Addr Cmp 1 Sup/User */ 405#define DBCR1_IAC1ER 0x30000000 /* Instr Addr Cmp 1 Eff/Real */ 406#define DBCR1_IAC1ER_01 0x10000000 /* reserved */ 407#define DBCR1_IAC1ER_10 0x20000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */ 408#define DBCR1_IAC1ER_11 0x30000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */ 409#define DBCR1_IAC2US 0x0C000000 /* Instr Addr Cmp 2 Sup/User */ 410#define DBCR1_IAC2ER 0x03000000 /* Instr Addr Cmp 2 Eff/Real */ 411#define DBCR1_IAC2ER_01 0x01000000 /* reserved */ 412#define DBCR1_IAC2ER_10 0x02000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */ 413#define DBCR1_IAC2ER_11 0x03000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */ 414#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */ 415#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */ 416#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */ 417#define DBCR1_IAC3US 0x0000C000 /* Instr Addr Cmp 3 Sup/User */ 418#define DBCR1_IAC3ER 0x00003000 /* Instr Addr Cmp 3 Eff/Real */ 419#define DBCR1_IAC3ER_01 0x00001000 /* reserved */ 420#define DBCR1_IAC3ER_10 0x00002000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */ 421#define DBCR1_IAC3ER_11 0x00003000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */ 422#define DBCR1_IAC4US 0x00000C00 /* Instr Addr Cmp 4 Sup/User */ 423#define DBCR1_IAC4ER 0x00000300 /* Instr Addr Cmp 4 Eff/Real */ 424#define DBCR1_IAC4ER_01 0x00000100 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */ 425#define DBCR1_IAC4ER_10 0x00000200 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */ 426#define DBCR1_IAC4ER_11 0x00000300 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */ 427#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */ 428#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */ 429#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */ 430 431#define dbcr_iac_range(task) ((task)->thread.dbcr1) 432#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */ 433#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */ 434#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */ 435#define DBCR_IAC34I DBCR1_IAC34M /* Range Inclusive */ 436#define DBCR_IAC34X DBCR1_IAC34MX /* Range Exclusive */ 437#define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */ 438 439/* Bit definitions related to the DBCR2. */ 440#define DBCR2_DAC1US 0xC0000000 /* Data Addr Cmp 1 Sup/User */ 441#define DBCR2_DAC1ER 0x30000000 /* Data Addr Cmp 1 Eff/Real */ 442#define DBCR2_DAC2US 0x0C000000 /* Data Addr Cmp 2 Sup/User */ 443#define DBCR2_DAC2ER 0x03000000 /* Data Addr Cmp 2 Eff/Real */ 444#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */ 445#define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/ 446#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */ 447#define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */ 448#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */ 449#define DBCR2_DVC1M 0x000C0000 /* Data Value Comp 1 Mode */ 450#define DBCR2_DVC1M_SHIFT 18 /* # of bits to shift DBCR2_DVC1M */ 451#define DBCR2_DVC2M 0x00030000 /* Data Value Comp 2 Mode */ 452#define DBCR2_DVC2M_SHIFT 16 /* # of bits to shift DBCR2_DVC2M */ 453#define DBCR2_DVC1BE 0x00000F00 /* Data Value Comp 1 Byte */ 454#define DBCR2_DVC1BE_SHIFT 8 /* # of bits to shift DBCR2_DVC1BE */ 455#define DBCR2_DVC2BE 0x0000000F /* Data Value Comp 2 Byte */ 456#define DBCR2_DVC2BE_SHIFT 0 /* # of bits to shift DBCR2_DVC2BE */ 457 458/* 459 * Are there any active Debug Events represented in the 460 * Debug Control Registers? 461 */ 462#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \ 463 DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \ 464 DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W) 465#define DBCR1_ACTIVE_EVENTS 0 466 467#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \ 468 ((dbcr1) & DBCR1_ACTIVE_EVENTS)) 469#endif /* #elif defined(CONFIG_BOOKE) */ 470 471/* Bit definitions related to the TCR. */ 472#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ 473#define TCR_WP_MASK TCR_WP(3) 474#define WP_2_17 0 /* 2^17 clocks */ 475#define WP_2_21 1 /* 2^21 clocks */ 476#define WP_2_25 2 /* 2^25 clocks */ 477#define WP_2_29 3 /* 2^29 clocks */ 478#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ 479#define TCR_WRC_MASK TCR_WRC(3) 480#define WRC_NONE 0 /* No reset will occur */ 481#define WRC_CORE 1 /* Core reset will occur */ 482#define WRC_CHIP 2 /* Chip reset will occur */ 483#define WRC_SYSTEM 3 /* System reset will occur */ 484#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ 485#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 486#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ 487#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ 488#define TCR_FP_MASK TCR_FP(3) 489#define FP_2_9 0 /* 2^9 clocks */ 490#define FP_2_13 1 /* 2^13 clocks */ 491#define FP_2_17 2 /* 2^17 clocks */ 492#define FP_2_21 3 /* 2^21 clocks */ 493#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 494#define TCR_ARE 0x00400000 /* Auto Reload Enable */ 495 496/* Bit definitions for the TSR. */ 497#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 498#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ 499#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ 500#define WRS_NONE 0 /* No WDT reset occurred */ 501#define WRS_CORE 1 /* WDT forced core reset */ 502#define WRS_CHIP 2 /* WDT forced chip reset */ 503#define WRS_SYSTEM 3 /* WDT forced system reset */ 504#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 505#define TSR_DIS TSR_PIS /* DEC Interrupt Status */ 506#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 507 508/* Bit definitions for the DCCR. */ 509#define DCCR_NOCACHE 0 /* Noncacheable */ 510#define DCCR_CACHE 1 /* Cacheable */ 511 512/* Bit definitions for DCWR. */ 513#define DCWR_COPY 0 /* Copy-back */ 514#define DCWR_WRITE 1 /* Write-through */ 515 516/* Bit definitions for ICCR. */ 517#define ICCR_NOCACHE 0 /* Noncacheable */ 518#define ICCR_CACHE 1 /* Cacheable */ 519 520/* Bit definitions for L1CSR0. */ 521#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ 522#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ 523#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 524#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ 525#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 526 527/* Bit definitions for L1CSR1. */ 528#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ 529#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ 530#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ 531#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ 532 533/* Bit definitions for L2CSR0. */ 534#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ 535#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ 536#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ 537#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ 538#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ 539#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ 540#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ 541#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ 542#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ 543#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ 544#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ 545#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ 546 547/* Bit definitions for SGR. */ 548#define SGR_NORMAL 0 /* Speculative fetching allowed. */ 549#define SGR_GUARDED 1 /* Speculative fetching disallowed. */ 550 551/* Bit definitions for EPCR */ 552#define SPRN_EPCR_EXTGS 0x80000000 /* External Input interrupt 553 * directed to Guest state */ 554#define SPRN_EPCR_DTLBGS 0x40000000 /* Data TLB Error interrupt 555 * directed to guest state */ 556#define SPRN_EPCR_ITLBGS 0x20000000 /* Instr. TLB error interrupt 557 * directed to guest state */ 558#define SPRN_EPCR_DSIGS 0x10000000 /* Data Storage interrupt 559 * directed to guest state */ 560#define SPRN_EPCR_ISIGS 0x08000000 /* Instr. Storage interrupt 561 * directed to guest state */ 562#define SPRN_EPCR_DUVD 0x04000000 /* Disable Hypervisor Debug */ 563#define SPRN_EPCR_ICM 0x02000000 /* Interrupt computation mode 564 * (copied to MSR:CM on intr) */ 565#define SPRN_EPCR_GICM 0x01000000 /* Guest Interrupt Comp. mode */ 566#define SPRN_EPCR_DGTMI 0x00800000 /* Disable TLB Guest Management 567 * instructions */ 568#define SPRN_EPCR_DMIUH 0x00400000 /* Disable MAS Interrupt updates 569 * for hypervisor */ 570 571 572/* 573 * The IBM-403 is an even more odd special case, as it is much 574 * older than the IBM-405 series. We put these down here incase someone 575 * wishes to support these machines again. 576 */ 577#ifdef CONFIG_403GCX 578/* Special Purpose Registers (SPRNs)*/ 579#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ 580#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ 581#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ 582#define SPRN_TBHI 0x3DC /* Time Base High */ 583#define SPRN_TBLO 0x3DD /* Time Base Low */ 584#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ 585#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ 586#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ 587#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ 588#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ 589 590 591/* Bit definitions for the DBCR. */ 592#define DBCR_EDM DBCR0_EDM 593#define DBCR_IDM DBCR0_IDM 594#define DBCR_RST(x) (((x) & 0x3) << 28) 595#define DBCR_RST_NONE 0 596#define DBCR_RST_CORE 1 597#define DBCR_RST_CHIP 2 598#define DBCR_RST_SYSTEM 3 599#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ 600#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ 601#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ 602#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ 603#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ 604#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ 605#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ 606#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ 607#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ 608#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ 609#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ 610#define DAC_BYTE 0 611#define DAC_HALF 1 612#define DAC_WORD 2 613#define DAC_QUAD 3 614#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ 615#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ 616#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ 617#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ 618#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ 619#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ 620#define DBCR_SIA 0x00000008 /* Second IAC Enable */ 621#define DBCR_SDA 0x00000004 /* Second DAC Enable */ 622#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ 623#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ 624#endif /* 403GCX */ 625 626/* Some 476 specific registers */ 627#define SPRN_SSPCR 830 628#define SPRN_USPCR 831 629#define SPRN_ISPCR 829 630#define SPRN_MMUBE0 820 631#define MMUBE0_IBE0_SHIFT 24 632#define MMUBE0_IBE1_SHIFT 16 633#define MMUBE0_IBE2_SHIFT 8 634#define MMUBE0_VBE0 0x00000004 635#define MMUBE0_VBE1 0x00000002 636#define MMUBE0_VBE2 0x00000001 637#define SPRN_MMUBE1 821 638#define MMUBE1_IBE3_SHIFT 24 639#define MMUBE1_IBE4_SHIFT 16 640#define MMUBE1_IBE5_SHIFT 8 641#define MMUBE1_VBE3 0x00000004 642#define MMUBE1_VBE4 0x00000002 643#define MMUBE1_VBE5 0x00000001 644 645#endif /* __ASM_POWERPC_REG_BOOKE_H__ */ 646#endif /* __KERNEL__ */ 647