1/* 2 * Copyright 2009 Freescale Semicondutor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * provides masks and opcode images for use by code generation, emulation 10 * and for instructions that older assemblers might not know about 11 */ 12#ifndef _ASM_POWERPC_PPC_OPCODE_H 13#define _ASM_POWERPC_PPC_OPCODE_H 14 15#include <linux/stringify.h> 16#include <asm/asm-compat.h> 17 18/* sorted alphabetically */ 19#define PPC_INST_DCBA 0x7c0005ec 20#define PPC_INST_DCBA_MASK 0xfc0007fe 21#define PPC_INST_DCBAL 0x7c2005ec 22#define PPC_INST_DCBZL 0x7c2007ec 23#define PPC_INST_ISEL 0x7c00001e 24#define PPC_INST_ISEL_MASK 0xfc00003e 25#define PPC_INST_LDARX 0x7c0000a8 26#define PPC_INST_LSWI 0x7c0004aa 27#define PPC_INST_LSWX 0x7c00042a 28#define PPC_INST_LWARX 0x7c000028 29#define PPC_INST_LWSYNC 0x7c2004ac 30#define PPC_INST_LXVD2X 0x7c000698 31#define PPC_INST_MCRXR 0x7c000400 32#define PPC_INST_MCRXR_MASK 0xfc0007fe 33#define PPC_INST_MFSPR_PVR 0x7c1f42a6 34#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff 35#define PPC_INST_MSGSND 0x7c00019c 36#define PPC_INST_NOP 0x60000000 37#define PPC_INST_POPCNTB 0x7c0000f4 38#define PPC_INST_POPCNTB_MASK 0xfc0007fe 39#define PPC_INST_RFCI 0x4c000066 40#define PPC_INST_RFDI 0x4c00004e 41#define PPC_INST_RFMCI 0x4c00004c 42 43#define PPC_INST_STRING 0x7c00042a 44#define PPC_INST_STRING_MASK 0xfc0007fe 45#define PPC_INST_STRING_GEN_MASK 0xfc00067e 46 47#define PPC_INST_STSWI 0x7c0005aa 48#define PPC_INST_STSWX 0x7c00052a 49#define PPC_INST_STXVD2X 0x7c000798 50#define PPC_INST_TLBIE 0x7c000264 51#define PPC_INST_TLBILX 0x7c000024 52#define PPC_INST_WAIT 0x7c00007c 53#define PPC_INST_TLBIVAX 0x7c000624 54#define PPC_INST_TLBSRX_DOT 0x7c0006a5 55#define PPC_INST_XXLOR 0xf0000510 56 57/* macros to insert fields into opcodes */ 58#define __PPC_RA(a) (((a) & 0x1f) << 16) 59#define __PPC_RB(b) (((b) & 0x1f) << 11) 60#define __PPC_RS(s) (((s) & 0x1f) << 21) 61#define __PPC_RT(s) __PPC_RS(s) 62#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3)) 63#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4)) 64#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) 65#define __PPC_XT(s) __PPC_XS(s) 66#define __PPC_T_TLB(t) (((t) & 0x3) << 21) 67#define __PPC_WC(w) (((w) & 0x3) << 21) 68/* 69 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a 70 * larx with EH set as an illegal instruction. 71 */ 72#ifdef CONFIG_PPC64 73#define __PPC_EH(eh) (((eh) & 0x1) << 0) 74#else 75#define __PPC_EH(eh) 0 76#endif 77 78/* Deal with instructions that older assemblers aren't aware of */ 79#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ 80 __PPC_RA(a) | __PPC_RB(b)) 81#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ 82 __PPC_RA(a) | __PPC_RB(b)) 83#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ 84 __PPC_RT(t) | __PPC_RA(a) | \ 85 __PPC_RB(b) | __PPC_EH(eh)) 86#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ 87 __PPC_RT(t) | __PPC_RA(a) | \ 88 __PPC_RB(b) | __PPC_EH(eh)) 89#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ 90 __PPC_RB(b)) 91#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) 92#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) 93#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) 94#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ 95 __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) 96#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) 97#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) 98#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) 99#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ 100 __PPC_WC(w)) 101#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ 102 __PPC_RB(a) | __PPC_RS(lp)) 103#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \ 104 __PPC_RA(a) | __PPC_RB(b)) 105#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ 106 __PPC_RA(a) | __PPC_RB(b)) 107 108/* 109 * Define what the VSX XX1 form instructions will look like, then add 110 * the 128 bit load store instructions based on that. 111 */ 112#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b)) 113#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b)) 114#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \ 115 VSX_XX1((s), (a), (b))) 116#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \ 117 VSX_XX1((s), (a), (b))) 118#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \ 119 VSX_XX3((t), (a), (b))) 120 121#endif /* _ASM_POWERPC_PPC_OPCODE_H */ 122