1/* 2 * include/asm-ppc/mpc52xx_psc.h 3 * 4 * Definitions of consts/structs to drive the Freescale MPC52xx OnChip 5 * PSCs. Theses are shared between multiple drivers since a PSC can be 6 * UART, AC97, IR, I2S, ... So this header is in asm-ppc. 7 * 8 * 9 * Maintainer : Sylvain Munaut <tnt@246tNt.com> 10 * 11 * Based/Extracted from some header of the 2.4 originally written by 12 * Dale Farnsworth <dfarnsworth@mvista.com> 13 * 14 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com> 15 * Copyright (C) 2003 MontaVista, Software, Inc. 16 * 17 * This file is licensed under the terms of the GNU General Public License 18 * version 2. This program is licensed "as is" without any warranty of any 19 * kind, whether express or implied. 20 */ 21 22#ifndef __ASM_MPC52xx_PSC_H__ 23#define __ASM_MPC52xx_PSC_H__ 24 25#include <asm/types.h> 26 27/* Max number of PSCs */ 28#ifdef CONFIG_PPC_MPC512x 29#define MPC52xx_PSC_MAXNUM 12 30#else 31#define MPC52xx_PSC_MAXNUM 6 32#endif 33 34/* Programmable Serial Controller (PSC) status register bits */ 35#define MPC52xx_PSC_SR_UNEX_RX 0x0001 36#define MPC52xx_PSC_SR_DATA_VAL 0x0002 37#define MPC52xx_PSC_SR_DATA_OVR 0x0004 38#define MPC52xx_PSC_SR_CMDSEND 0x0008 39#define MPC52xx_PSC_SR_CDE 0x0080 40#define MPC52xx_PSC_SR_RXRDY 0x0100 41#define MPC52xx_PSC_SR_RXFULL 0x0200 42#define MPC52xx_PSC_SR_TXRDY 0x0400 43#define MPC52xx_PSC_SR_TXEMP 0x0800 44#define MPC52xx_PSC_SR_OE 0x1000 45#define MPC52xx_PSC_SR_PE 0x2000 46#define MPC52xx_PSC_SR_FE 0x4000 47#define MPC52xx_PSC_SR_RB 0x8000 48 49/* PSC Command values */ 50#define MPC52xx_PSC_RX_ENABLE 0x0001 51#define MPC52xx_PSC_RX_DISABLE 0x0002 52#define MPC52xx_PSC_TX_ENABLE 0x0004 53#define MPC52xx_PSC_TX_DISABLE 0x0008 54#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010 55#define MPC52xx_PSC_RST_RX 0x0020 56#define MPC52xx_PSC_RST_TX 0x0030 57#define MPC52xx_PSC_RST_ERR_STAT 0x0040 58#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050 59#define MPC52xx_PSC_START_BRK 0x0060 60#define MPC52xx_PSC_STOP_BRK 0x0070 61 62/* PSC TxRx FIFO status bits */ 63#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040 64#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020 65#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010 66#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008 67#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004 68#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002 69#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 70 71/* PSC interrupt status/mask bits */ 72#define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001 73#define MPC52xx_PSC_IMR_DATA_VALID 0x0002 74#define MPC52xx_PSC_IMR_DATA_OVR 0x0004 75#define MPC52xx_PSC_IMR_CMD_SEND 0x0008 76#define MPC52xx_PSC_IMR_ERROR 0x0040 77#define MPC52xx_PSC_IMR_DEOF 0x0080 78#define MPC52xx_PSC_IMR_TXRDY 0x0100 79#define MPC52xx_PSC_IMR_RXRDY 0x0200 80#define MPC52xx_PSC_IMR_DB 0x0400 81#define MPC52xx_PSC_IMR_TXEMP 0x0800 82#define MPC52xx_PSC_IMR_ORERR 0x1000 83#define MPC52xx_PSC_IMR_IPC 0x8000 84 85/* PSC input port change bits */ 86#define MPC52xx_PSC_CTS 0x01 87#define MPC52xx_PSC_DCD 0x02 88#define MPC52xx_PSC_D_CTS 0x10 89#define MPC52xx_PSC_D_DCD 0x20 90 91/* PSC acr bits */ 92#define MPC52xx_PSC_IEC_CTS 0x01 93#define MPC52xx_PSC_IEC_DCD 0x02 94 95/* PSC output port bits */ 96#define MPC52xx_PSC_OP_RTS 0x01 97#define MPC52xx_PSC_OP_RES 0x02 98 99/* PSC mode fields */ 100#define MPC52xx_PSC_MODE_5_BITS 0x00 101#define MPC52xx_PSC_MODE_6_BITS 0x01 102#define MPC52xx_PSC_MODE_7_BITS 0x02 103#define MPC52xx_PSC_MODE_8_BITS 0x03 104#define MPC52xx_PSC_MODE_BITS_MASK 0x03 105#define MPC52xx_PSC_MODE_PAREVEN 0x00 106#define MPC52xx_PSC_MODE_PARODD 0x04 107#define MPC52xx_PSC_MODE_PARFORCE 0x08 108#define MPC52xx_PSC_MODE_PARNONE 0x10 109#define MPC52xx_PSC_MODE_ERR 0x20 110#define MPC52xx_PSC_MODE_FFULL 0x40 111#define MPC52xx_PSC_MODE_RXRTS 0x80 112 113#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00 114#define MPC52xx_PSC_MODE_ONE_STOP 0x07 115#define MPC52xx_PSC_MODE_TWO_STOP 0x0f 116#define MPC52xx_PSC_MODE_TXCTS 0x10 117 118#define MPC52xx_PSC_RFNUM_MASK 0x01ff 119 120#define MPC52xx_PSC_SICR_DTS1 (1 << 29) 121#define MPC52xx_PSC_SICR_SHDR (1 << 28) 122#define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24) 123#define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24) 124#define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24) 125#define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24) 126#define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24) 127#define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24) 128#define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24) 129#define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24) 130#define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24) 131#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24) 132#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24) 133#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24) 134#define MPC52xx_PSC_SICR_ACRB (0x8 << 24) 135#define MPC52xx_PSC_SICR_AWR (1 << 30) 136#define MPC52xx_PSC_SICR_GENCLK (1 << 23) 137#define MPC52xx_PSC_SICR_I2S (1 << 22) 138#define MPC52xx_PSC_SICR_CLKPOL (1 << 21) 139#define MPC52xx_PSC_SICR_SYNCPOL (1 << 20) 140#define MPC52xx_PSC_SICR_CELLSLAVE (1 << 19) 141#define MPC52xx_PSC_SICR_CELL2XCLK (1 << 18) 142#define MPC52xx_PSC_SICR_ESAI (1 << 17) 143#define MPC52xx_PSC_SICR_ENAC97 (1 << 16) 144#define MPC52xx_PSC_SICR_SPI (1 << 15) 145#define MPC52xx_PSC_SICR_MSTR (1 << 14) 146#define MPC52xx_PSC_SICR_CPOL (1 << 13) 147#define MPC52xx_PSC_SICR_CPHA (1 << 12) 148#define MPC52xx_PSC_SICR_USEEOF (1 << 11) 149#define MPC52xx_PSC_SICR_DISABLEEOF (1 << 10) 150 151/* Structure of the hardware registers */ 152struct mpc52xx_psc { 153 u8 mode; /* PSC + 0x00 */ 154 u8 reserved0[3]; 155 union { /* PSC + 0x04 */ 156 u16 status; 157 u16 clock_select; 158 } sr_csr; 159#define mpc52xx_psc_status sr_csr.status 160#define mpc52xx_psc_clock_select sr_csr.clock_select 161 u16 reserved1; 162 u8 command; /* PSC + 0x08 */ 163 u8 reserved2[3]; 164 union { /* PSC + 0x0c */ 165 u8 buffer_8; 166 u16 buffer_16; 167 u32 buffer_32; 168 } buffer; 169#define mpc52xx_psc_buffer_8 buffer.buffer_8 170#define mpc52xx_psc_buffer_16 buffer.buffer_16 171#define mpc52xx_psc_buffer_32 buffer.buffer_32 172 union { /* PSC + 0x10 */ 173 u8 ipcr; 174 u8 acr; 175 } ipcr_acr; 176#define mpc52xx_psc_ipcr ipcr_acr.ipcr 177#define mpc52xx_psc_acr ipcr_acr.acr 178 u8 reserved3[3]; 179 union { /* PSC + 0x14 */ 180 u16 isr; 181 u16 imr; 182 } isr_imr; 183#define mpc52xx_psc_isr isr_imr.isr 184#define mpc52xx_psc_imr isr_imr.imr 185 u16 reserved4; 186 u8 ctur; /* PSC + 0x18 */ 187 u8 reserved5[3]; 188 u8 ctlr; /* PSC + 0x1c */ 189 u8 reserved6[3]; 190 /* BitClkDiv field of CCR is byte swapped in 191 * the hardware for mpc5200/b compatibility */ 192 u32 ccr; /* PSC + 0x20 */ 193 u32 ac97_slots; /* PSC + 0x24 */ 194 u32 ac97_cmd; /* PSC + 0x28 */ 195 u32 ac97_data; /* PSC + 0x2c */ 196 u8 ivr; /* PSC + 0x30 */ 197 u8 reserved8[3]; 198 u8 ip; /* PSC + 0x34 */ 199 u8 reserved9[3]; 200 u8 op1; /* PSC + 0x38 */ 201 u8 reserved10[3]; 202 u8 op0; /* PSC + 0x3c */ 203 u8 reserved11[3]; 204 u32 sicr; /* PSC + 0x40 */ 205 u8 ircr1; /* PSC + 0x44 */ 206 u8 reserved13[3]; 207 u8 ircr2; /* PSC + 0x44 */ 208 u8 reserved14[3]; 209 u8 irsdr; /* PSC + 0x4c */ 210 u8 reserved15[3]; 211 u8 irmdr; /* PSC + 0x50 */ 212 u8 reserved16[3]; 213 u8 irfdr; /* PSC + 0x54 */ 214 u8 reserved17[3]; 215}; 216 217struct mpc52xx_psc_fifo { 218 u16 rfnum; /* PSC + 0x58 */ 219 u16 reserved18; 220 u16 tfnum; /* PSC + 0x5c */ 221 u16 reserved19; 222 u32 rfdata; /* PSC + 0x60 */ 223 u16 rfstat; /* PSC + 0x64 */ 224 u16 reserved20; 225 u8 rfcntl; /* PSC + 0x68 */ 226 u8 reserved21[5]; 227 u16 rfalarm; /* PSC + 0x6e */ 228 u16 reserved22; 229 u16 rfrptr; /* PSC + 0x72 */ 230 u16 reserved23; 231 u16 rfwptr; /* PSC + 0x76 */ 232 u16 reserved24; 233 u16 rflrfptr; /* PSC + 0x7a */ 234 u16 reserved25; 235 u16 rflwfptr; /* PSC + 0x7e */ 236 u32 tfdata; /* PSC + 0x80 */ 237 u16 tfstat; /* PSC + 0x84 */ 238 u16 reserved26; 239 u8 tfcntl; /* PSC + 0x88 */ 240 u8 reserved27[5]; 241 u16 tfalarm; /* PSC + 0x8e */ 242 u16 reserved28; 243 u16 tfrptr; /* PSC + 0x92 */ 244 u16 reserved29; 245 u16 tfwptr; /* PSC + 0x96 */ 246 u16 reserved30; 247 u16 tflrfptr; /* PSC + 0x9a */ 248 u16 reserved31; 249 u16 tflwfptr; /* PSC + 0x9e */ 250}; 251 252#define MPC512x_PSC_FIFO_EOF 0x100 253#define MPC512x_PSC_FIFO_RESET_SLICE 0x80 254#define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01 255#define MPC512x_PSC_FIFO_ENABLE_DMA 0x04 256 257#define MPC512x_PSC_FIFO_EMPTY 0x1 258#define MPC512x_PSC_FIFO_FULL 0x2 259#define MPC512x_PSC_FIFO_ALARM 0x4 260#define MPC512x_PSC_FIFO_URERR 0x8 261#define MPC512x_PSC_FIFO_ORERR 0x01 262#define MPC512x_PSC_FIFO_MEMERROR 0x02 263 264struct mpc512x_psc_fifo { 265 u32 reserved1[10]; 266 u32 txcmd; /* PSC + 0x80 */ 267 u32 txalarm; /* PSC + 0x84 */ 268 u32 txsr; /* PSC + 0x88 */ 269 u32 txisr; /* PSC + 0x8c */ 270 u32 tximr; /* PSC + 0x90 */ 271 u32 txcnt; /* PSC + 0x94 */ 272 u32 txptr; /* PSC + 0x98 */ 273 u32 txsz; /* PSC + 0x9c */ 274 u32 reserved2[7]; 275 union { 276 u8 txdata_8; 277 u16 txdata_16; 278 u32 txdata_32; 279 } txdata; /* PSC + 0xbc */ 280#define txdata_8 txdata.txdata_8 281#define txdata_16 txdata.txdata_16 282#define txdata_32 txdata.txdata_32 283 u32 rxcmd; /* PSC + 0xc0 */ 284 u32 rxalarm; /* PSC + 0xc4 */ 285 u32 rxsr; /* PSC + 0xc8 */ 286 u32 rxisr; /* PSC + 0xcc */ 287 u32 rximr; /* PSC + 0xd0 */ 288 u32 rxcnt; /* PSC + 0xd4 */ 289 u32 rxptr; /* PSC + 0xd8 */ 290 u32 rxsz; /* PSC + 0xdc */ 291 u32 reserved3[7]; 292 union { 293 u8 rxdata_8; 294 u16 rxdata_16; 295 u32 rxdata_32; 296 } rxdata; /* PSC + 0xfc */ 297#define rxdata_8 rxdata.rxdata_8 298#define rxdata_16 rxdata.rxdata_16 299#define rxdata_32 rxdata.rxdata_32 300}; 301 302#endif /* __ASM_MPC52xx_PSC_H__ */ 303