1/* 2 * SBC8349E Device Tree Source 3 * 4 * Copyright 2007 Wind River Inc. 5 * 6 * Paul Gortmaker (see MAINTAINERS for contact information) 7 * 8 * -based largely on the Freescale MPC834x_MDS dts. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16/dts-v1/; 17 18/ { 19 model = "SBC8349E"; 20 compatible = "SBC834xE"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 aliases { 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 serial0 = &serial0; 28 serial1 = &serial1; 29 pci0 = &pci0; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 PowerPC,8349@0 { 37 device_type = "cpu"; 38 reg = <0x0>; 39 d-cache-line-size = <32>; 40 i-cache-line-size = <32>; 41 d-cache-size = <32768>; 42 i-cache-size = <32768>; 43 timebase-frequency = <0>; // from bootloader 44 bus-frequency = <0>; // from bootloader 45 clock-frequency = <0>; // from bootloader 46 }; 47 }; 48 49 memory { 50 device_type = "memory"; 51 reg = <0x00000000 0x10000000>; // 256MB at 0 52 }; 53 54 soc8349@e0000000 { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 device_type = "soc"; 58 ranges = <0x0 0xe0000000 0x00100000>; 59 reg = <0xe0000000 0x00000200>; 60 bus-frequency = <0>; 61 62 wdt@200 { 63 compatible = "mpc83xx_wdt"; 64 reg = <0x200 0x100>; 65 }; 66 67 i2c@3000 { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 cell-index = <0>; 71 compatible = "fsl-i2c"; 72 reg = <0x3000 0x100>; 73 interrupts = <14 0x8>; 74 interrupt-parent = <&ipic>; 75 dfsrr; 76 }; 77 78 i2c@3100 { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 cell-index = <1>; 82 compatible = "fsl-i2c"; 83 reg = <0x3100 0x100>; 84 interrupts = <15 0x8>; 85 interrupt-parent = <&ipic>; 86 dfsrr; 87 }; 88 89 spi@7000 { 90 cell-index = <0>; 91 compatible = "fsl,spi"; 92 reg = <0x7000 0x1000>; 93 interrupts = <16 0x8>; 94 interrupt-parent = <&ipic>; 95 mode = "cpu"; 96 }; 97 98 dma@82a8 { 99 #address-cells = <1>; 100 #size-cells = <1>; 101 compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; 102 reg = <0x82a8 4>; 103 ranges = <0 0x8100 0x1a8>; 104 interrupt-parent = <&ipic>; 105 interrupts = <71 8>; 106 cell-index = <0>; 107 dma-channel@0 { 108 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 109 reg = <0 0x80>; 110 cell-index = <0>; 111 interrupt-parent = <&ipic>; 112 interrupts = <71 8>; 113 }; 114 dma-channel@80 { 115 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 116 reg = <0x80 0x80>; 117 cell-index = <1>; 118 interrupt-parent = <&ipic>; 119 interrupts = <71 8>; 120 }; 121 dma-channel@100 { 122 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 123 reg = <0x100 0x80>; 124 cell-index = <2>; 125 interrupt-parent = <&ipic>; 126 interrupts = <71 8>; 127 }; 128 dma-channel@180 { 129 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 130 reg = <0x180 0x28>; 131 cell-index = <3>; 132 interrupt-parent = <&ipic>; 133 interrupts = <71 8>; 134 }; 135 }; 136 137 /* phy type (ULPI or SERIAL) are only types supported for MPH */ 138 /* port = 0 or 1 */ 139 usb@22000 { 140 compatible = "fsl-usb2-mph"; 141 reg = <0x22000 0x1000>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 interrupt-parent = <&ipic>; 145 interrupts = <39 0x8>; 146 phy_type = "ulpi"; 147 port0; 148 }; 149 150 enet0: ethernet@24000 { 151 #address-cells = <1>; 152 #size-cells = <1>; 153 cell-index = <0>; 154 device_type = "network"; 155 model = "TSEC"; 156 compatible = "gianfar"; 157 reg = <0x24000 0x1000>; 158 ranges = <0x0 0x24000 0x1000>; 159 local-mac-address = [ 00 00 00 00 00 00 ]; 160 interrupts = <32 0x8 33 0x8 34 0x8>; 161 interrupt-parent = <&ipic>; 162 tbi-handle = <&tbi0>; 163 phy-handle = <&phy0>; 164 linux,network-index = <0>; 165 166 mdio@520 { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 compatible = "fsl,gianfar-mdio"; 170 reg = <0x520 0x20>; 171 172 phy0: ethernet-phy@19 { 173 interrupt-parent = <&ipic>; 174 interrupts = <20 0x8>; 175 reg = <0x19>; 176 device_type = "ethernet-phy"; 177 }; 178 179 phy1: ethernet-phy@1a { 180 interrupt-parent = <&ipic>; 181 interrupts = <21 0x8>; 182 reg = <0x1a>; 183 device_type = "ethernet-phy"; 184 }; 185 186 tbi0: tbi-phy@11 { 187 reg = <0x11>; 188 device_type = "tbi-phy"; 189 }; 190 }; 191 }; 192 193 enet1: ethernet@25000 { 194 #address-cells = <1>; 195 #size-cells = <1>; 196 cell-index = <1>; 197 device_type = "network"; 198 model = "TSEC"; 199 compatible = "gianfar"; 200 reg = <0x25000 0x1000>; 201 ranges = <0x0 0x25000 0x1000>; 202 local-mac-address = [ 00 00 00 00 00 00 ]; 203 interrupts = <35 0x8 36 0x8 37 0x8>; 204 interrupt-parent = <&ipic>; 205 tbi-handle = <&tbi1>; 206 phy-handle = <&phy1>; 207 linux,network-index = <1>; 208 209 mdio@520 { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 compatible = "fsl,gianfar-tbi"; 213 reg = <0x520 0x20>; 214 215 tbi1: tbi-phy@11 { 216 reg = <0x11>; 217 device_type = "tbi-phy"; 218 }; 219 }; 220 }; 221 222 serial0: serial@4500 { 223 cell-index = <0>; 224 device_type = "serial"; 225 compatible = "ns16550"; 226 reg = <0x4500 0x100>; 227 clock-frequency = <0>; 228 interrupts = <9 0x8>; 229 interrupt-parent = <&ipic>; 230 }; 231 232 serial1: serial@4600 { 233 cell-index = <1>; 234 device_type = "serial"; 235 compatible = "ns16550"; 236 reg = <0x4600 0x100>; 237 clock-frequency = <0>; 238 interrupts = <10 0x8>; 239 interrupt-parent = <&ipic>; 240 }; 241 242 crypto@30000 { 243 compatible = "fsl,sec2.0"; 244 reg = <0x30000 0x10000>; 245 interrupts = <11 0x8>; 246 interrupt-parent = <&ipic>; 247 fsl,num-channels = <4>; 248 fsl,channel-fifo-len = <24>; 249 fsl,exec-units-mask = <0x7e>; 250 fsl,descriptor-types-mask = <0x01010ebf>; 251 }; 252 253 /* IPIC 254 * interrupts cell = <intr #, sense> 255 * sense values match linux IORESOURCE_IRQ_* defines: 256 * sense == 8: Level, low assertion 257 * sense == 2: Edge, high-to-low change 258 */ 259 ipic: pic@700 { 260 interrupt-controller; 261 #address-cells = <0>; 262 #interrupt-cells = <2>; 263 reg = <0x700 0x100>; 264 device_type = "ipic"; 265 }; 266 }; 267 268 localbus@e0005000 { 269 #address-cells = <2>; 270 #size-cells = <1>; 271 compatible = "fsl,mpc8349-localbus", "simple-bus"; 272 reg = <0xe0005000 0x1000>; 273 interrupts = <77 0x8>; 274 interrupt-parent = <&ipic>; 275 ranges = <0x0 0x0 0xff800000 0x00800000 /* 8MB Flash */ 276 0x1 0x0 0xf8000000 0x00002000 /* 8KB EEPROM */ 277 0x2 0x0 0x10000000 0x04000000 /* 64MB SDRAM */ 278 0x3 0x0 0x10000000 0x04000000>; /* 64MB SDRAM */ 279 280 flash@0,0 { 281 #address-cells = <1>; 282 #size-cells = <1>; 283 compatible = "intel,28F640J3A", "cfi-flash"; 284 reg = <0x0 0x0 0x800000>; 285 bank-width = <2>; 286 device-width = <1>; 287 288 partition@0 { 289 label = "u-boot"; 290 reg = <0x00000000 0x00040000>; 291 read-only; 292 }; 293 294 partition@40000 { 295 label = "user"; 296 reg = <0x00040000 0x006c0000>; 297 }; 298 299 partition@700000 { 300 label = "legacy u-boot"; 301 reg = <0x00700000 0x00100000>; 302 read-only; 303 }; 304 305 }; 306 }; 307 308 pci0: pci@e0008500 { 309 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 310 interrupt-map = < 311 312 /* IDSEL 0x11 */ 313 0x8800 0x0 0x0 0x1 &ipic 48 0x8 314 0x8800 0x0 0x0 0x2 &ipic 17 0x8 315 0x8800 0x0 0x0 0x3 &ipic 18 0x8 316 0x8800 0x0 0x0 0x4 &ipic 19 0x8>; 317 318 interrupt-parent = <&ipic>; 319 interrupts = <0x42 0x8>; 320 bus-range = <0 0>; 321 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 322 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 323 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 324 clock-frequency = <66666666>; 325 #interrupt-cells = <1>; 326 #size-cells = <2>; 327 #address-cells = <3>; 328 reg = <0xe0008500 0x100 /* internal registers */ 329 0xe0008300 0x8>; /* config space access registers */ 330 compatible = "fsl,mpc8349-pci"; 331 device_type = "pci"; 332 }; 333}; 334