1/* Device Tree Source for Motorola PrPMC2800 2 * 3 * Author: Mark A. Greer <mgreer@mvista.com> 4 * 5 * 2007 (c) MontaVista, Software, Inc. This file is licensed under 6 * the terms of the GNU General Public License version 2. This program 7 * is licensed "as is" without any warranty of any kind, whether express 8 * or implied. 9 * 10 * Property values that are labeled as "Default" will be updated by bootwrapper 11 * if it can determine the exact PrPMC type. 12 */ 13 14/dts-v1/; 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 model = "PrPMC280/PrPMC2800"; /* Default */ 20 compatible = "motorola,PrPMC2800"; 21 coherency-off; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 PowerPC,7447 { 28 device_type = "cpu"; 29 reg = <0>; 30 clock-frequency = <733333333>; /* Default */ 31 bus-frequency = <133333333>; 32 timebase-frequency = <33333333>; 33 i-cache-line-size = <32>; 34 d-cache-line-size = <32>; 35 i-cache-size = <32768>; 36 d-cache-size = <32768>; 37 }; 38 }; 39 40 memory { 41 device_type = "memory"; 42 reg = <0x0 0x20000000>; /* Default (512MB) */ 43 }; 44 45 system-controller@f1000000 { /* Marvell Discovery mv64360 */ 46 #address-cells = <1>; 47 #size-cells = <1>; 48 model = "mv64360"; /* Default */ 49 compatible = "marvell,mv64360"; 50 clock-frequency = <133333333>; 51 reg = <0xf1000000 0x10000>; 52 virtual-reg = <0xf1000000>; 53 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ 54 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ 55 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ 56 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ 57 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ 58 59 flash@a0000000 { 60 device_type = "rom"; 61 compatible = "direct-mapped"; 62 reg = <0xa0000000 0x4000000>; /* Default (64MB) */ 63 probe-type = "CFI"; 64 bank-width = <4>; 65 partitions = <0x00000000 0x00100000 /* RO */ 66 0x00100000 0x00040001 /* RW */ 67 0x00140000 0x00400000 /* RO */ 68 0x00540000 0x039c0000 /* RO */ 69 0x03f00000 0x00100000>; /* RO */ 70 partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B"; 71 }; 72 73 mdio { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 device_type = "mdio"; 77 compatible = "marvell,mv64360-mdio"; 78 PHY0: ethernet-phy@1 { 79 device_type = "ethernet-phy"; 80 compatible = "broadcom,bcm5421"; 81 interrupts = <76>; /* GPP 12 */ 82 interrupt-parent = <&PIC>; 83 reg = <1>; 84 }; 85 PHY1: ethernet-phy@3 { 86 device_type = "ethernet-phy"; 87 compatible = "broadcom,bcm5421"; 88 interrupts = <76>; /* GPP 12 */ 89 interrupt-parent = <&PIC>; 90 reg = <3>; 91 }; 92 }; 93 94 ethernet-group@2000 { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 compatible = "marvell,mv64360-eth-group"; 98 reg = <0x2000 0x2000>; 99 ethernet@0 { 100 device_type = "network"; 101 compatible = "marvell,mv64360-eth"; 102 reg = <0>; 103 interrupts = <32>; 104 interrupt-parent = <&PIC>; 105 phy = <&PHY0>; 106 local-mac-address = [ 00 00 00 00 00 00 ]; 107 }; 108 ethernet@1 { 109 device_type = "network"; 110 compatible = "marvell,mv64360-eth"; 111 reg = <1>; 112 interrupts = <33>; 113 interrupt-parent = <&PIC>; 114 phy = <&PHY1>; 115 local-mac-address = [ 00 00 00 00 00 00 ]; 116 }; 117 }; 118 119 SDMA0: sdma@4000 { 120 compatible = "marvell,mv64360-sdma"; 121 reg = <0x4000 0xc18>; 122 virtual-reg = <0xf1004000>; 123 interrupts = <36>; 124 interrupt-parent = <&PIC>; 125 }; 126 127 SDMA1: sdma@6000 { 128 compatible = "marvell,mv64360-sdma"; 129 reg = <0x6000 0xc18>; 130 virtual-reg = <0xf1006000>; 131 interrupts = <38>; 132 interrupt-parent = <&PIC>; 133 }; 134 135 BRG0: brg@b200 { 136 compatible = "marvell,mv64360-brg"; 137 reg = <0xb200 0x8>; 138 clock-src = <8>; 139 clock-frequency = <133333333>; 140 current-speed = <9600>; 141 }; 142 143 BRG1: brg@b208 { 144 compatible = "marvell,mv64360-brg"; 145 reg = <0xb208 0x8>; 146 clock-src = <8>; 147 clock-frequency = <133333333>; 148 current-speed = <9600>; 149 }; 150 151 CUNIT: cunit@f200 { 152 reg = <0xf200 0x200>; 153 }; 154 155 MPSCROUTING: mpscrouting@b400 { 156 reg = <0xb400 0xc>; 157 }; 158 159 MPSCINTR: mpscintr@b800 { 160 reg = <0xb800 0x100>; 161 virtual-reg = <0xf100b800>; 162 }; 163 164 MPSC0: mpsc@8000 { 165 device_type = "serial"; 166 compatible = "marvell,mv64360-mpsc"; 167 reg = <0x8000 0x38>; 168 virtual-reg = <0xf1008000>; 169 sdma = <&SDMA0>; 170 brg = <&BRG0>; 171 cunit = <&CUNIT>; 172 mpscrouting = <&MPSCROUTING>; 173 mpscintr = <&MPSCINTR>; 174 cell-index = <0>; 175 interrupts = <40>; 176 interrupt-parent = <&PIC>; 177 }; 178 179 MPSC1: mpsc@9000 { 180 device_type = "serial"; 181 compatible = "marvell,mv64360-mpsc"; 182 reg = <0x9000 0x38>; 183 virtual-reg = <0xf1009000>; 184 sdma = <&SDMA1>; 185 brg = <&BRG1>; 186 cunit = <&CUNIT>; 187 mpscrouting = <&MPSCROUTING>; 188 mpscintr = <&MPSCINTR>; 189 cell-index = <1>; 190 interrupts = <42>; 191 interrupt-parent = <&PIC>; 192 }; 193 194 wdt@b410 { /* watchdog timer */ 195 compatible = "marvell,mv64360-wdt"; 196 reg = <0xb410 0x8>; 197 }; 198 199 i2c@c000 { 200 device_type = "i2c"; 201 compatible = "marvell,mv64360-i2c"; 202 reg = <0xc000 0x20>; 203 virtual-reg = <0xf100c000>; 204 interrupts = <37>; 205 interrupt-parent = <&PIC>; 206 }; 207 208 PIC: pic { 209 #interrupt-cells = <1>; 210 #address-cells = <0>; 211 compatible = "marvell,mv64360-pic"; 212 reg = <0x0 0x88>; 213 interrupt-controller; 214 }; 215 216 mpp@f000 { 217 compatible = "marvell,mv64360-mpp"; 218 reg = <0xf000 0x10>; 219 }; 220 221 gpp@f100 { 222 compatible = "marvell,mv64360-gpp"; 223 reg = <0xf100 0x20>; 224 }; 225 226 pci@80000000 { 227 #address-cells = <3>; 228 #size-cells = <2>; 229 #interrupt-cells = <1>; 230 device_type = "pci"; 231 compatible = "marvell,mv64360-pci"; 232 reg = <0xcf8 0x8>; 233 ranges = <0x01000000 0x0 0x0 234 0x88000000 0x0 0x01000000 235 0x02000000 0x0 0x80000000 236 0x80000000 0x0 0x08000000>; 237 bus-range = <0 255>; 238 clock-frequency = <66000000>; 239 interrupt-pci-iack = <0xc34>; 240 interrupt-parent = <&PIC>; 241 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 242 interrupt-map = < 243 /* IDSEL 0x0a */ 244 0x5000 0 0 1 &PIC 80 245 0x5000 0 0 2 &PIC 81 246 0x5000 0 0 3 &PIC 91 247 0x5000 0 0 4 &PIC 93 248 249 /* IDSEL 0x0b */ 250 0x5800 0 0 1 &PIC 91 251 0x5800 0 0 2 &PIC 93 252 0x5800 0 0 3 &PIC 80 253 0x5800 0 0 4 &PIC 81 254 255 /* IDSEL 0x0c */ 256 0x6000 0 0 1 &PIC 91 257 0x6000 0 0 2 &PIC 93 258 0x6000 0 0 3 &PIC 80 259 0x6000 0 0 4 &PIC 81 260 261 /* IDSEL 0x0d */ 262 0x6800 0 0 1 &PIC 93 263 0x6800 0 0 2 &PIC 80 264 0x6800 0 0 3 &PIC 81 265 0x6800 0 0 4 &PIC 91 266 >; 267 }; 268 269 cpu-error@0070 { 270 compatible = "marvell,mv64360-cpu-error"; 271 reg = <0x70 0x10 0x128 0x28>; 272 interrupts = <3>; 273 interrupt-parent = <&PIC>; 274 }; 275 276 sram-ctrl@0380 { 277 compatible = "marvell,mv64360-sram-ctrl"; 278 reg = <0x380 0x80>; 279 interrupts = <13>; 280 interrupt-parent = <&PIC>; 281 }; 282 283 pci-error@1d40 { 284 compatible = "marvell,mv64360-pci-error"; 285 reg = <0x1d40 0x40 0xc28 0x4>; 286 interrupts = <12>; 287 interrupt-parent = <&PIC>; 288 }; 289 290 mem-ctrl@1400 { 291 compatible = "marvell,mv64360-mem-ctrl"; 292 reg = <0x1400 0x60>; 293 interrupts = <17>; 294 interrupt-parent = <&PIC>; 295 }; 296 }; 297 298 chosen { 299 bootargs = "ip=on"; 300 linux,stdout-path = &MPSC0; 301 }; 302}; 303