1/* 2 * P4080DS Device Tree Source 3 * 4 * Copyright 2009 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "fsl,P4080DS"; 16 compatible = "fsl,P4080DS"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ccsr = &soc; 22 23 serial0 = &serial0; 24 serial1 = &serial1; 25 serial2 = &serial2; 26 serial3 = &serial3; 27 pci0 = &pci0; 28 pci1 = &pci1; 29 pci2 = &pci2; 30 usb0 = &usb0; 31 usb1 = &usb1; 32 dma0 = &dma0; 33 dma1 = &dma1; 34 sdhc = &sdhc; 35 36 rio0 = &rapidio0; 37 }; 38 39 cpus { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 43 cpu0: PowerPC,4080@0 { 44 device_type = "cpu"; 45 reg = <0>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 }; 49 }; 50 cpu1: PowerPC,4080@1 { 51 device_type = "cpu"; 52 reg = <1>; 53 next-level-cache = <&L2_1>; 54 L2_1: l2-cache { 55 }; 56 }; 57 cpu2: PowerPC,4080@2 { 58 device_type = "cpu"; 59 reg = <2>; 60 next-level-cache = <&L2_2>; 61 L2_2: l2-cache { 62 }; 63 }; 64 cpu3: PowerPC,4080@3 { 65 device_type = "cpu"; 66 reg = <3>; 67 next-level-cache = <&L2_3>; 68 L2_3: l2-cache { 69 }; 70 }; 71 cpu4: PowerPC,4080@4 { 72 device_type = "cpu"; 73 reg = <4>; 74 next-level-cache = <&L2_4>; 75 L2_4: l2-cache { 76 }; 77 }; 78 cpu5: PowerPC,4080@5 { 79 device_type = "cpu"; 80 reg = <5>; 81 next-level-cache = <&L2_5>; 82 L2_5: l2-cache { 83 }; 84 }; 85 cpu6: PowerPC,4080@6 { 86 device_type = "cpu"; 87 reg = <6>; 88 next-level-cache = <&L2_6>; 89 L2_6: l2-cache { 90 }; 91 }; 92 cpu7: PowerPC,4080@7 { 93 device_type = "cpu"; 94 reg = <7>; 95 next-level-cache = <&L2_7>; 96 L2_7: l2-cache { 97 }; 98 }; 99 }; 100 101 memory { 102 device_type = "memory"; 103 }; 104 105 soc: soc@ffe000000 { 106 #address-cells = <1>; 107 #size-cells = <1>; 108 device_type = "soc"; 109 compatible = "simple-bus"; 110 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 111 reg = <0xf 0xfe000000 0 0x00001000>; 112 113 corenet-law@0 { 114 compatible = "fsl,corenet-law"; 115 reg = <0x0 0x1000>; 116 fsl,num-laws = <32>; 117 }; 118 119 memory-controller@8000 { 120 compatible = "fsl,p4080-memory-controller"; 121 reg = <0x8000 0x1000>; 122 interrupt-parent = <&mpic>; 123 interrupts = <0x12 2>; 124 }; 125 126 memory-controller@9000 { 127 compatible = "fsl,p4080-memory-controller"; 128 reg = <0x9000 0x1000>; 129 interrupt-parent = <&mpic>; 130 interrupts = <0x12 2>; 131 }; 132 133 corenet-cf@18000 { 134 compatible = "fsl,corenet-cf"; 135 reg = <0x18000 0x1000>; 136 fsl,ccf-num-csdids = <32>; 137 fsl,ccf-num-snoopids = <32>; 138 }; 139 140 iommu@20000 { 141 compatible = "fsl,p4080-pamu"; 142 reg = <0x20000 0x10000>; 143 interrupts = <24 2>; 144 interrupt-parent = <&mpic>; 145 }; 146 147 mpic: pic@40000 { 148 interrupt-controller; 149 #address-cells = <0>; 150 #interrupt-cells = <2>; 151 reg = <0x40000 0x40000>; 152 compatible = "chrp,open-pic"; 153 device_type = "open-pic"; 154 }; 155 156 dma0: dma@100300 { 157 #address-cells = <1>; 158 #size-cells = <1>; 159 compatible = "fsl,p4080-dma", "fsl,eloplus-dma"; 160 reg = <0x100300 0x4>; 161 ranges = <0x0 0x100100 0x200>; 162 cell-index = <0>; 163 dma-channel@0 { 164 compatible = "fsl,p4080-dma-channel", 165 "fsl,eloplus-dma-channel"; 166 reg = <0x0 0x80>; 167 cell-index = <0>; 168 interrupt-parent = <&mpic>; 169 interrupts = <28 2>; 170 }; 171 dma-channel@80 { 172 compatible = "fsl,p4080-dma-channel", 173 "fsl,eloplus-dma-channel"; 174 reg = <0x80 0x80>; 175 cell-index = <1>; 176 interrupt-parent = <&mpic>; 177 interrupts = <29 2>; 178 }; 179 dma-channel@100 { 180 compatible = "fsl,p4080-dma-channel", 181 "fsl,eloplus-dma-channel"; 182 reg = <0x100 0x80>; 183 cell-index = <2>; 184 interrupt-parent = <&mpic>; 185 interrupts = <30 2>; 186 }; 187 dma-channel@180 { 188 compatible = "fsl,p4080-dma-channel", 189 "fsl,eloplus-dma-channel"; 190 reg = <0x180 0x80>; 191 cell-index = <3>; 192 interrupt-parent = <&mpic>; 193 interrupts = <31 2>; 194 }; 195 }; 196 197 dma1: dma@101300 { 198 #address-cells = <1>; 199 #size-cells = <1>; 200 compatible = "fsl,p4080-dma", "fsl,eloplus-dma"; 201 reg = <0x101300 0x4>; 202 ranges = <0x0 0x101100 0x200>; 203 cell-index = <1>; 204 dma-channel@0 { 205 compatible = "fsl,p4080-dma-channel", 206 "fsl,eloplus-dma-channel"; 207 reg = <0x0 0x80>; 208 cell-index = <0>; 209 interrupt-parent = <&mpic>; 210 interrupts = <32 2>; 211 }; 212 dma-channel@80 { 213 compatible = "fsl,p4080-dma-channel", 214 "fsl,eloplus-dma-channel"; 215 reg = <0x80 0x80>; 216 cell-index = <1>; 217 interrupt-parent = <&mpic>; 218 interrupts = <33 2>; 219 }; 220 dma-channel@100 { 221 compatible = "fsl,p4080-dma-channel", 222 "fsl,eloplus-dma-channel"; 223 reg = <0x100 0x80>; 224 cell-index = <2>; 225 interrupt-parent = <&mpic>; 226 interrupts = <34 2>; 227 }; 228 dma-channel@180 { 229 compatible = "fsl,p4080-dma-channel", 230 "fsl,eloplus-dma-channel"; 231 reg = <0x180 0x80>; 232 cell-index = <3>; 233 interrupt-parent = <&mpic>; 234 interrupts = <35 2>; 235 }; 236 }; 237 238 spi@110000 { 239 cell-index = <0>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 compatible = "fsl,espi"; 243 reg = <0x110000 0x1000>; 244 interrupts = <53 0x2>; 245 interrupt-parent = <&mpic>; 246 espi,num-ss-bits = <4>; 247 mode = "cpu"; 248 249 fsl_m25p80@0 { 250 #address-cells = <1>; 251 #size-cells = <1>; 252 compatible = "fsl,espi-flash"; 253 reg = <0>; 254 linux,modalias = "fsl_m25p80"; 255 spi-max-frequency = <40000000>; /* input clock */ 256 partition@u-boot { 257 label = "u-boot"; 258 reg = <0x00000000 0x00100000>; 259 read-only; 260 }; 261 partition@kernel { 262 label = "kernel"; 263 reg = <0x00100000 0x00500000>; 264 read-only; 265 }; 266 partition@dtb { 267 label = "dtb"; 268 reg = <0x00600000 0x00100000>; 269 read-only; 270 }; 271 partition@fs { 272 label = "file system"; 273 reg = <0x00700000 0x00900000>; 274 }; 275 }; 276 }; 277 278 sdhc: sdhc@114000 { 279 compatible = "fsl,p4080-esdhc", "fsl,esdhc"; 280 reg = <0x114000 0x1000>; 281 interrupts = <48 2>; 282 interrupt-parent = <&mpic>; 283 voltage-ranges = <3300 3300>; 284 sdhci,auto-cmd12; 285 }; 286 287 i2c@118000 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 cell-index = <0>; 291 compatible = "fsl-i2c"; 292 reg = <0x118000 0x100>; 293 interrupts = <38 2>; 294 interrupt-parent = <&mpic>; 295 dfsrr; 296 }; 297 298 i2c@118100 { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 cell-index = <1>; 302 compatible = "fsl-i2c"; 303 reg = <0x118100 0x100>; 304 interrupts = <38 2>; 305 interrupt-parent = <&mpic>; 306 dfsrr; 307 eeprom@51 { 308 compatible = "at24,24c256"; 309 reg = <0x51>; 310 }; 311 eeprom@52 { 312 compatible = "at24,24c256"; 313 reg = <0x52>; 314 }; 315 rtc@68 { 316 compatible = "dallas,ds3232"; 317 reg = <0x68>; 318 interrupts = <0 0x1>; 319 interrupt-parent = <&mpic>; 320 }; 321 }; 322 323 i2c@119000 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 cell-index = <2>; 327 compatible = "fsl-i2c"; 328 reg = <0x119000 0x100>; 329 interrupts = <39 2>; 330 interrupt-parent = <&mpic>; 331 dfsrr; 332 }; 333 334 i2c@119100 { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 cell-index = <3>; 338 compatible = "fsl-i2c"; 339 reg = <0x119100 0x100>; 340 interrupts = <39 2>; 341 interrupt-parent = <&mpic>; 342 dfsrr; 343 }; 344 345 serial0: serial@11c500 { 346 cell-index = <0>; 347 device_type = "serial"; 348 compatible = "ns16550"; 349 reg = <0x11c500 0x100>; 350 clock-frequency = <0>; 351 interrupts = <36 2>; 352 interrupt-parent = <&mpic>; 353 }; 354 355 serial1: serial@11c600 { 356 cell-index = <1>; 357 device_type = "serial"; 358 compatible = "ns16550"; 359 reg = <0x11c600 0x100>; 360 clock-frequency = <0>; 361 interrupts = <36 2>; 362 interrupt-parent = <&mpic>; 363 }; 364 365 serial2: serial@11d500 { 366 cell-index = <2>; 367 device_type = "serial"; 368 compatible = "ns16550"; 369 reg = <0x11d500 0x100>; 370 clock-frequency = <0>; 371 interrupts = <37 2>; 372 interrupt-parent = <&mpic>; 373 }; 374 375 serial3: serial@11d600 { 376 cell-index = <3>; 377 device_type = "serial"; 378 compatible = "ns16550"; 379 reg = <0x11d600 0x100>; 380 clock-frequency = <0>; 381 interrupts = <37 2>; 382 interrupt-parent = <&mpic>; 383 }; 384 385 gpio0: gpio@130000 { 386 compatible = "fsl,p4080-gpio"; 387 reg = <0x130000 0x1000>; 388 interrupts = <55 2>; 389 interrupt-parent = <&mpic>; 390 #gpio-cells = <2>; 391 gpio-controller; 392 }; 393 394 usb0: usb@210000 { 395 compatible = "fsl,p4080-usb2-mph", 396 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 397 reg = <0x210000 0x1000>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 interrupt-parent = <&mpic>; 401 interrupts = <44 0x2>; 402 phy_type = "ulpi"; 403 }; 404 405 usb1: usb@211000 { 406 compatible = "fsl,p4080-usb2-dr", 407 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 408 reg = <0x211000 0x1000>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 interrupt-parent = <&mpic>; 412 interrupts = <45 0x2>; 413 dr_mode = "host"; 414 phy_type = "ulpi"; 415 }; 416 }; 417 418 rapidio0: rapidio@ffe0c0000 { 419 #address-cells = <2>; 420 #size-cells = <2>; 421 compatible = "fsl,rapidio-delta"; 422 reg = <0xf 0xfe0c0000 0 0x20000>; 423 ranges = <0 0 0xf 0xf5000000 0 0x01000000>; 424 interrupt-parent = <&mpic>; 425 /* err_irq bell_outb_irq bell_inb_irq 426 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */ 427 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>; 428 }; 429 430 localbus@ffe124000 { 431 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus"; 432 reg = <0xf 0xfe124000 0 0x1000>; 433 interrupts = <25 2>; 434 #address-cells = <2>; 435 #size-cells = <1>; 436 437 ranges = <0 0 0xf 0xe8000000 0x08000000>; 438 439 flash@0,0 { 440 compatible = "cfi-flash"; 441 reg = <0 0 0x08000000>; 442 bank-width = <2>; 443 device-width = <2>; 444 }; 445 }; 446 447 pci0: pcie@ffe200000 { 448 compatible = "fsl,p4080-pcie"; 449 device_type = "pci"; 450 #interrupt-cells = <1>; 451 #size-cells = <2>; 452 #address-cells = <3>; 453 reg = <0xf 0xfe200000 0 0x1000>; 454 bus-range = <0x0 0xff>; 455 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 456 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 457 clock-frequency = <0x1fca055>; 458 interrupt-parent = <&mpic>; 459 interrupts = <16 2>; 460 461 interrupt-map-mask = <0xf800 0 0 7>; 462 interrupt-map = < 463 /* IDSEL 0x0 */ 464 0000 0 0 1 &mpic 40 1 465 0000 0 0 2 &mpic 1 1 466 0000 0 0 3 &mpic 2 1 467 0000 0 0 4 &mpic 3 1 468 >; 469 pcie@0 { 470 reg = <0 0 0 0 0>; 471 #size-cells = <2>; 472 #address-cells = <3>; 473 device_type = "pci"; 474 ranges = <0x02000000 0 0xe0000000 475 0x02000000 0 0xe0000000 476 0 0x20000000 477 478 0x01000000 0 0x00000000 479 0x01000000 0 0x00000000 480 0 0x00010000>; 481 }; 482 }; 483 484 pci1: pcie@ffe201000 { 485 compatible = "fsl,p4080-pcie"; 486 device_type = "pci"; 487 #interrupt-cells = <1>; 488 #size-cells = <2>; 489 #address-cells = <3>; 490 reg = <0xf 0xfe201000 0 0x1000>; 491 bus-range = <0 0xff>; 492 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 493 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 494 clock-frequency = <0x1fca055>; 495 interrupt-parent = <&mpic>; 496 interrupts = <16 2>; 497 interrupt-map-mask = <0xf800 0 0 7>; 498 interrupt-map = < 499 /* IDSEL 0x0 */ 500 0000 0 0 1 &mpic 41 1 501 0000 0 0 2 &mpic 5 1 502 0000 0 0 3 &mpic 6 1 503 0000 0 0 4 &mpic 7 1 504 >; 505 pcie@0 { 506 reg = <0 0 0 0 0>; 507 #size-cells = <2>; 508 #address-cells = <3>; 509 device_type = "pci"; 510 ranges = <0x02000000 0 0xe0000000 511 0x02000000 0 0xe0000000 512 0 0x20000000 513 514 0x01000000 0 0x00000000 515 0x01000000 0 0x00000000 516 0 0x00010000>; 517 }; 518 }; 519 520 pci2: pcie@ffe202000 { 521 compatible = "fsl,p4080-pcie"; 522 device_type = "pci"; 523 #interrupt-cells = <1>; 524 #size-cells = <2>; 525 #address-cells = <3>; 526 reg = <0xf 0xfe202000 0 0x1000>; 527 bus-range = <0x0 0xff>; 528 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 529 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 530 clock-frequency = <0x1fca055>; 531 interrupt-parent = <&mpic>; 532 interrupts = <16 2>; 533 interrupt-map-mask = <0xf800 0 0 7>; 534 interrupt-map = < 535 /* IDSEL 0x0 */ 536 0000 0 0 1 &mpic 42 1 537 0000 0 0 2 &mpic 9 1 538 0000 0 0 3 &mpic 10 1 539 0000 0 0 4 &mpic 11 1 540 >; 541 pcie@0 { 542 reg = <0 0 0 0 0>; 543 #size-cells = <2>; 544 #address-cells = <3>; 545 device_type = "pci"; 546 ranges = <0x02000000 0 0xe0000000 547 0x02000000 0 0xe0000000 548 0 0x20000000 549 550 0x01000000 0 0x00000000 551 0x01000000 0 0x00000000 552 0 0x00010000>; 553 }; 554 }; 555 556}; 557