1/* 2 * P1021 MDS Device Tree Source 3 * 4 * Copyright 2010 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13/ { 14 model = "fsl,P1021"; 15 compatible = "fsl,P1021MDS"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 serial0 = &serial0; 21 serial1 = &serial1; 22 ethernet0 = &enet0; 23 ethernet1 = &enet1; 24 ethernet2 = &enet2; 25 ethernet3 = &enet3; 26 ethernet4 = &enet4; 27 pci0 = &pci0; 28 pci1 = &pci1; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 PowerPC,P1021@0 { 36 device_type = "cpu"; 37 reg = <0x0>; 38 next-level-cache = <&L2>; 39 }; 40 41 PowerPC,P1021@1 { 42 device_type = "cpu"; 43 reg = <0x1>; 44 next-level-cache = <&L2>; 45 }; 46 }; 47 48 memory { 49 device_type = "memory"; 50 }; 51 52 localbus@ffe05000 { 53 #address-cells = <2>; 54 #size-cells = <1>; 55 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus"; 56 reg = <0 0xffe05000 0 0x1000>; 57 interrupts = <19 2>; 58 interrupt-parent = <&mpic>; 59 60 /* NAND Flash, BCSR, PMC0/1*/ 61 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000 62 0x1 0x0 0x0 0xf8000000 0x00008000 63 0x2 0x0 0x0 0xf8010000 0x00020000 64 0x3 0x0 0x0 0xf8020000 0x00020000>; 65 66 nand@0,0 { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 compatible = "fsl,p1021-fcm-nand", 70 "fsl,elbc-fcm-nand"; 71 reg = <0x0 0x0 0x40000>; 72 73 partition@0 { 74 /* This location must not be altered */ 75 /* 1MB for u-boot Bootloader Image */ 76 reg = <0x0 0x00100000>; 77 label = "NAND (RO) U-Boot Image"; 78 read-only; 79 }; 80 81 partition@100000 { 82 /* 1MB for DTB Image */ 83 reg = <0x00100000 0x00100000>; 84 label = "NAND (RO) DTB Image"; 85 read-only; 86 }; 87 88 partition@200000 { 89 /* 4MB for Linux Kernel Image */ 90 reg = <0x00200000 0x00400000>; 91 label = "NAND (RO) Linux Kernel Image"; 92 read-only; 93 }; 94 95 partition@600000 { 96 /* 5MB for Compressed Root file System Image */ 97 reg = <0x00600000 0x00500000>; 98 label = "NAND (RO) Compressed RFS Image"; 99 read-only; 100 }; 101 102 partition@b00000 { 103 /* 6MB for JFFS2 based Root file System */ 104 reg = <0x00a00000 0x00600000>; 105 label = "NAND (RW) JFFS2 Root File System"; 106 }; 107 108 partition@1100000 { 109 /* 14MB for JFFS2 based Root file System */ 110 reg = <0x01100000 0x00e00000>; 111 label = "NAND (RW) Writable User area"; 112 }; 113 114 partition@1f00000 { 115 /* 1MB for microcode */ 116 reg = <0x01f00000 0x00100000>; 117 label = "NAND (RO) QE Ucode"; 118 read-only; 119 }; 120 }; 121 122 bcsr@1,0 { 123 #address-cells = <1>; 124 #size-cells = <1>; 125 compatible = "fsl,p1021mds-bcsr"; 126 reg = <1 0 0x8000>; 127 ranges = <0 1 0 0x8000>; 128 }; 129 130 pib@2,0 { 131 compatible = "fsl,p1021mds-pib"; 132 reg = <2 0 0x10000>; 133 }; 134 135 pib@3,0 { 136 compatible = "fsl,p1021mds-pib"; 137 reg = <3 0 0x10000>; 138 }; 139 }; 140 141 soc@ffe00000 { 142 143 #address-cells = <1>; 144 #size-cells = <1>; 145 device_type = "soc"; 146 compatible = "fsl,p1021-immr", "simple-bus"; 147 ranges = <0x0 0x0 0xffe00000 0x100000>; 148 bus-frequency = <0>; // Filled out by uboot. 149 150 ecm-law@0 { 151 compatible = "fsl,ecm-law"; 152 reg = <0x0 0x1000>; 153 fsl,num-laws = <12>; 154 }; 155 156 ecm@1000 { 157 compatible = "fsl,p1021-ecm", "fsl,ecm"; 158 reg = <0x1000 0x1000>; 159 interrupts = <16 2>; 160 interrupt-parent = <&mpic>; 161 }; 162 163 memory-controller@2000 { 164 compatible = "fsl,p1021-memory-controller"; 165 reg = <0x2000 0x1000>; 166 interrupt-parent = <&mpic>; 167 interrupts = <16 2>; 168 }; 169 170 i2c@3000 { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 cell-index = <0>; 174 compatible = "fsl-i2c"; 175 reg = <0x3000 0x100>; 176 interrupts = <43 2>; 177 interrupt-parent = <&mpic>; 178 dfsrr; 179 rtc@68 { 180 compatible = "dallas,ds1374"; 181 reg = <0x68>; 182 }; 183 }; 184 185 i2c@3100 { 186 #address-cells = <1>; 187 #size-cells = <0>; 188 cell-index = <1>; 189 compatible = "fsl-i2c"; 190 reg = <0x3100 0x100>; 191 interrupts = <43 2>; 192 interrupt-parent = <&mpic>; 193 dfsrr; 194 }; 195 196 serial0: serial@4500 { 197 cell-index = <0>; 198 device_type = "serial"; 199 compatible = "ns16550"; 200 reg = <0x4500 0x100>; 201 clock-frequency = <0>; 202 interrupts = <42 2>; 203 interrupt-parent = <&mpic>; 204 }; 205 206 serial1: serial@4600 { 207 cell-index = <1>; 208 device_type = "serial"; 209 compatible = "ns16550"; 210 reg = <0x4600 0x100>; 211 clock-frequency = <0>; 212 interrupts = <42 2>; 213 interrupt-parent = <&mpic>; 214 }; 215 216 spi@7000 { 217 cell-index = <0>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 compatible = "fsl,espi"; 221 reg = <0x7000 0x1000>; 222 interrupts = <59 0x2>; 223 interrupt-parent = <&mpic>; 224 espi,num-ss-bits = <4>; 225 mode = "cpu"; 226 227 fsl_m25p80@0 { 228 #address-cells = <1>; 229 #size-cells = <1>; 230 compatible = "fsl,espi-flash"; 231 reg = <0>; 232 linux,modalias = "fsl_m25p80"; 233 spi-max-frequency = <40000000>; /* input clock */ 234 partition@u-boot { 235 label = "u-boot-spi"; 236 reg = <0x00000000 0x00100000>; 237 read-only; 238 }; 239 partition@kernel { 240 label = "kernel-spi"; 241 reg = <0x00100000 0x00500000>; 242 read-only; 243 }; 244 partition@dtb { 245 label = "dtb-spi"; 246 reg = <0x00600000 0x00100000>; 247 read-only; 248 }; 249 partition@fs { 250 label = "file system-spi"; 251 reg = <0x00700000 0x00900000>; 252 }; 253 }; 254 }; 255 256 gpio: gpio-controller@f000 { 257 #gpio-cells = <2>; 258 compatible = "fsl,mpc8572-gpio"; 259 reg = <0xf000 0x100>; 260 interrupts = <47 0x2>; 261 interrupt-parent = <&mpic>; 262 gpio-controller; 263 }; 264 265 L2: l2-cache-controller@20000 { 266 compatible = "fsl,p1021-l2-cache-controller"; 267 reg = <0x20000 0x1000>; 268 cache-line-size = <32>; // 32 bytes 269 cache-size = <0x40000>; // L2,256K 270 interrupt-parent = <&mpic>; 271 interrupts = <16 2>; 272 }; 273 274 dma@21300 { 275 #address-cells = <1>; 276 #size-cells = <1>; 277 compatible = "fsl,eloplus-dma"; 278 reg = <0x21300 0x4>; 279 ranges = <0x0 0x21100 0x200>; 280 cell-index = <0>; 281 dma-channel@0 { 282 compatible = "fsl,eloplus-dma-channel"; 283 reg = <0x0 0x80>; 284 cell-index = <0>; 285 interrupt-parent = <&mpic>; 286 interrupts = <20 2>; 287 }; 288 dma-channel@80 { 289 compatible = "fsl,eloplus-dma-channel"; 290 reg = <0x80 0x80>; 291 cell-index = <1>; 292 interrupt-parent = <&mpic>; 293 interrupts = <21 2>; 294 }; 295 dma-channel@100 { 296 compatible = "fsl,eloplus-dma-channel"; 297 reg = <0x100 0x80>; 298 cell-index = <2>; 299 interrupt-parent = <&mpic>; 300 interrupts = <22 2>; 301 }; 302 dma-channel@180 { 303 compatible = "fsl,eloplus-dma-channel"; 304 reg = <0x180 0x80>; 305 cell-index = <3>; 306 interrupt-parent = <&mpic>; 307 interrupts = <23 2>; 308 }; 309 }; 310 311 usb@22000 { 312 #address-cells = <1>; 313 #size-cells = <0>; 314 compatible = "fsl-usb2-dr"; 315 reg = <0x22000 0x1000>; 316 interrupt-parent = <&mpic>; 317 interrupts = <28 0x2>; 318 phy_type = "ulpi"; 319 }; 320 321 mdio@24000 { 322 #address-cells = <1>; 323 #size-cells = <0>; 324 compatible = "fsl,etsec2-mdio"; 325 reg = <0x24000 0x1000 0xb0030 0x4>; 326 327 phy0: ethernet-phy@0 { 328 interrupt-parent = <&mpic>; 329 interrupts = <1 1>; 330 reg = <0x0>; 331 }; 332 phy1: ethernet-phy@1 { 333 interrupt-parent = <&mpic>; 334 interrupts = <2 1>; 335 reg = <0x1>; 336 }; 337 phy4: ethernet-phy@4 { 338 interrupt-parent = <&mpic>; 339 reg = <0x4>; 340 }; 341 }; 342 343 mdio@25000 { 344 #address-cells = <1>; 345 #size-cells = <0>; 346 compatible = "fsl,etsec2-tbi"; 347 reg = <0x25000 0x1000 0xb1030 0x4>; 348 tbi0: tbi-phy@11 { 349 reg = <0x11>; 350 device_type = "tbi-phy"; 351 }; 352 }; 353 354 enet0: ethernet@B0000 { 355 #address-cells = <1>; 356 #size-cells = <1>; 357 cell-index = <0>; 358 device_type = "network"; 359 model = "eTSEC"; 360 compatible = "fsl,etsec2"; 361 fsl,num_rx_queues = <0x8>; 362 fsl,num_tx_queues = <0x8>; 363 local-mac-address = [ 00 00 00 00 00 00 ]; 364 interrupt-parent = <&mpic>; 365 phy-handle = <&phy0>; 366 phy-connection-type = "rgmii-id"; 367 queue-group@0{ 368 #address-cells = <1>; 369 #size-cells = <1>; 370 reg = <0xB0000 0x1000>; 371 interrupts = <29 2 30 2 34 2>; 372 }; 373 queue-group@1{ 374 #address-cells = <1>; 375 #size-cells = <1>; 376 reg = <0xB4000 0x1000>; 377 interrupts = <17 2 18 2 24 2>; 378 }; 379 }; 380 381 enet1: ethernet@B1000 { 382 #address-cells = <1>; 383 #size-cells = <1>; 384 cell-index = <0>; 385 device_type = "network"; 386 model = "eTSEC"; 387 compatible = "fsl,etsec2"; 388 fsl,num_rx_queues = <0x8>; 389 fsl,num_tx_queues = <0x8>; 390 local-mac-address = [ 00 00 00 00 00 00 ]; 391 interrupt-parent = <&mpic>; 392 phy-handle = <&phy4>; 393 tbi-handle = <&tbi0>; 394 phy-connection-type = "sgmii"; 395 queue-group@0{ 396 #address-cells = <1>; 397 #size-cells = <1>; 398 reg = <0xB1000 0x1000>; 399 interrupts = <35 2 36 2 40 2>; 400 }; 401 queue-group@1{ 402 #address-cells = <1>; 403 #size-cells = <1>; 404 reg = <0xB5000 0x1000>; 405 interrupts = <51 2 52 2 67 2>; 406 }; 407 }; 408 409 enet2: ethernet@B2000 { 410 #address-cells = <1>; 411 #size-cells = <1>; 412 cell-index = <0>; 413 device_type = "network"; 414 model = "eTSEC"; 415 compatible = "fsl,etsec2"; 416 fsl,num_rx_queues = <0x8>; 417 fsl,num_tx_queues = <0x8>; 418 local-mac-address = [ 00 00 00 00 00 00 ]; 419 interrupt-parent = <&mpic>; 420 phy-handle = <&phy1>; 421 phy-connection-type = "rgmii-id"; 422 queue-group@0{ 423 #address-cells = <1>; 424 #size-cells = <1>; 425 reg = <0xB2000 0x1000>; 426 interrupts = <31 2 32 2 33 2>; 427 }; 428 queue-group@1{ 429 #address-cells = <1>; 430 #size-cells = <1>; 431 reg = <0xB6000 0x1000>; 432 interrupts = <25 2 26 2 27 2>; 433 }; 434 }; 435 436 sdhci@2e000 { 437 compatible = "fsl,p1021-esdhc", "fsl,esdhc"; 438 reg = <0x2e000 0x1000>; 439 interrupts = <72 0x2>; 440 interrupt-parent = <&mpic>; 441 /* Filled in by U-Boot */ 442 clock-frequency = <0>; 443 }; 444 445 crypto@30000 { 446 compatible = "fsl,sec3.3", "fsl,sec3.1", 447 "fsl,sec3.0", "fsl,sec2.4", 448 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; 449 reg = <0x30000 0x10000>; 450 interrupts = <45 2 58 2>; 451 interrupt-parent = <&mpic>; 452 fsl,num-channels = <4>; 453 fsl,channel-fifo-len = <24>; 454 fsl,exec-units-mask = <0x97c>; 455 fsl,descriptor-types-mask = <0x3a30abf>; 456 }; 457 458 mpic: pic@40000 { 459 interrupt-controller; 460 #address-cells = <0>; 461 #interrupt-cells = <2>; 462 reg = <0x40000 0x40000>; 463 compatible = "chrp,open-pic"; 464 device_type = "open-pic"; 465 }; 466 467 msi@41600 { 468 compatible = "fsl,p1021-msi", "fsl,mpic-msi"; 469 reg = <0x41600 0x80>; 470 msi-available-ranges = <0 0x100>; 471 interrupts = < 472 0xe0 0 473 0xe1 0 474 0xe2 0 475 0xe3 0 476 0xe4 0 477 0xe5 0 478 0xe6 0 479 0xe7 0>; 480 interrupt-parent = <&mpic>; 481 }; 482 483 global-utilities@e0000 { //global utilities block 484 compatible = "fsl,p1021-guts"; 485 reg = <0xe0000 0x1000>; 486 fsl,has-rstcr; 487 }; 488 489 par_io@e0100 { 490 #address-cells = <1>; 491 #size-cells = <1>; 492 reg = <0xe0100 0x60>; 493 ranges = <0x0 0xe0100 0x60>; 494 device_type = "par_io"; 495 num-ports = <3>; 496 pio1: ucc_pin@01 { 497 pio-map = < 498 /* port pin dir open_drain assignment has_irq */ 499 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 500 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 501 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ 502 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 503*/ 504 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ 505 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ 506 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ 507 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ 508 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */ 509 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */ 510 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ 511 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ 512 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ 513 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */ 514 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */ 515 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */ 516 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */ 517 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */ 518 }; 519 520 pio2: ucc_pin@02 { 521 pio-map = < 522 /* port pin dir open_drain assignment has_irq */ 523 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 524 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 525 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */ 526 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */ 527 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */ 528 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */ 529 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */ 530 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */ 531 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ 532 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ 533 }; 534 }; 535 }; 536 537 pci0: pcie@ffe09000 { 538 compatible = "fsl,mpc8548-pcie"; 539 device_type = "pci"; 540 #interrupt-cells = <1>; 541 #size-cells = <2>; 542 #address-cells = <3>; 543 reg = <0 0xffe09000 0 0x1000>; 544 bus-range = <0 255>; 545 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 546 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 547 clock-frequency = <33333333>; 548 interrupt-parent = <&mpic>; 549 interrupts = <16 2>; 550 interrupt-map-mask = <0xf800 0 0 7>; 551 interrupt-map = < 552 /* IDSEL 0x0 */ 553 0000 0 0 1 &mpic 4 1 554 0000 0 0 2 &mpic 5 1 555 0000 0 0 3 &mpic 6 1 556 0000 0 0 4 &mpic 7 1 557 >; 558 pcie@0 { 559 reg = <0x0 0x0 0x0 0x0 0x0>; 560 #size-cells = <2>; 561 #address-cells = <3>; 562 device_type = "pci"; 563 ranges = <0x2000000 0x0 0xa0000000 564 0x2000000 0x0 0xa0000000 565 0x0 0x20000000 566 567 0x1000000 0x0 0x0 568 0x1000000 0x0 0x0 569 0x0 0x100000>; 570 }; 571 }; 572 573 pci1: pcie@ffe0a000 { 574 compatible = "fsl,mpc8548-pcie"; 575 device_type = "pci"; 576 #interrupt-cells = <1>; 577 #size-cells = <2>; 578 #address-cells = <3>; 579 reg = <0 0xffe0a000 0 0x1000>; 580 bus-range = <0 255>; 581 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 582 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 583 clock-frequency = <33333333>; 584 interrupt-parent = <&mpic>; 585 interrupts = <16 2>; 586 interrupt-map-mask = <0xf800 0 0 7>; 587 interrupt-map = < 588 /* IDSEL 0x0 */ 589 0000 0 0 1 &mpic 0 1 590 0000 0 0 2 &mpic 1 1 591 0000 0 0 3 &mpic 2 1 592 0000 0 0 4 &mpic 3 1 593 >; 594 pcie@0 { 595 reg = <0x0 0x0 0x0 0x0 0x0>; 596 #size-cells = <2>; 597 #address-cells = <3>; 598 device_type = "pci"; 599 ranges = <0x2000000 0x0 0xc0000000 600 0x2000000 0x0 0xc0000000 601 0x0 0x20000000 602 603 0x1000000 0x0 0x0 604 0x1000000 0x0 0x0 605 0x0 0x100000>; 606 }; 607 }; 608 609 qe@ffe80000 { 610 #address-cells = <1>; 611 #size-cells = <1>; 612 device_type = "qe"; 613 compatible = "fsl,qe"; 614 ranges = <0x0 0x0 0xffe80000 0x40000>; 615 reg = <0 0xffe80000 0 0x480>; 616 brg-frequency = <0>; 617 bus-frequency = <0>; 618 fsl,qe-num-riscs = <1>; 619 fsl,qe-num-snums = <28>; 620 status = "disabled"; /* no firmware loaded */ 621 622 qeic: interrupt-controller@80 { 623 interrupt-controller; 624 compatible = "fsl,qe-ic"; 625 #address-cells = <0>; 626 #interrupt-cells = <1>; 627 reg = <0x80 0x80>; 628 interrupts = <63 2 60 2>; //high:47 low:44 629 interrupt-parent = <&mpic>; 630 }; 631 632 enet3: ucc@2000 { 633 device_type = "network"; 634 compatible = "ucc_geth"; 635 cell-index = <1>; 636 reg = <0x2000 0x200>; 637 interrupts = <32>; 638 interrupt-parent = <&qeic>; 639 local-mac-address = [ 00 00 00 00 00 00 ]; 640 rx-clock-name = "clk12"; 641 tx-clock-name = "clk9"; 642 pio-handle = <&pio1>; 643 phy-handle = <&qe_phy0>; 644 phy-connection-type = "mii"; 645 }; 646 647 mdio@2120 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 reg = <0x2120 0x18>; 651 compatible = "fsl,ucc-mdio"; 652 653 qe_phy0: ethernet-phy@0 { 654 interrupt-parent = <&mpic>; 655 interrupts = <4 1>; 656 reg = <0x0>; 657 device_type = "ethernet-phy"; 658 }; 659 qe_phy1: ethernet-phy@03 { 660 interrupt-parent = <&mpic>; 661 interrupts = <5 1>; 662 reg = <0x3>; 663 device_type = "ethernet-phy"; 664 }; 665 tbi-phy@11 { 666 reg = <0x11>; 667 device_type = "tbi-phy"; 668 }; 669 }; 670 671 enet4: ucc@2400 { 672 device_type = "network"; 673 compatible = "ucc_geth"; 674 cell-index = <5>; 675 reg = <0x2400 0x200>; 676 interrupts = <40>; 677 interrupt-parent = <&qeic>; 678 local-mac-address = [ 00 00 00 00 00 00 ]; 679 rx-clock-name = "none"; 680 tx-clock-name = "clk13"; 681 pio-handle = <&pio2>; 682 phy-handle = <&qe_phy1>; 683 phy-connection-type = "rmii"; 684 }; 685 686 muram@10000 { 687 #address-cells = <1>; 688 #size-cells = <1>; 689 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 690 ranges = <0x0 0x10000 0x6000>; 691 692 data-only@0 { 693 compatible = "fsl,qe-muram-data", 694 "fsl,cpm-muram-data"; 695 reg = <0x0 0x6000>; 696 }; 697 }; 698 }; 699}; 700