1/* 2 * MPC8641 HPCN Device Tree Source 3 * 4 * Copyright 2008-2009 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8641HPCN"; 16 compatible = "fsl,mpc8641hpcn"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 ethernet2 = &enet2; 24 ethernet3 = &enet3; 25 serial0 = &serial0; 26 serial1 = &serial1; 27 pci0 = &pci0; 28 pci1 = &pci1; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 PowerPC,8641@0 { 36 device_type = "cpu"; 37 reg = <0>; 38 d-cache-line-size = <32>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes 40 d-cache-size = <32768>; // L1, 32K 41 i-cache-size = <32768>; // L1, 32K 42 timebase-frequency = <0>; // 33 MHz, from uboot 43 bus-frequency = <0>; // From uboot 44 clock-frequency = <0>; // From uboot 45 }; 46 PowerPC,8641@1 { 47 device_type = "cpu"; 48 reg = <1>; 49 d-cache-line-size = <32>; // 32 bytes 50 i-cache-line-size = <32>; // 32 bytes 51 d-cache-size = <32768>; // L1, 32K 52 i-cache-size = <32768>; // L1, 32K 53 timebase-frequency = <0>; // 33 MHz, from uboot 54 bus-frequency = <0>; // From uboot 55 clock-frequency = <0>; // From uboot 56 }; 57 }; 58 59 memory { 60 device_type = "memory"; 61 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0 62 }; 63 64 localbus@fffe05000 { 65 #address-cells = <2>; 66 #size-cells = <1>; 67 compatible = "fsl,mpc8641-localbus", "simple-bus"; 68 reg = <0x0f 0xffe05000 0x0 0x1000>; 69 interrupts = <19 2>; 70 interrupt-parent = <&mpic>; 71 72 ranges = <0 0 0xf 0xef800000 0x00800000 73 2 0 0xf 0xffdf8000 0x00008000 74 3 0 0xf 0xffdf0000 0x00008000>; 75 76 flash@0,0 { 77 compatible = "cfi-flash"; 78 reg = <0 0 0x00800000>; 79 bank-width = <2>; 80 device-width = <2>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 partition@0 { 84 label = "kernel"; 85 reg = <0x00000000 0x00300000>; 86 }; 87 partition@300000 { 88 label = "firmware b"; 89 reg = <0x00300000 0x00100000>; 90 read-only; 91 }; 92 partition@400000 { 93 label = "fs"; 94 reg = <0x00400000 0x00300000>; 95 }; 96 partition@700000 { 97 label = "firmware a"; 98 reg = <0x00700000 0x00100000>; 99 read-only; 100 }; 101 }; 102 }; 103 104 soc8641@fffe00000 { 105 #address-cells = <1>; 106 #size-cells = <1>; 107 device_type = "soc"; 108 compatible = "simple-bus"; 109 ranges = <0x00000000 0x0f 0xffe00000 0x00100000>; 110 bus-frequency = <0>; 111 112 mcm-law@0 { 113 compatible = "fsl,mcm-law"; 114 reg = <0x0 0x1000>; 115 fsl,num-laws = <10>; 116 }; 117 118 mcm@1000 { 119 compatible = "fsl,mpc8641-mcm", "fsl,mcm"; 120 reg = <0x1000 0x1000>; 121 interrupts = <17 2>; 122 interrupt-parent = <&mpic>; 123 }; 124 125 i2c@3000 { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 cell-index = <0>; 129 compatible = "fsl-i2c"; 130 reg = <0x3000 0x100>; 131 interrupts = <43 2>; 132 interrupt-parent = <&mpic>; 133 dfsrr; 134 }; 135 136 i2c@3100 { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 cell-index = <1>; 140 compatible = "fsl-i2c"; 141 reg = <0x3100 0x100>; 142 interrupts = <43 2>; 143 interrupt-parent = <&mpic>; 144 dfsrr; 145 }; 146 147 dma@21300 { 148 #address-cells = <1>; 149 #size-cells = <1>; 150 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; 151 reg = <0x21300 0x4>; 152 ranges = <0x0 0x21100 0x200>; 153 cell-index = <0>; 154 dma-channel@0 { 155 compatible = "fsl,mpc8641-dma-channel", 156 "fsl,eloplus-dma-channel"; 157 reg = <0x0 0x80>; 158 cell-index = <0>; 159 interrupt-parent = <&mpic>; 160 interrupts = <20 2>; 161 }; 162 dma-channel@80 { 163 compatible = "fsl,mpc8641-dma-channel", 164 "fsl,eloplus-dma-channel"; 165 reg = <0x80 0x80>; 166 cell-index = <1>; 167 interrupt-parent = <&mpic>; 168 interrupts = <21 2>; 169 }; 170 dma-channel@100 { 171 compatible = "fsl,mpc8641-dma-channel", 172 "fsl,eloplus-dma-channel"; 173 reg = <0x100 0x80>; 174 cell-index = <2>; 175 interrupt-parent = <&mpic>; 176 interrupts = <22 2>; 177 }; 178 dma-channel@180 { 179 compatible = "fsl,mpc8641-dma-channel", 180 "fsl,eloplus-dma-channel"; 181 reg = <0x180 0x80>; 182 cell-index = <3>; 183 interrupt-parent = <&mpic>; 184 interrupts = <23 2>; 185 }; 186 }; 187 188 enet0: ethernet@24000 { 189 #address-cells = <1>; 190 #size-cells = <1>; 191 cell-index = <0>; 192 device_type = "network"; 193 model = "TSEC"; 194 compatible = "gianfar"; 195 reg = <0x24000 0x1000>; 196 ranges = <0x0 0x24000 0x1000>; 197 local-mac-address = [ 00 00 00 00 00 00 ]; 198 interrupts = <29 2 30 2 34 2>; 199 interrupt-parent = <&mpic>; 200 tbi-handle = <&tbi0>; 201 phy-handle = <&phy0>; 202 phy-connection-type = "rgmii-id"; 203 204 mdio@520 { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 compatible = "fsl,gianfar-mdio"; 208 reg = <0x520 0x20>; 209 210 phy0: ethernet-phy@0 { 211 interrupt-parent = <&mpic>; 212 interrupts = <10 1>; 213 reg = <0>; 214 device_type = "ethernet-phy"; 215 }; 216 phy1: ethernet-phy@1 { 217 interrupt-parent = <&mpic>; 218 interrupts = <10 1>; 219 reg = <1>; 220 device_type = "ethernet-phy"; 221 }; 222 phy2: ethernet-phy@2 { 223 interrupt-parent = <&mpic>; 224 interrupts = <10 1>; 225 reg = <2>; 226 device_type = "ethernet-phy"; 227 }; 228 phy3: ethernet-phy@3 { 229 interrupt-parent = <&mpic>; 230 interrupts = <10 1>; 231 reg = <3>; 232 device_type = "ethernet-phy"; 233 }; 234 tbi0: tbi-phy@11 { 235 reg = <0x11>; 236 device_type = "tbi-phy"; 237 }; 238 }; 239 }; 240 241 enet1: ethernet@25000 { 242 #address-cells = <1>; 243 #size-cells = <1>; 244 cell-index = <1>; 245 device_type = "network"; 246 model = "TSEC"; 247 compatible = "gianfar"; 248 reg = <0x25000 0x1000>; 249 ranges = <0x0 0x25000 0x1000>; 250 local-mac-address = [ 00 00 00 00 00 00 ]; 251 interrupts = <35 2 36 2 40 2>; 252 interrupt-parent = <&mpic>; 253 tbi-handle = <&tbi1>; 254 phy-handle = <&phy1>; 255 phy-connection-type = "rgmii-id"; 256 257 mdio@520 { 258 #address-cells = <1>; 259 #size-cells = <0>; 260 compatible = "fsl,gianfar-tbi"; 261 reg = <0x520 0x20>; 262 263 tbi1: tbi-phy@11 { 264 reg = <0x11>; 265 device_type = "tbi-phy"; 266 }; 267 }; 268 }; 269 270 enet2: ethernet@26000 { 271 #address-cells = <1>; 272 #size-cells = <1>; 273 cell-index = <2>; 274 device_type = "network"; 275 model = "TSEC"; 276 compatible = "gianfar"; 277 reg = <0x26000 0x1000>; 278 ranges = <0x0 0x26000 0x1000>; 279 local-mac-address = [ 00 00 00 00 00 00 ]; 280 interrupts = <31 2 32 2 33 2>; 281 interrupt-parent = <&mpic>; 282 tbi-handle = <&tbi2>; 283 phy-handle = <&phy2>; 284 phy-connection-type = "rgmii-id"; 285 286 mdio@520 { 287 #address-cells = <1>; 288 #size-cells = <0>; 289 compatible = "fsl,gianfar-tbi"; 290 reg = <0x520 0x20>; 291 292 tbi2: tbi-phy@11 { 293 reg = <0x11>; 294 device_type = "tbi-phy"; 295 }; 296 }; 297 }; 298 299 enet3: ethernet@27000 { 300 #address-cells = <1>; 301 #size-cells = <1>; 302 cell-index = <3>; 303 device_type = "network"; 304 model = "TSEC"; 305 compatible = "gianfar"; 306 reg = <0x27000 0x1000>; 307 ranges = <0x0 0x27000 0x1000>; 308 local-mac-address = [ 00 00 00 00 00 00 ]; 309 interrupts = <37 2 38 2 39 2>; 310 interrupt-parent = <&mpic>; 311 tbi-handle = <&tbi3>; 312 phy-handle = <&phy3>; 313 phy-connection-type = "rgmii-id"; 314 315 mdio@520 { 316 #address-cells = <1>; 317 #size-cells = <0>; 318 compatible = "fsl,gianfar-tbi"; 319 reg = <0x520 0x20>; 320 321 tbi3: tbi-phy@11 { 322 reg = <0x11>; 323 device_type = "tbi-phy"; 324 }; 325 }; 326 }; 327 328 serial0: serial@4500 { 329 cell-index = <0>; 330 device_type = "serial"; 331 compatible = "ns16550"; 332 reg = <0x4500 0x100>; 333 clock-frequency = <0>; 334 interrupts = <42 2>; 335 interrupt-parent = <&mpic>; 336 }; 337 338 serial1: serial@4600 { 339 cell-index = <1>; 340 device_type = "serial"; 341 compatible = "ns16550"; 342 reg = <0x4600 0x100>; 343 clock-frequency = <0>; 344 interrupts = <28 2>; 345 interrupt-parent = <&mpic>; 346 }; 347 348 mpic: pic@40000 { 349 interrupt-controller; 350 #address-cells = <0>; 351 #interrupt-cells = <2>; 352 reg = <0x40000 0x40000>; 353 compatible = "chrp,open-pic"; 354 device_type = "open-pic"; 355 }; 356 357 global-utilities@e0000 { 358 compatible = "fsl,mpc8641-guts"; 359 reg = <0xe0000 0x1000>; 360 fsl,has-rstcr; 361 }; 362 }; 363 364 pci0: pcie@fffe08000 { 365 cell-index = <0>; 366 compatible = "fsl,mpc8641-pcie"; 367 device_type = "pci"; 368 #interrupt-cells = <1>; 369 #size-cells = <2>; 370 #address-cells = <3>; 371 reg = <0x0f 0xffe08000 0x0 0x1000>; 372 bus-range = <0x0 0xff>; 373 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000 374 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>; 375 clock-frequency = <33333333>; 376 interrupt-parent = <&mpic>; 377 interrupts = <24 2>; 378 interrupt-map-mask = <0xff00 0 0 7>; 379 interrupt-map = < 380 /* IDSEL 0x11 func 0 - PCI slot 1 */ 381 0x8800 0 0 1 &mpic 2 1 382 0x8800 0 0 2 &mpic 3 1 383 0x8800 0 0 3 &mpic 4 1 384 0x8800 0 0 4 &mpic 1 1 385 386 /* IDSEL 0x11 func 1 - PCI slot 1 */ 387 0x8900 0 0 1 &mpic 2 1 388 0x8900 0 0 2 &mpic 3 1 389 0x8900 0 0 3 &mpic 4 1 390 0x8900 0 0 4 &mpic 1 1 391 392 /* IDSEL 0x11 func 2 - PCI slot 1 */ 393 0x8a00 0 0 1 &mpic 2 1 394 0x8a00 0 0 2 &mpic 3 1 395 0x8a00 0 0 3 &mpic 4 1 396 0x8a00 0 0 4 &mpic 1 1 397 398 /* IDSEL 0x11 func 3 - PCI slot 1 */ 399 0x8b00 0 0 1 &mpic 2 1 400 0x8b00 0 0 2 &mpic 3 1 401 0x8b00 0 0 3 &mpic 4 1 402 0x8b00 0 0 4 &mpic 1 1 403 404 /* IDSEL 0x11 func 4 - PCI slot 1 */ 405 0x8c00 0 0 1 &mpic 2 1 406 0x8c00 0 0 2 &mpic 3 1 407 0x8c00 0 0 3 &mpic 4 1 408 0x8c00 0 0 4 &mpic 1 1 409 410 /* IDSEL 0x11 func 5 - PCI slot 1 */ 411 0x8d00 0 0 1 &mpic 2 1 412 0x8d00 0 0 2 &mpic 3 1 413 0x8d00 0 0 3 &mpic 4 1 414 0x8d00 0 0 4 &mpic 1 1 415 416 /* IDSEL 0x11 func 6 - PCI slot 1 */ 417 0x8e00 0 0 1 &mpic 2 1 418 0x8e00 0 0 2 &mpic 3 1 419 0x8e00 0 0 3 &mpic 4 1 420 0x8e00 0 0 4 &mpic 1 1 421 422 /* IDSEL 0x11 func 7 - PCI slot 1 */ 423 0x8f00 0 0 1 &mpic 2 1 424 0x8f00 0 0 2 &mpic 3 1 425 0x8f00 0 0 3 &mpic 4 1 426 0x8f00 0 0 4 &mpic 1 1 427 428 /* IDSEL 0x12 func 0 - PCI slot 2 */ 429 0x9000 0 0 1 &mpic 3 1 430 0x9000 0 0 2 &mpic 4 1 431 0x9000 0 0 3 &mpic 1 1 432 0x9000 0 0 4 &mpic 2 1 433 434 /* IDSEL 0x12 func 1 - PCI slot 2 */ 435 0x9100 0 0 1 &mpic 3 1 436 0x9100 0 0 2 &mpic 4 1 437 0x9100 0 0 3 &mpic 1 1 438 0x9100 0 0 4 &mpic 2 1 439 440 /* IDSEL 0x12 func 2 - PCI slot 2 */ 441 0x9200 0 0 1 &mpic 3 1 442 0x9200 0 0 2 &mpic 4 1 443 0x9200 0 0 3 &mpic 1 1 444 0x9200 0 0 4 &mpic 2 1 445 446 /* IDSEL 0x12 func 3 - PCI slot 2 */ 447 0x9300 0 0 1 &mpic 3 1 448 0x9300 0 0 2 &mpic 4 1 449 0x9300 0 0 3 &mpic 1 1 450 0x9300 0 0 4 &mpic 2 1 451 452 /* IDSEL 0x12 func 4 - PCI slot 2 */ 453 0x9400 0 0 1 &mpic 3 1 454 0x9400 0 0 2 &mpic 4 1 455 0x9400 0 0 3 &mpic 1 1 456 0x9400 0 0 4 &mpic 2 1 457 458 /* IDSEL 0x12 func 5 - PCI slot 2 */ 459 0x9500 0 0 1 &mpic 3 1 460 0x9500 0 0 2 &mpic 4 1 461 0x9500 0 0 3 &mpic 1 1 462 0x9500 0 0 4 &mpic 2 1 463 464 /* IDSEL 0x12 func 6 - PCI slot 2 */ 465 0x9600 0 0 1 &mpic 3 1 466 0x9600 0 0 2 &mpic 4 1 467 0x9600 0 0 3 &mpic 1 1 468 0x9600 0 0 4 &mpic 2 1 469 470 /* IDSEL 0x12 func 7 - PCI slot 2 */ 471 0x9700 0 0 1 &mpic 3 1 472 0x9700 0 0 2 &mpic 4 1 473 0x9700 0 0 3 &mpic 1 1 474 0x9700 0 0 4 &mpic 2 1 475 476 // IDSEL 0x1c USB 477 0xe000 0 0 1 &i8259 12 2 478 0xe100 0 0 2 &i8259 9 2 479 0xe200 0 0 3 &i8259 10 2 480 0xe300 0 0 4 &i8259 11 2 481 482 // IDSEL 0x1d Audio 483 0xe800 0 0 1 &i8259 6 2 484 485 // IDSEL 0x1e Legacy 486 0xf000 0 0 1 &i8259 7 2 487 0xf100 0 0 1 &i8259 7 2 488 489 // IDSEL 0x1f IDE/SATA 490 0xf800 0 0 1 &i8259 14 2 491 0xf900 0 0 1 &i8259 5 2 492 >; 493 494 pcie@0 { 495 reg = <0 0 0 0 0>; 496 #size-cells = <2>; 497 #address-cells = <3>; 498 device_type = "pci"; 499 ranges = <0x02000000 0x0 0xe0000000 500 0x02000000 0x0 0xe0000000 501 0x0 0x20000000 502 503 0x01000000 0x0 0x00000000 504 0x01000000 0x0 0x00000000 505 0x0 0x00010000>; 506 uli1575@0 { 507 reg = <0 0 0 0 0>; 508 #size-cells = <2>; 509 #address-cells = <3>; 510 ranges = <0x02000000 0x0 0xe0000000 511 0x02000000 0x0 0xe0000000 512 0x0 0x20000000 513 0x01000000 0x0 0x00000000 514 0x01000000 0x0 0x00000000 515 0x0 0x00010000>; 516 isa@1e { 517 device_type = "isa"; 518 #interrupt-cells = <2>; 519 #size-cells = <1>; 520 #address-cells = <2>; 521 reg = <0xf000 0 0 0 0>; 522 ranges = <1 0 0x01000000 0 0 523 0x00001000>; 524 interrupt-parent = <&i8259>; 525 526 i8259: interrupt-controller@20 { 527 reg = <1 0x20 2 528 1 0xa0 2 529 1 0x4d0 2>; 530 interrupt-controller; 531 device_type = "interrupt-controller"; 532 #address-cells = <0>; 533 #interrupt-cells = <2>; 534 compatible = "chrp,iic"; 535 interrupts = <9 2>; 536 interrupt-parent = <&mpic>; 537 }; 538 539 i8042@60 { 540 #size-cells = <0>; 541 #address-cells = <1>; 542 reg = <1 0x60 1 1 0x64 1>; 543 interrupts = <1 3 12 3>; 544 interrupt-parent = 545 <&i8259>; 546 547 keyboard@0 { 548 reg = <0>; 549 compatible = "pnpPNP,303"; 550 }; 551 552 mouse@1 { 553 reg = <1>; 554 compatible = "pnpPNP,f03"; 555 }; 556 }; 557 558 rtc@70 { 559 compatible = 560 "pnpPNP,b00"; 561 reg = <1 0x70 2>; 562 }; 563 564 gpio@400 { 565 reg = <1 0x400 0x80>; 566 }; 567 }; 568 }; 569 }; 570 571 }; 572 573 pci1: pcie@fffe09000 { 574 cell-index = <1>; 575 compatible = "fsl,mpc8641-pcie"; 576 device_type = "pci"; 577 #interrupt-cells = <1>; 578 #size-cells = <2>; 579 #address-cells = <3>; 580 reg = <0x0f 0xffe09000 0x0 0x1000>; 581 bus-range = <0x0 0xff>; 582 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000 583 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>; 584 clock-frequency = <33333333>; 585 interrupt-parent = <&mpic>; 586 interrupts = <25 2>; 587 interrupt-map-mask = <0xf800 0 0 7>; 588 interrupt-map = < 589 /* IDSEL 0x0 */ 590 0x0000 0 0 1 &mpic 4 1 591 0x0000 0 0 2 &mpic 5 1 592 0x0000 0 0 3 &mpic 6 1 593 0x0000 0 0 4 &mpic 7 1 594 >; 595 pcie@0 { 596 reg = <0 0 0 0 0>; 597 #size-cells = <2>; 598 #address-cells = <3>; 599 device_type = "pci"; 600 ranges = <0x02000000 0x0 0xe0000000 601 0x02000000 0x0 0xe0000000 602 0x0 0x20000000 603 604 0x01000000 0x0 0x00000000 605 0x01000000 0x0 0x00000000 606 0x0 0x00010000>; 607 }; 608 }; 609}; 610