1/* 2 * MPC8379E MDS Device Tree Source 3 * 4 * Copyright 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "fsl,mpc8379emds"; 16 compatible = "fsl,mpc8379emds","fsl,mpc837xmds"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,8379@0 { 33 device_type = "cpu"; 34 reg = <0x0>; 35 d-cache-line-size = <32>; 36 i-cache-line-size = <32>; 37 d-cache-size = <32768>; 38 i-cache-size = <32768>; 39 timebase-frequency = <0>; 40 bus-frequency = <0>; 41 clock-frequency = <0>; 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x20000000>; // 512MB at 0 48 }; 49 50 localbus@e0005000 { 51 #address-cells = <2>; 52 #size-cells = <1>; 53 compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus"; 54 reg = <0xe0005000 0x1000>; 55 interrupts = <77 0x8>; 56 interrupt-parent = <&ipic>; 57 58 // booting from NOR flash 59 ranges = <0 0x0 0xfe000000 0x02000000 60 1 0x0 0xf8000000 0x00008000 61 3 0x0 0xe0600000 0x00008000>; 62 63 flash@0,0 { 64 #address-cells = <1>; 65 #size-cells = <1>; 66 compatible = "cfi-flash"; 67 reg = <0 0x0 0x2000000>; 68 bank-width = <2>; 69 device-width = <1>; 70 71 u-boot@0 { 72 reg = <0x0 0x100000>; 73 read-only; 74 }; 75 76 fs@100000 { 77 reg = <0x100000 0x800000>; 78 }; 79 80 kernel@1d00000 { 81 reg = <0x1d00000 0x200000>; 82 }; 83 84 dtb@1f00000 { 85 reg = <0x1f00000 0x100000>; 86 }; 87 }; 88 89 bcsr@1,0 { 90 reg = <1 0x0 0x8000>; 91 compatible = "fsl,mpc837xmds-bcsr"; 92 }; 93 94 nand@3,0 { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 compatible = "fsl,mpc8379-fcm-nand", 98 "fsl,elbc-fcm-nand"; 99 reg = <3 0x0 0x8000>; 100 101 u-boot@0 { 102 reg = <0x0 0x100000>; 103 read-only; 104 }; 105 106 kernel@100000 { 107 reg = <0x100000 0x300000>; 108 }; 109 110 fs@400000 { 111 reg = <0x400000 0x1c00000>; 112 }; 113 }; 114 }; 115 116 soc@e0000000 { 117 #address-cells = <1>; 118 #size-cells = <1>; 119 device_type = "soc"; 120 compatible = "simple-bus"; 121 ranges = <0x0 0xe0000000 0x00100000>; 122 reg = <0xe0000000 0x00000200>; 123 bus-frequency = <0>; 124 125 wdt@200 { 126 compatible = "mpc83xx_wdt"; 127 reg = <0x200 0x100>; 128 }; 129 130 sleep-nexus { 131 #address-cells = <1>; 132 #size-cells = <1>; 133 compatible = "simple-bus"; 134 sleep = <&pmc 0x0c000000>; 135 ranges; 136 137 i2c@3000 { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 cell-index = <0>; 141 compatible = "fsl-i2c"; 142 reg = <0x3000 0x100>; 143 interrupts = <14 0x8>; 144 interrupt-parent = <&ipic>; 145 dfsrr; 146 147 rtc@68 { 148 compatible = "dallas,ds1374"; 149 reg = <0x68>; 150 interrupts = <19 0x8>; 151 interrupt-parent = <&ipic>; 152 }; 153 }; 154 155 sdhci@2e000 { 156 compatible = "fsl,mpc8379-esdhc", "fsl,esdhc"; 157 reg = <0x2e000 0x1000>; 158 interrupts = <42 0x8>; 159 interrupt-parent = <&ipic>; 160 sdhci,wp-inverted; 161 /* Filled in by U-Boot */ 162 clock-frequency = <0>; 163 }; 164 }; 165 166 i2c@3100 { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 cell-index = <1>; 170 compatible = "fsl-i2c"; 171 reg = <0x3100 0x100>; 172 interrupts = <15 0x8>; 173 interrupt-parent = <&ipic>; 174 dfsrr; 175 }; 176 177 spi@7000 { 178 cell-index = <0>; 179 compatible = "fsl,spi"; 180 reg = <0x7000 0x1000>; 181 interrupts = <16 0x8>; 182 interrupt-parent = <&ipic>; 183 mode = "cpu"; 184 }; 185 186 dma@82a8 { 187 #address-cells = <1>; 188 #size-cells = <1>; 189 compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; 190 reg = <0x82a8 4>; 191 ranges = <0 0x8100 0x1a8>; 192 interrupt-parent = <&ipic>; 193 interrupts = <71 8>; 194 cell-index = <0>; 195 dma-channel@0 { 196 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 197 reg = <0 0x80>; 198 cell-index = <0>; 199 interrupt-parent = <&ipic>; 200 interrupts = <71 8>; 201 }; 202 dma-channel@80 { 203 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 204 reg = <0x80 0x80>; 205 cell-index = <1>; 206 interrupt-parent = <&ipic>; 207 interrupts = <71 8>; 208 }; 209 dma-channel@100 { 210 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 211 reg = <0x100 0x80>; 212 cell-index = <2>; 213 interrupt-parent = <&ipic>; 214 interrupts = <71 8>; 215 }; 216 dma-channel@180 { 217 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 218 reg = <0x180 0x28>; 219 cell-index = <3>; 220 interrupt-parent = <&ipic>; 221 interrupts = <71 8>; 222 }; 223 }; 224 225 usb@23000 { 226 compatible = "fsl-usb2-dr"; 227 reg = <0x23000 0x1000>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 interrupt-parent = <&ipic>; 231 interrupts = <38 0x8>; 232 dr_mode = "host"; 233 phy_type = "ulpi"; 234 sleep = <&pmc 0x00c00000>; 235 }; 236 237 enet0: ethernet@24000 { 238 #address-cells = <1>; 239 #size-cells = <1>; 240 cell-index = <0>; 241 device_type = "network"; 242 model = "eTSEC"; 243 compatible = "gianfar"; 244 reg = <0x24000 0x1000>; 245 ranges = <0x0 0x24000 0x1000>; 246 local-mac-address = [ 00 00 00 00 00 00 ]; 247 interrupts = <32 0x8 33 0x8 34 0x8>; 248 phy-connection-type = "mii"; 249 interrupt-parent = <&ipic>; 250 tbi-handle = <&tbi0>; 251 phy-handle = <&phy2>; 252 sleep = <&pmc 0xc0000000>; 253 fsl,magic-packet; 254 255 mdio@520 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "fsl,gianfar-mdio"; 259 reg = <0x520 0x20>; 260 261 phy2: ethernet-phy@2 { 262 interrupt-parent = <&ipic>; 263 interrupts = <17 0x8>; 264 reg = <0x2>; 265 device_type = "ethernet-phy"; 266 }; 267 268 phy3: ethernet-phy@3 { 269 interrupt-parent = <&ipic>; 270 interrupts = <18 0x8>; 271 reg = <0x3>; 272 device_type = "ethernet-phy"; 273 }; 274 275 tbi0: tbi-phy@11 { 276 reg = <0x11>; 277 device_type = "tbi-phy"; 278 }; 279 }; 280 }; 281 282 enet1: ethernet@25000 { 283 #address-cells = <1>; 284 #size-cells = <1>; 285 cell-index = <1>; 286 device_type = "network"; 287 model = "eTSEC"; 288 compatible = "gianfar"; 289 reg = <0x25000 0x1000>; 290 ranges = <0x0 0x25000 0x1000>; 291 local-mac-address = [ 00 00 00 00 00 00 ]; 292 interrupts = <35 0x8 36 0x8 37 0x8>; 293 phy-connection-type = "mii"; 294 interrupt-parent = <&ipic>; 295 tbi-handle = <&tbi1>; 296 phy-handle = <&phy3>; 297 sleep = <&pmc 0x30000000>; 298 fsl,magic-packet; 299 300 mdio@520 { 301 #address-cells = <1>; 302 #size-cells = <0>; 303 compatible = "fsl,gianfar-tbi"; 304 reg = <0x520 0x20>; 305 306 tbi1: tbi-phy@11 { 307 reg = <0x11>; 308 device_type = "tbi-phy"; 309 }; 310 }; 311 }; 312 313 serial0: serial@4500 { 314 cell-index = <0>; 315 device_type = "serial"; 316 compatible = "ns16550"; 317 reg = <0x4500 0x100>; 318 clock-frequency = <0>; 319 interrupts = <9 0x8>; 320 interrupt-parent = <&ipic>; 321 }; 322 323 serial1: serial@4600 { 324 cell-index = <1>; 325 device_type = "serial"; 326 compatible = "ns16550"; 327 reg = <0x4600 0x100>; 328 clock-frequency = <0>; 329 interrupts = <10 0x8>; 330 interrupt-parent = <&ipic>; 331 }; 332 333 crypto@30000 { 334 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 335 "fsl,sec2.1", "fsl,sec2.0"; 336 reg = <0x30000 0x10000>; 337 interrupts = <11 0x8>; 338 interrupt-parent = <&ipic>; 339 fsl,num-channels = <4>; 340 fsl,channel-fifo-len = <24>; 341 fsl,exec-units-mask = <0x9fe>; 342 fsl,descriptor-types-mask = <0x3ab0ebf>; 343 sleep = <&pmc 0x03000000>; 344 }; 345 346 sata@18000 { 347 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 348 reg = <0x18000 0x1000>; 349 interrupts = <44 0x8>; 350 interrupt-parent = <&ipic>; 351 sleep = <&pmc 0x000000c0>; 352 }; 353 354 sata@19000 { 355 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 356 reg = <0x19000 0x1000>; 357 interrupts = <45 0x8>; 358 interrupt-parent = <&ipic>; 359 sleep = <&pmc 0x00000030>; 360 }; 361 362 sata@1a000 { 363 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 364 reg = <0x1a000 0x1000>; 365 interrupts = <46 0x8>; 366 interrupt-parent = <&ipic>; 367 sleep = <&pmc 0x0000000c>; 368 }; 369 370 sata@1b000 { 371 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 372 reg = <0x1b000 0x1000>; 373 interrupts = <47 0x8>; 374 interrupt-parent = <&ipic>; 375 sleep = <&pmc 0x00000003>; 376 }; 377 378 /* IPIC 379 * interrupts cell = <intr #, sense> 380 * sense values match linux IORESOURCE_IRQ_* defines: 381 * sense == 8: Level, low assertion 382 * sense == 2: Edge, high-to-low change 383 */ 384 ipic: pic@700 { 385 compatible = "fsl,ipic"; 386 interrupt-controller; 387 #address-cells = <0>; 388 #interrupt-cells = <2>; 389 reg = <0x700 0x100>; 390 }; 391 392 pmc: power@b00 { 393 compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc"; 394 reg = <0xb00 0x100 0xa00 0x100>; 395 interrupts = <80 0x8>; 396 interrupt-parent = <&ipic>; 397 }; 398 }; 399 400 pci0: pci@e0008500 { 401 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 402 interrupt-map = < 403 404 /* IDSEL 0x11 */ 405 0x8800 0x0 0x0 0x1 &ipic 20 0x8 406 0x8800 0x0 0x0 0x2 &ipic 21 0x8 407 0x8800 0x0 0x0 0x3 &ipic 22 0x8 408 0x8800 0x0 0x0 0x4 &ipic 23 0x8 409 410 /* IDSEL 0x12 */ 411 0x9000 0x0 0x0 0x1 &ipic 22 0x8 412 0x9000 0x0 0x0 0x2 &ipic 23 0x8 413 0x9000 0x0 0x0 0x3 &ipic 20 0x8 414 0x9000 0x0 0x0 0x4 &ipic 21 0x8 415 416 /* IDSEL 0x13 */ 417 0x9800 0x0 0x0 0x1 &ipic 23 0x8 418 0x9800 0x0 0x0 0x2 &ipic 20 0x8 419 0x9800 0x0 0x0 0x3 &ipic 21 0x8 420 0x9800 0x0 0x0 0x4 &ipic 22 0x8 421 422 /* IDSEL 0x15 */ 423 0xa800 0x0 0x0 0x1 &ipic 20 0x8 424 0xa800 0x0 0x0 0x2 &ipic 21 0x8 425 0xa800 0x0 0x0 0x3 &ipic 22 0x8 426 0xa800 0x0 0x0 0x4 &ipic 23 0x8 427 428 /* IDSEL 0x16 */ 429 0xb000 0x0 0x0 0x1 &ipic 23 0x8 430 0xb000 0x0 0x0 0x2 &ipic 20 0x8 431 0xb000 0x0 0x0 0x3 &ipic 21 0x8 432 0xb000 0x0 0x0 0x4 &ipic 22 0x8 433 434 /* IDSEL 0x17 */ 435 0xb800 0x0 0x0 0x1 &ipic 22 0x8 436 0xb800 0x0 0x0 0x2 &ipic 23 0x8 437 0xb800 0x0 0x0 0x3 &ipic 20 0x8 438 0xb800 0x0 0x0 0x4 &ipic 21 0x8 439 440 /* IDSEL 0x18 */ 441 0xc000 0x0 0x0 0x1 &ipic 21 0x8 442 0xc000 0x0 0x0 0x2 &ipic 22 0x8 443 0xc000 0x0 0x0 0x3 &ipic 23 0x8 444 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; 445 interrupt-parent = <&ipic>; 446 interrupts = <66 0x8>; 447 bus-range = <0x0 0x0>; 448 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 449 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 450 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 451 sleep = <&pmc 0x00010000>; 452 clock-frequency = <0>; 453 #interrupt-cells = <1>; 454 #size-cells = <2>; 455 #address-cells = <3>; 456 reg = <0xe0008500 0x100 /* internal registers */ 457 0xe0008300 0x8>; /* config space access registers */ 458 compatible = "fsl,mpc8349-pci"; 459 device_type = "pci"; 460 }; 461}; 462