1/* 2 * MPC8378E MDS Device Tree Source 3 * 4 * Copyright 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "fsl,mpc8378emds"; 16 compatible = "fsl,mpc8378emds","fsl,mpc837xmds"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 pci1 = &pci1; 27 pci2 = &pci2; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 PowerPC,8378@0 { 35 device_type = "cpu"; 36 reg = <0x0>; 37 d-cache-line-size = <32>; 38 i-cache-line-size = <32>; 39 d-cache-size = <32768>; 40 i-cache-size = <32768>; 41 timebase-frequency = <0>; 42 bus-frequency = <0>; 43 clock-frequency = <0>; 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x00000000 0x20000000>; // 512MB at 0 50 }; 51 52 localbus@e0005000 { 53 #address-cells = <2>; 54 #size-cells = <1>; 55 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus"; 56 reg = <0xe0005000 0x1000>; 57 interrupts = <77 0x8>; 58 interrupt-parent = <&ipic>; 59 60 // booting from NOR flash 61 ranges = <0 0x0 0xfe000000 0x02000000 62 1 0x0 0xf8000000 0x00008000 63 3 0x0 0xe0600000 0x00008000>; 64 65 flash@0,0 { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 compatible = "cfi-flash"; 69 reg = <0 0x0 0x2000000>; 70 bank-width = <2>; 71 device-width = <1>; 72 73 u-boot@0 { 74 reg = <0x0 0x100000>; 75 read-only; 76 }; 77 78 fs@100000 { 79 reg = <0x100000 0x800000>; 80 }; 81 82 kernel@1d00000 { 83 reg = <0x1d00000 0x200000>; 84 }; 85 86 dtb@1f00000 { 87 reg = <0x1f00000 0x100000>; 88 }; 89 }; 90 91 bcsr@1,0 { 92 reg = <1 0x0 0x8000>; 93 compatible = "fsl,mpc837xmds-bcsr"; 94 }; 95 96 nand@3,0 { 97 #address-cells = <1>; 98 #size-cells = <1>; 99 compatible = "fsl,mpc8378-fcm-nand", 100 "fsl,elbc-fcm-nand"; 101 reg = <3 0x0 0x8000>; 102 103 u-boot@0 { 104 reg = <0x0 0x100000>; 105 read-only; 106 }; 107 108 kernel@100000 { 109 reg = <0x100000 0x300000>; 110 }; 111 112 fs@400000 { 113 reg = <0x400000 0x1c00000>; 114 }; 115 }; 116 }; 117 118 soc@e0000000 { 119 #address-cells = <1>; 120 #size-cells = <1>; 121 device_type = "soc"; 122 compatible = "simple-bus"; 123 ranges = <0x0 0xe0000000 0x00100000>; 124 reg = <0xe0000000 0x00000200>; 125 bus-frequency = <0>; 126 127 wdt@200 { 128 compatible = "mpc83xx_wdt"; 129 reg = <0x200 0x100>; 130 }; 131 132 sleep-nexus { 133 #address-cells = <1>; 134 #size-cells = <1>; 135 compatible = "simple-bus"; 136 sleep = <&pmc 0x0c000000>; 137 ranges; 138 139 i2c@3000 { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 cell-index = <0>; 143 compatible = "fsl-i2c"; 144 reg = <0x3000 0x100>; 145 interrupts = <14 0x8>; 146 interrupt-parent = <&ipic>; 147 dfsrr; 148 149 rtc@68 { 150 compatible = "dallas,ds1374"; 151 reg = <0x68>; 152 interrupts = <19 0x8>; 153 interrupt-parent = <&ipic>; 154 }; 155 }; 156 157 sdhci@2e000 { 158 compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; 159 reg = <0x2e000 0x1000>; 160 interrupts = <42 0x8>; 161 interrupt-parent = <&ipic>; 162 sdhci,wp-inverted; 163 /* Filled in by U-Boot */ 164 clock-frequency = <0>; 165 }; 166 }; 167 168 i2c@3100 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 cell-index = <1>; 172 compatible = "fsl-i2c"; 173 reg = <0x3100 0x100>; 174 interrupts = <15 0x8>; 175 interrupt-parent = <&ipic>; 176 dfsrr; 177 }; 178 179 spi@7000 { 180 cell-index = <0>; 181 compatible = "fsl,spi"; 182 reg = <0x7000 0x1000>; 183 interrupts = <16 0x8>; 184 interrupt-parent = <&ipic>; 185 mode = "cpu"; 186 }; 187 188 dma@82a8 { 189 #address-cells = <1>; 190 #size-cells = <1>; 191 compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; 192 reg = <0x82a8 4>; 193 ranges = <0 0x8100 0x1a8>; 194 interrupt-parent = <&ipic>; 195 interrupts = <71 8>; 196 cell-index = <0>; 197 dma-channel@0 { 198 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 199 reg = <0 0x80>; 200 cell-index = <0>; 201 interrupt-parent = <&ipic>; 202 interrupts = <71 8>; 203 }; 204 dma-channel@80 { 205 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 206 reg = <0x80 0x80>; 207 cell-index = <1>; 208 interrupt-parent = <&ipic>; 209 interrupts = <71 8>; 210 }; 211 dma-channel@100 { 212 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 213 reg = <0x100 0x80>; 214 cell-index = <2>; 215 interrupt-parent = <&ipic>; 216 interrupts = <71 8>; 217 }; 218 dma-channel@180 { 219 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 220 reg = <0x180 0x28>; 221 cell-index = <3>; 222 interrupt-parent = <&ipic>; 223 interrupts = <71 8>; 224 }; 225 }; 226 227 usb@23000 { 228 compatible = "fsl-usb2-dr"; 229 reg = <0x23000 0x1000>; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 interrupt-parent = <&ipic>; 233 interrupts = <38 0x8>; 234 dr_mode = "host"; 235 phy_type = "ulpi"; 236 sleep = <&pmc 0x00c00000>; 237 }; 238 239 enet0: ethernet@24000 { 240 #address-cells = <1>; 241 #size-cells = <1>; 242 cell-index = <0>; 243 device_type = "network"; 244 model = "eTSEC"; 245 compatible = "gianfar"; 246 reg = <0x24000 0x1000>; 247 ranges = <0x0 0x24000 0x1000>; 248 local-mac-address = [ 00 00 00 00 00 00 ]; 249 interrupts = <32 0x8 33 0x8 34 0x8>; 250 phy-connection-type = "mii"; 251 interrupt-parent = <&ipic>; 252 tbi-handle = <&tbi0>; 253 phy-handle = <&phy2>; 254 sleep = <&pmc 0xc0000000>; 255 fsl,magic-packet; 256 257 mdio@520 { 258 #address-cells = <1>; 259 #size-cells = <0>; 260 compatible = "fsl,gianfar-mdio"; 261 reg = <0x520 0x20>; 262 263 phy2: ethernet-phy@2 { 264 interrupt-parent = <&ipic>; 265 interrupts = <17 0x8>; 266 reg = <0x2>; 267 device_type = "ethernet-phy"; 268 }; 269 270 phy3: ethernet-phy@3 { 271 interrupt-parent = <&ipic>; 272 interrupts = <18 0x8>; 273 reg = <0x3>; 274 device_type = "ethernet-phy"; 275 }; 276 277 tbi0: tbi-phy@11 { 278 reg = <0x11>; 279 device_type = "tbi-phy"; 280 }; 281 }; 282 }; 283 284 enet1: ethernet@25000 { 285 #address-cells = <1>; 286 #size-cells = <1>; 287 cell-index = <1>; 288 device_type = "network"; 289 model = "eTSEC"; 290 compatible = "gianfar"; 291 reg = <0x25000 0x1000>; 292 ranges = <0x0 0x25000 0x1000>; 293 local-mac-address = [ 00 00 00 00 00 00 ]; 294 interrupts = <35 0x8 36 0x8 37 0x8>; 295 phy-connection-type = "mii"; 296 interrupt-parent = <&ipic>; 297 tbi-handle = <&tbi1>; 298 phy-handle = <&phy3>; 299 sleep = <&pmc 0x30000000>; 300 fsl,magic-packet; 301 302 mdio@520 { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 compatible = "fsl,gianfar-tbi"; 306 reg = <0x520 0x20>; 307 308 tbi1: tbi-phy@11 { 309 reg = <0x11>; 310 device_type = "tbi-phy"; 311 }; 312 }; 313 }; 314 315 serial0: serial@4500 { 316 cell-index = <0>; 317 device_type = "serial"; 318 compatible = "ns16550"; 319 reg = <0x4500 0x100>; 320 clock-frequency = <0>; 321 interrupts = <9 0x8>; 322 interrupt-parent = <&ipic>; 323 }; 324 325 serial1: serial@4600 { 326 cell-index = <1>; 327 device_type = "serial"; 328 compatible = "ns16550"; 329 reg = <0x4600 0x100>; 330 clock-frequency = <0>; 331 interrupts = <10 0x8>; 332 interrupt-parent = <&ipic>; 333 }; 334 335 crypto@30000 { 336 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 337 "fsl,sec2.1", "fsl,sec2.0"; 338 reg = <0x30000 0x10000>; 339 interrupts = <11 0x8>; 340 interrupt-parent = <&ipic>; 341 fsl,num-channels = <4>; 342 fsl,channel-fifo-len = <24>; 343 fsl,exec-units-mask = <0x9fe>; 344 fsl,descriptor-types-mask = <0x3ab0ebf>; 345 sleep = <&pmc 0x03000000>; 346 }; 347 348 /* IPIC 349 * interrupts cell = <intr #, sense> 350 * sense values match linux IORESOURCE_IRQ_* defines: 351 * sense == 8: Level, low assertion 352 * sense == 2: Edge, high-to-low change 353 */ 354 ipic: pic@700 { 355 compatible = "fsl,ipic"; 356 interrupt-controller; 357 #address-cells = <0>; 358 #interrupt-cells = <2>; 359 reg = <0x700 0x100>; 360 }; 361 362 pmc: power@b00 { 363 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc"; 364 reg = <0xb00 0x100 0xa00 0x100>; 365 interrupts = <80 0x8>; 366 interrupt-parent = <&ipic>; 367 }; 368 }; 369 370 pci0: pci@e0008500 { 371 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 372 interrupt-map = < 373 374 /* IDSEL 0x11 */ 375 0x8800 0x0 0x0 0x1 &ipic 20 0x8 376 0x8800 0x0 0x0 0x2 &ipic 21 0x8 377 0x8800 0x0 0x0 0x3 &ipic 22 0x8 378 0x8800 0x0 0x0 0x4 &ipic 23 0x8 379 380 /* IDSEL 0x12 */ 381 0x9000 0x0 0x0 0x1 &ipic 22 0x8 382 0x9000 0x0 0x0 0x2 &ipic 23 0x8 383 0x9000 0x0 0x0 0x3 &ipic 20 0x8 384 0x9000 0x0 0x0 0x4 &ipic 21 0x8 385 386 /* IDSEL 0x13 */ 387 0x9800 0x0 0x0 0x1 &ipic 23 0x8 388 0x9800 0x0 0x0 0x2 &ipic 20 0x8 389 0x9800 0x0 0x0 0x3 &ipic 21 0x8 390 0x9800 0x0 0x0 0x4 &ipic 22 0x8 391 392 /* IDSEL 0x15 */ 393 0xa800 0x0 0x0 0x1 &ipic 20 0x8 394 0xa800 0x0 0x0 0x2 &ipic 21 0x8 395 0xa800 0x0 0x0 0x3 &ipic 22 0x8 396 0xa800 0x0 0x0 0x4 &ipic 23 0x8 397 398 /* IDSEL 0x16 */ 399 0xb000 0x0 0x0 0x1 &ipic 23 0x8 400 0xb000 0x0 0x0 0x2 &ipic 20 0x8 401 0xb000 0x0 0x0 0x3 &ipic 21 0x8 402 0xb000 0x0 0x0 0x4 &ipic 22 0x8 403 404 /* IDSEL 0x17 */ 405 0xb800 0x0 0x0 0x1 &ipic 22 0x8 406 0xb800 0x0 0x0 0x2 &ipic 23 0x8 407 0xb800 0x0 0x0 0x3 &ipic 20 0x8 408 0xb800 0x0 0x0 0x4 &ipic 21 0x8 409 410 /* IDSEL 0x18 */ 411 0xc000 0x0 0x0 0x1 &ipic 21 0x8 412 0xc000 0x0 0x0 0x2 &ipic 22 0x8 413 0xc000 0x0 0x0 0x3 &ipic 23 0x8 414 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; 415 interrupt-parent = <&ipic>; 416 interrupts = <66 0x8>; 417 bus-range = <0x0 0x0>; 418 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 419 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 420 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 421 clock-frequency = <0>; 422 sleep = <&pmc 0x00010000>; 423 #interrupt-cells = <1>; 424 #size-cells = <2>; 425 #address-cells = <3>; 426 reg = <0xe0008500 0x100 /* internal registers */ 427 0xe0008300 0x8>; /* config space access registers */ 428 compatible = "fsl,mpc8349-pci"; 429 device_type = "pci"; 430 }; 431 432 pci1: pcie@e0009000 { 433 #address-cells = <3>; 434 #size-cells = <2>; 435 #interrupt-cells = <1>; 436 device_type = "pci"; 437 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 438 reg = <0xe0009000 0x00001000>; 439 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 440 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; 441 bus-range = <0 255>; 442 interrupt-map-mask = <0xf800 0 0 7>; 443 interrupt-map = <0 0 0 1 &ipic 1 8 444 0 0 0 2 &ipic 1 8 445 0 0 0 3 &ipic 1 8 446 0 0 0 4 &ipic 1 8>; 447 sleep = <&pmc 0x00300000>; 448 clock-frequency = <0>; 449 450 pcie@0 { 451 #address-cells = <3>; 452 #size-cells = <2>; 453 device_type = "pci"; 454 reg = <0 0 0 0 0>; 455 ranges = <0x02000000 0 0xa8000000 456 0x02000000 0 0xa8000000 457 0 0x10000000 458 0x01000000 0 0x00000000 459 0x01000000 0 0x00000000 460 0 0x00800000>; 461 }; 462 }; 463 464 pci2: pcie@e000a000 { 465 #address-cells = <3>; 466 #size-cells = <2>; 467 #interrupt-cells = <1>; 468 device_type = "pci"; 469 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 470 reg = <0xe000a000 0x00001000>; 471 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 472 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; 473 bus-range = <0 255>; 474 interrupt-map-mask = <0xf800 0 0 7>; 475 interrupt-map = <0 0 0 1 &ipic 2 8 476 0 0 0 2 &ipic 2 8 477 0 0 0 3 &ipic 2 8 478 0 0 0 4 &ipic 2 8>; 479 sleep = <&pmc 0x000c0000>; 480 clock-frequency = <0>; 481 482 pcie@0 { 483 #address-cells = <3>; 484 #size-cells = <2>; 485 device_type = "pci"; 486 reg = <0 0 0 0 0>; 487 ranges = <0x02000000 0 0xc8000000 488 0x02000000 0 0xc8000000 489 0 0x10000000 490 0x01000000 0 0x00000000 491 0x01000000 0 0x00000000 492 0 0x00800000>; 493 }; 494 }; 495}; 496