1/* 2 * MPC8323E EMDS Device Tree Source 3 * 4 * Copyright 2006 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 11 * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do 12 * this: 13 * 14 * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board. 15 * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board 16 * next to the serial ports. 17 * 3) Solder a wire from U61-22 to P19K-22. 18 * 19 * Note that there's a typo in the schematic. The board labels the last column 20 * of pins "P19K", but in the schematic, that column is called "P19J". So if 21 * you're going by the schematic, the pin is called "P19J-K22". 22 */ 23 24/dts-v1/; 25 26/ { 27 model = "MPC8323EMDS"; 28 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS"; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 32 aliases { 33 ethernet0 = &enet0; 34 ethernet1 = &enet1; 35 serial0 = &serial0; 36 serial1 = &serial1; 37 pci0 = &pci0; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 PowerPC,8323@0 { 45 device_type = "cpu"; 46 reg = <0x0>; 47 d-cache-line-size = <32>; // 32 bytes 48 i-cache-line-size = <32>; // 32 bytes 49 d-cache-size = <16384>; // L1, 16K 50 i-cache-size = <16384>; // L1, 16K 51 timebase-frequency = <0>; 52 bus-frequency = <0>; 53 clock-frequency = <0>; 54 }; 55 }; 56 57 memory { 58 device_type = "memory"; 59 reg = <0x00000000 0x08000000>; 60 }; 61 62 bcsr@f8000000 { 63 compatible = "fsl,mpc8323mds-bcsr"; 64 reg = <0xf8000000 0x8000>; 65 }; 66 67 soc8323@e0000000 { 68 #address-cells = <1>; 69 #size-cells = <1>; 70 device_type = "soc"; 71 compatible = "simple-bus"; 72 ranges = <0x0 0xe0000000 0x00100000>; 73 reg = <0xe0000000 0x00000200>; 74 bus-frequency = <132000000>; 75 76 wdt@200 { 77 device_type = "watchdog"; 78 compatible = "mpc83xx_wdt"; 79 reg = <0x200 0x100>; 80 }; 81 82 pmc: power@b00 { 83 compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc"; 84 reg = <0xb00 0x100 0xa00 0x100>; 85 interrupts = <80 0x8>; 86 interrupt-parent = <&ipic>; 87 }; 88 89 i2c@3000 { 90 #address-cells = <1>; 91 #size-cells = <0>; 92 cell-index = <0>; 93 compatible = "fsl-i2c"; 94 reg = <0x3000 0x100>; 95 interrupts = <14 0x8>; 96 interrupt-parent = <&ipic>; 97 dfsrr; 98 99 rtc@68 { 100 compatible = "dallas,ds1374"; 101 reg = <0x68>; 102 }; 103 }; 104 105 serial0: serial@4500 { 106 cell-index = <0>; 107 device_type = "serial"; 108 compatible = "ns16550"; 109 reg = <0x4500 0x100>; 110 clock-frequency = <0>; 111 interrupts = <9 0x8>; 112 interrupt-parent = <&ipic>; 113 }; 114 115 serial1: serial@4600 { 116 cell-index = <1>; 117 device_type = "serial"; 118 compatible = "ns16550"; 119 reg = <0x4600 0x100>; 120 clock-frequency = <0>; 121 interrupts = <10 0x8>; 122 interrupt-parent = <&ipic>; 123 }; 124 125 dma@82a8 { 126 #address-cells = <1>; 127 #size-cells = <1>; 128 compatible = "fsl,mpc8323-dma", "fsl,elo-dma"; 129 reg = <0x82a8 4>; 130 ranges = <0 0x8100 0x1a8>; 131 interrupt-parent = <&ipic>; 132 interrupts = <71 8>; 133 cell-index = <0>; 134 dma-channel@0 { 135 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 136 reg = <0 0x80>; 137 cell-index = <0>; 138 interrupt-parent = <&ipic>; 139 interrupts = <71 8>; 140 }; 141 dma-channel@80 { 142 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 143 reg = <0x80 0x80>; 144 cell-index = <1>; 145 interrupt-parent = <&ipic>; 146 interrupts = <71 8>; 147 }; 148 dma-channel@100 { 149 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 150 reg = <0x100 0x80>; 151 cell-index = <2>; 152 interrupt-parent = <&ipic>; 153 interrupts = <71 8>; 154 }; 155 dma-channel@180 { 156 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel"; 157 reg = <0x180 0x28>; 158 cell-index = <3>; 159 interrupt-parent = <&ipic>; 160 interrupts = <71 8>; 161 }; 162 }; 163 164 crypto@30000 { 165 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; 166 reg = <0x30000 0x10000>; 167 interrupts = <11 0x8>; 168 interrupt-parent = <&ipic>; 169 fsl,num-channels = <1>; 170 fsl,channel-fifo-len = <24>; 171 fsl,exec-units-mask = <0x4c>; 172 fsl,descriptor-types-mask = <0x0122003f>; 173 sleep = <&pmc 0x03000000>; 174 }; 175 176 ipic: pic@700 { 177 interrupt-controller; 178 #address-cells = <0>; 179 #interrupt-cells = <2>; 180 reg = <0x700 0x100>; 181 device_type = "ipic"; 182 }; 183 184 par_io@1400 { 185 reg = <0x1400 0x100>; 186 device_type = "par_io"; 187 num-ports = <7>; 188 189 pio3: ucc_pin@03 { 190 pio-map = < 191 /* port pin dir open_drain assignment has_irq */ 192 3 4 3 0 2 0 /* MDIO */ 193 3 5 1 0 2 0 /* MDC */ 194 0 13 2 0 1 0 /* RX_CLK (CLK9) */ 195 3 24 2 0 1 0 /* TX_CLK (CLK10) */ 196 1 0 1 0 1 0 /* TxD0 */ 197 1 1 1 0 1 0 /* TxD1 */ 198 1 2 1 0 1 0 /* TxD2 */ 199 1 3 1 0 1 0 /* TxD3 */ 200 1 4 2 0 1 0 /* RxD0 */ 201 1 5 2 0 1 0 /* RxD1 */ 202 1 6 2 0 1 0 /* RxD2 */ 203 1 7 2 0 1 0 /* RxD3 */ 204 1 8 2 0 1 0 /* RX_ER */ 205 1 9 1 0 1 0 /* TX_ER */ 206 1 10 2 0 1 0 /* RX_DV */ 207 1 11 2 0 1 0 /* COL */ 208 1 12 1 0 1 0 /* TX_EN */ 209 1 13 2 0 1 0>; /* CRS */ 210 }; 211 pio4: ucc_pin@04 { 212 pio-map = < 213 /* port pin dir open_drain assignment has_irq */ 214 3 31 2 0 1 0 /* RX_CLK (CLK7) */ 215 3 6 2 0 1 0 /* TX_CLK (CLK8) */ 216 1 18 1 0 1 0 /* TxD0 */ 217 1 19 1 0 1 0 /* TxD1 */ 218 1 20 1 0 1 0 /* TxD2 */ 219 1 21 1 0 1 0 /* TxD3 */ 220 1 22 2 0 1 0 /* RxD0 */ 221 1 23 2 0 1 0 /* RxD1 */ 222 1 24 2 0 1 0 /* RxD2 */ 223 1 25 2 0 1 0 /* RxD3 */ 224 1 26 2 0 1 0 /* RX_ER */ 225 1 27 1 0 1 0 /* TX_ER */ 226 1 28 2 0 1 0 /* RX_DV */ 227 1 29 2 0 1 0 /* COL */ 228 1 30 1 0 1 0 /* TX_EN */ 229 1 31 2 0 1 0>; /* CRS */ 230 }; 231 pio5: ucc_pin@05 { 232 pio-map = < 233 /* 234 * open has 235 * port pin dir drain sel irq 236 */ 237 2 0 1 0 2 0 /* TxD5 */ 238 2 8 2 0 2 0 /* RxD5 */ 239 240 2 29 2 0 0 0 /* CTS5 */ 241 2 31 1 0 2 0 /* RTS5 */ 242 243 2 24 2 0 0 0 /* CD */ 244 245 >; 246 }; 247 248 }; 249 }; 250 251 qe@e0100000 { 252 #address-cells = <1>; 253 #size-cells = <1>; 254 device_type = "qe"; 255 compatible = "fsl,qe"; 256 ranges = <0x0 0xe0100000 0x00100000>; 257 reg = <0xe0100000 0x480>; 258 brg-frequency = <0>; 259 bus-frequency = <198000000>; 260 fsl,qe-num-riscs = <1>; 261 fsl,qe-num-snums = <28>; 262 263 muram@10000 { 264 #address-cells = <1>; 265 #size-cells = <1>; 266 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 267 ranges = <0x0 0x00010000 0x00004000>; 268 269 data-only@0 { 270 compatible = "fsl,qe-muram-data", 271 "fsl,cpm-muram-data"; 272 reg = <0x0 0x4000>; 273 }; 274 }; 275 276 spi@4c0 { 277 cell-index = <0>; 278 compatible = "fsl,spi"; 279 reg = <0x4c0 0x40>; 280 interrupts = <2>; 281 interrupt-parent = <&qeic>; 282 mode = "cpu"; 283 }; 284 285 spi@500 { 286 cell-index = <1>; 287 compatible = "fsl,spi"; 288 reg = <0x500 0x40>; 289 interrupts = <1>; 290 interrupt-parent = <&qeic>; 291 mode = "cpu"; 292 }; 293 294 usb@6c0 { 295 compatible = "qe_udc"; 296 reg = <0x6c0 0x40 0x8b00 0x100>; 297 interrupts = <11>; 298 interrupt-parent = <&qeic>; 299 mode = "slave"; 300 }; 301 302 enet0: ucc@2200 { 303 device_type = "network"; 304 compatible = "ucc_geth"; 305 cell-index = <3>; 306 reg = <0x2200 0x200>; 307 interrupts = <34>; 308 interrupt-parent = <&qeic>; 309 local-mac-address = [ 00 00 00 00 00 00 ]; 310 rx-clock-name = "clk9"; 311 tx-clock-name = "clk10"; 312 phy-handle = <&phy3>; 313 pio-handle = <&pio3>; 314 }; 315 316 enet1: ucc@3200 { 317 device_type = "network"; 318 compatible = "ucc_geth"; 319 cell-index = <4>; 320 reg = <0x3200 0x200>; 321 interrupts = <35>; 322 interrupt-parent = <&qeic>; 323 local-mac-address = [ 00 00 00 00 00 00 ]; 324 rx-clock-name = "clk7"; 325 tx-clock-name = "clk8"; 326 phy-handle = <&phy4>; 327 pio-handle = <&pio4>; 328 }; 329 330 ucc@2400 { 331 device_type = "serial"; 332 compatible = "ucc_uart"; 333 cell-index = <5>; /* The UCC number, 1-7*/ 334 port-number = <0>; /* Which ttyQEx device */ 335 soft-uart; /* We need Soft-UART */ 336 reg = <0x2400 0x200>; 337 interrupts = <40>; /* From Table 18-12 */ 338 interrupt-parent = < &qeic >; 339 /* 340 * For Soft-UART, we need to set TX to 1X, which 341 * means specifying separate clock sources. 342 */ 343 rx-clock-name = "brg5"; 344 tx-clock-name = "brg6"; 345 pio-handle = < &pio5 >; 346 }; 347 348 349 mdio@2320 { 350 #address-cells = <1>; 351 #size-cells = <0>; 352 reg = <0x2320 0x18>; 353 compatible = "fsl,ucc-mdio"; 354 355 phy3: ethernet-phy@03 { 356 interrupt-parent = <&ipic>; 357 interrupts = <17 0x8>; 358 reg = <0x3>; 359 device_type = "ethernet-phy"; 360 }; 361 phy4: ethernet-phy@04 { 362 interrupt-parent = <&ipic>; 363 interrupts = <18 0x8>; 364 reg = <0x4>; 365 device_type = "ethernet-phy"; 366 }; 367 }; 368 369 qeic: interrupt-controller@80 { 370 interrupt-controller; 371 compatible = "fsl,qe-ic"; 372 #address-cells = <0>; 373 #interrupt-cells = <1>; 374 reg = <0x80 0x80>; 375 big-endian; 376 interrupts = <32 0x8 33 0x8>; //high:32 low:33 377 interrupt-parent = <&ipic>; 378 }; 379 }; 380 381 pci0: pci@e0008500 { 382 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 383 interrupt-map = < 384 /* IDSEL 0x11 AD17 */ 385 0x8800 0x0 0x0 0x1 &ipic 20 0x8 386 0x8800 0x0 0x0 0x2 &ipic 21 0x8 387 0x8800 0x0 0x0 0x3 &ipic 22 0x8 388 0x8800 0x0 0x0 0x4 &ipic 23 0x8 389 390 /* IDSEL 0x12 AD18 */ 391 0x9000 0x0 0x0 0x1 &ipic 22 0x8 392 0x9000 0x0 0x0 0x2 &ipic 23 0x8 393 0x9000 0x0 0x0 0x3 &ipic 20 0x8 394 0x9000 0x0 0x0 0x4 &ipic 21 0x8 395 396 /* IDSEL 0x13 AD19 */ 397 0x9800 0x0 0x0 0x1 &ipic 23 0x8 398 0x9800 0x0 0x0 0x2 &ipic 20 0x8 399 0x9800 0x0 0x0 0x3 &ipic 21 0x8 400 0x9800 0x0 0x0 0x4 &ipic 22 0x8 401 402 /* IDSEL 0x15 AD21*/ 403 0xa800 0x0 0x0 0x1 &ipic 20 0x8 404 0xa800 0x0 0x0 0x2 &ipic 21 0x8 405 0xa800 0x0 0x0 0x3 &ipic 22 0x8 406 0xa800 0x0 0x0 0x4 &ipic 23 0x8 407 408 /* IDSEL 0x16 AD22*/ 409 0xb000 0x0 0x0 0x1 &ipic 23 0x8 410 0xb000 0x0 0x0 0x2 &ipic 20 0x8 411 0xb000 0x0 0x0 0x3 &ipic 21 0x8 412 0xb000 0x0 0x0 0x4 &ipic 22 0x8 413 414 /* IDSEL 0x17 AD23*/ 415 0xb800 0x0 0x0 0x1 &ipic 22 0x8 416 0xb800 0x0 0x0 0x2 &ipic 23 0x8 417 0xb800 0x0 0x0 0x3 &ipic 20 0x8 418 0xb800 0x0 0x0 0x4 &ipic 21 0x8 419 420 /* IDSEL 0x18 AD24*/ 421 0xc000 0x0 0x0 0x1 &ipic 21 0x8 422 0xc000 0x0 0x0 0x2 &ipic 22 0x8 423 0xc000 0x0 0x0 0x3 &ipic 23 0x8 424 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; 425 interrupt-parent = <&ipic>; 426 interrupts = <66 0x8>; 427 bus-range = <0x0 0x0>; 428 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 429 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 430 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>; 431 clock-frequency = <0>; 432 #interrupt-cells = <1>; 433 #size-cells = <2>; 434 #address-cells = <3>; 435 reg = <0xe0008500 0x100 /* internal registers */ 436 0xe0008300 0x8>; /* config space access registers */ 437 compatible = "fsl,mpc8349-pci"; 438 device_type = "pci"; 439 sleep = <&pmc 0x00010000>; 440 }; 441}; 442