1/* 2 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand) 3 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org> 4 * Copyright (C) 1999 SuSE GmbH 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21#ifndef _PARISC_ASSEMBLY_H 22#define _PARISC_ASSEMBLY_H 23 24#define CALLEE_FLOAT_FRAME_SIZE 80 25 26#ifdef CONFIG_64BIT 27#define LDREG ldd 28#define STREG std 29#define LDREGX ldd,s 30#define LDREGM ldd,mb 31#define STREGM std,ma 32#define SHRREG shrd 33#define SHLREG shld 34#define ANDCM andcm,* 35#define COND(x) * ## x 36#define RP_OFFSET 16 37#define FRAME_SIZE 128 38#define CALLEE_REG_FRAME_SIZE 144 39#define ASM_ULONG_INSN .dword 40#else /* CONFIG_64BIT */ 41#define LDREG ldw 42#define STREG stw 43#define LDREGX ldwx,s 44#define LDREGM ldwm 45#define STREGM stwm 46#define SHRREG shr 47#define SHLREG shlw 48#define ANDCM andcm 49#define COND(x) x 50#define RP_OFFSET 20 51#define FRAME_SIZE 64 52#define CALLEE_REG_FRAME_SIZE 128 53#define ASM_ULONG_INSN .word 54#endif 55 56#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE) 57 58#ifdef CONFIG_PA20 59#define LDCW ldcw,co 60#define BL b,l 61# ifdef CONFIG_64BIT 62# define LEVEL 2.0w 63# else 64# define LEVEL 2.0 65# endif 66#else 67#define LDCW ldcw 68#define BL bl 69#define LEVEL 1.1 70#endif 71 72#ifdef __ASSEMBLY__ 73 74#ifdef CONFIG_64BIT 75 .level 2.0w 76#endif 77 78#include <asm/asm-offsets.h> 79#include <asm/page.h> 80#include <asm/types.h> 81 82#include <asm/asmregs.h> 83 84 sp = 30 85 gp = 27 86 ipsw = 22 87 88 /* 89 * We provide two versions of each macro to convert from physical 90 * to virtual and vice versa. The "_r1" versions take one argument 91 * register, but trashes r1 to do the conversion. The other 92 * version takes two arguments: a src and destination register. 93 * However, the source and destination registers can not be 94 * the same register. 95 */ 96 97 .macro tophys grvirt, grphys 98 ldil L%(__PAGE_OFFSET), \grphys 99 sub \grvirt, \grphys, \grphys 100 .endm 101 102 .macro tovirt grphys, grvirt 103 ldil L%(__PAGE_OFFSET), \grvirt 104 add \grphys, \grvirt, \grvirt 105 .endm 106 107 .macro tophys_r1 gr 108 ldil L%(__PAGE_OFFSET), %r1 109 sub \gr, %r1, \gr 110 .endm 111 112 .macro tovirt_r1 gr 113 ldil L%(__PAGE_OFFSET), %r1 114 add \gr, %r1, \gr 115 .endm 116 117 .macro delay value 118 ldil L%\value, 1 119 ldo R%\value(1), 1 120 addib,UV,n -1,1,. 121 addib,NUV,n -1,1,.+8 122 nop 123 .endm 124 125 .macro debug value 126 .endm 127 128 129 /* Shift Left - note the r and t can NOT be the same! */ 130 .macro shl r, sa, t 131 dep,z \r, 31-(\sa), 32-(\sa), \t 132 .endm 133 134 /* The PA 2.0 shift left */ 135 .macro shlw r, sa, t 136 depw,z \r, 31-(\sa), 32-(\sa), \t 137 .endm 138 139 /* And the PA 2.0W shift left */ 140 .macro shld r, sa, t 141 depd,z \r, 63-(\sa), 64-(\sa), \t 142 .endm 143 144 /* Shift Right - note the r and t can NOT be the same! */ 145 .macro shr r, sa, t 146 extru \r, 31-(\sa), 32-(\sa), \t 147 .endm 148 149 /* pa20w version of shift right */ 150 .macro shrd r, sa, t 151 extrd,u \r, 63-(\sa), 64-(\sa), \t 152 .endm 153 154 /* load 32-bit 'value' into 'reg' compensating for the ldil 155 * sign-extension when running in wide mode. 156 * WARNING!! neither 'value' nor 'reg' can be expressions 157 * containing '.'!!!! */ 158 .macro load32 value, reg 159 ldil L%\value, \reg 160 ldo R%\value(\reg), \reg 161 .endm 162 163 .macro loadgp 164#ifdef CONFIG_64BIT 165 ldil L%__gp, %r27 166 ldo R%__gp(%r27), %r27 167#else 168 ldil L%$global$, %r27 169 ldo R%$global$(%r27), %r27 170#endif 171 .endm 172 173#define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where 174#define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r 175#define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where 176#define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r 177 178 .macro save_general regs 179 STREG %r1, PT_GR1 (\regs) 180 STREG %r2, PT_GR2 (\regs) 181 STREG %r3, PT_GR3 (\regs) 182 STREG %r4, PT_GR4 (\regs) 183 STREG %r5, PT_GR5 (\regs) 184 STREG %r6, PT_GR6 (\regs) 185 STREG %r7, PT_GR7 (\regs) 186 STREG %r8, PT_GR8 (\regs) 187 STREG %r9, PT_GR9 (\regs) 188 STREG %r10, PT_GR10(\regs) 189 STREG %r11, PT_GR11(\regs) 190 STREG %r12, PT_GR12(\regs) 191 STREG %r13, PT_GR13(\regs) 192 STREG %r14, PT_GR14(\regs) 193 STREG %r15, PT_GR15(\regs) 194 STREG %r16, PT_GR16(\regs) 195 STREG %r17, PT_GR17(\regs) 196 STREG %r18, PT_GR18(\regs) 197 STREG %r19, PT_GR19(\regs) 198 STREG %r20, PT_GR20(\regs) 199 STREG %r21, PT_GR21(\regs) 200 STREG %r22, PT_GR22(\regs) 201 STREG %r23, PT_GR23(\regs) 202 STREG %r24, PT_GR24(\regs) 203 STREG %r25, PT_GR25(\regs) 204 /* r26 is saved in get_stack and used to preserve a value across virt_map */ 205 STREG %r27, PT_GR27(\regs) 206 STREG %r28, PT_GR28(\regs) 207 /* r29 is saved in get_stack and used to point to saved registers */ 208 /* r30 stack pointer saved in get_stack */ 209 STREG %r31, PT_GR31(\regs) 210 .endm 211 212 .macro rest_general regs 213 /* r1 used as a temp in rest_stack and is restored there */ 214 LDREG PT_GR2 (\regs), %r2 215 LDREG PT_GR3 (\regs), %r3 216 LDREG PT_GR4 (\regs), %r4 217 LDREG PT_GR5 (\regs), %r5 218 LDREG PT_GR6 (\regs), %r6 219 LDREG PT_GR7 (\regs), %r7 220 LDREG PT_GR8 (\regs), %r8 221 LDREG PT_GR9 (\regs), %r9 222 LDREG PT_GR10(\regs), %r10 223 LDREG PT_GR11(\regs), %r11 224 LDREG PT_GR12(\regs), %r12 225 LDREG PT_GR13(\regs), %r13 226 LDREG PT_GR14(\regs), %r14 227 LDREG PT_GR15(\regs), %r15 228 LDREG PT_GR16(\regs), %r16 229 LDREG PT_GR17(\regs), %r17 230 LDREG PT_GR18(\regs), %r18 231 LDREG PT_GR19(\regs), %r19 232 LDREG PT_GR20(\regs), %r20 233 LDREG PT_GR21(\regs), %r21 234 LDREG PT_GR22(\regs), %r22 235 LDREG PT_GR23(\regs), %r23 236 LDREG PT_GR24(\regs), %r24 237 LDREG PT_GR25(\regs), %r25 238 LDREG PT_GR26(\regs), %r26 239 LDREG PT_GR27(\regs), %r27 240 LDREG PT_GR28(\regs), %r28 241 /* r29 points to register save area, and is restored in rest_stack */ 242 /* r30 stack pointer restored in rest_stack */ 243 LDREG PT_GR31(\regs), %r31 244 .endm 245 246 .macro save_fp regs 247 fstd,ma %fr0, 8(\regs) 248 fstd,ma %fr1, 8(\regs) 249 fstd,ma %fr2, 8(\regs) 250 fstd,ma %fr3, 8(\regs) 251 fstd,ma %fr4, 8(\regs) 252 fstd,ma %fr5, 8(\regs) 253 fstd,ma %fr6, 8(\regs) 254 fstd,ma %fr7, 8(\regs) 255 fstd,ma %fr8, 8(\regs) 256 fstd,ma %fr9, 8(\regs) 257 fstd,ma %fr10, 8(\regs) 258 fstd,ma %fr11, 8(\regs) 259 fstd,ma %fr12, 8(\regs) 260 fstd,ma %fr13, 8(\regs) 261 fstd,ma %fr14, 8(\regs) 262 fstd,ma %fr15, 8(\regs) 263 fstd,ma %fr16, 8(\regs) 264 fstd,ma %fr17, 8(\regs) 265 fstd,ma %fr18, 8(\regs) 266 fstd,ma %fr19, 8(\regs) 267 fstd,ma %fr20, 8(\regs) 268 fstd,ma %fr21, 8(\regs) 269 fstd,ma %fr22, 8(\regs) 270 fstd,ma %fr23, 8(\regs) 271 fstd,ma %fr24, 8(\regs) 272 fstd,ma %fr25, 8(\regs) 273 fstd,ma %fr26, 8(\regs) 274 fstd,ma %fr27, 8(\regs) 275 fstd,ma %fr28, 8(\regs) 276 fstd,ma %fr29, 8(\regs) 277 fstd,ma %fr30, 8(\regs) 278 fstd %fr31, 0(\regs) 279 .endm 280 281 .macro rest_fp regs 282 fldd 0(\regs), %fr31 283 fldd,mb -8(\regs), %fr30 284 fldd,mb -8(\regs), %fr29 285 fldd,mb -8(\regs), %fr28 286 fldd,mb -8(\regs), %fr27 287 fldd,mb -8(\regs), %fr26 288 fldd,mb -8(\regs), %fr25 289 fldd,mb -8(\regs), %fr24 290 fldd,mb -8(\regs), %fr23 291 fldd,mb -8(\regs), %fr22 292 fldd,mb -8(\regs), %fr21 293 fldd,mb -8(\regs), %fr20 294 fldd,mb -8(\regs), %fr19 295 fldd,mb -8(\regs), %fr18 296 fldd,mb -8(\regs), %fr17 297 fldd,mb -8(\regs), %fr16 298 fldd,mb -8(\regs), %fr15 299 fldd,mb -8(\regs), %fr14 300 fldd,mb -8(\regs), %fr13 301 fldd,mb -8(\regs), %fr12 302 fldd,mb -8(\regs), %fr11 303 fldd,mb -8(\regs), %fr10 304 fldd,mb -8(\regs), %fr9 305 fldd,mb -8(\regs), %fr8 306 fldd,mb -8(\regs), %fr7 307 fldd,mb -8(\regs), %fr6 308 fldd,mb -8(\regs), %fr5 309 fldd,mb -8(\regs), %fr4 310 fldd,mb -8(\regs), %fr3 311 fldd,mb -8(\regs), %fr2 312 fldd,mb -8(\regs), %fr1 313 fldd,mb -8(\regs), %fr0 314 .endm 315 316 .macro callee_save_float 317 fstd,ma %fr12, 8(%r30) 318 fstd,ma %fr13, 8(%r30) 319 fstd,ma %fr14, 8(%r30) 320 fstd,ma %fr15, 8(%r30) 321 fstd,ma %fr16, 8(%r30) 322 fstd,ma %fr17, 8(%r30) 323 fstd,ma %fr18, 8(%r30) 324 fstd,ma %fr19, 8(%r30) 325 fstd,ma %fr20, 8(%r30) 326 fstd,ma %fr21, 8(%r30) 327 .endm 328 329 .macro callee_rest_float 330 fldd,mb -8(%r30), %fr21 331 fldd,mb -8(%r30), %fr20 332 fldd,mb -8(%r30), %fr19 333 fldd,mb -8(%r30), %fr18 334 fldd,mb -8(%r30), %fr17 335 fldd,mb -8(%r30), %fr16 336 fldd,mb -8(%r30), %fr15 337 fldd,mb -8(%r30), %fr14 338 fldd,mb -8(%r30), %fr13 339 fldd,mb -8(%r30), %fr12 340 .endm 341 342#ifdef CONFIG_64BIT 343 .macro callee_save 344 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 345 mfctl %cr27, %r3 346 std %r4, -136(%r30) 347 std %r5, -128(%r30) 348 std %r6, -120(%r30) 349 std %r7, -112(%r30) 350 std %r8, -104(%r30) 351 std %r9, -96(%r30) 352 std %r10, -88(%r30) 353 std %r11, -80(%r30) 354 std %r12, -72(%r30) 355 std %r13, -64(%r30) 356 std %r14, -56(%r30) 357 std %r15, -48(%r30) 358 std %r16, -40(%r30) 359 std %r17, -32(%r30) 360 std %r18, -24(%r30) 361 std %r3, -16(%r30) 362 .endm 363 364 .macro callee_rest 365 ldd -16(%r30), %r3 366 ldd -24(%r30), %r18 367 ldd -32(%r30), %r17 368 ldd -40(%r30), %r16 369 ldd -48(%r30), %r15 370 ldd -56(%r30), %r14 371 ldd -64(%r30), %r13 372 ldd -72(%r30), %r12 373 ldd -80(%r30), %r11 374 ldd -88(%r30), %r10 375 ldd -96(%r30), %r9 376 ldd -104(%r30), %r8 377 ldd -112(%r30), %r7 378 ldd -120(%r30), %r6 379 ldd -128(%r30), %r5 380 ldd -136(%r30), %r4 381 mtctl %r3, %cr27 382 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 383 .endm 384 385#else /* ! CONFIG_64BIT */ 386 387 .macro callee_save 388 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 389 mfctl %cr27, %r3 390 stw %r4, -124(%r30) 391 stw %r5, -120(%r30) 392 stw %r6, -116(%r30) 393 stw %r7, -112(%r30) 394 stw %r8, -108(%r30) 395 stw %r9, -104(%r30) 396 stw %r10, -100(%r30) 397 stw %r11, -96(%r30) 398 stw %r12, -92(%r30) 399 stw %r13, -88(%r30) 400 stw %r14, -84(%r30) 401 stw %r15, -80(%r30) 402 stw %r16, -76(%r30) 403 stw %r17, -72(%r30) 404 stw %r18, -68(%r30) 405 stw %r3, -64(%r30) 406 .endm 407 408 .macro callee_rest 409 ldw -64(%r30), %r3 410 ldw -68(%r30), %r18 411 ldw -72(%r30), %r17 412 ldw -76(%r30), %r16 413 ldw -80(%r30), %r15 414 ldw -84(%r30), %r14 415 ldw -88(%r30), %r13 416 ldw -92(%r30), %r12 417 ldw -96(%r30), %r11 418 ldw -100(%r30), %r10 419 ldw -104(%r30), %r9 420 ldw -108(%r30), %r8 421 ldw -112(%r30), %r7 422 ldw -116(%r30), %r6 423 ldw -120(%r30), %r5 424 ldw -124(%r30), %r4 425 mtctl %r3, %cr27 426 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 427 .endm 428#endif /* ! CONFIG_64BIT */ 429 430 .macro save_specials regs 431 432 SAVE_SP (%sr0, PT_SR0 (\regs)) 433 SAVE_SP (%sr1, PT_SR1 (\regs)) 434 SAVE_SP (%sr2, PT_SR2 (\regs)) 435 SAVE_SP (%sr3, PT_SR3 (\regs)) 436 SAVE_SP (%sr4, PT_SR4 (\regs)) 437 SAVE_SP (%sr5, PT_SR5 (\regs)) 438 SAVE_SP (%sr6, PT_SR6 (\regs)) 439 SAVE_SP (%sr7, PT_SR7 (\regs)) 440 441 SAVE_CR (%cr17, PT_IASQ0(\regs)) 442 mtctl %r0, %cr17 443 SAVE_CR (%cr17, PT_IASQ1(\regs)) 444 445 SAVE_CR (%cr18, PT_IAOQ0(\regs)) 446 mtctl %r0, %cr18 447 SAVE_CR (%cr18, PT_IAOQ1(\regs)) 448 449#ifdef CONFIG_64BIT 450 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0 451 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only 452 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise 453 * we lose the 6th bit on a save/restore over interrupt. 454 */ 455 mfctl,w %cr11, %r1 456 STREG %r1, PT_SAR (\regs) 457#else 458 SAVE_CR (%cr11, PT_SAR (\regs)) 459#endif 460 SAVE_CR (%cr19, PT_IIR (\regs)) 461 462 /* 463 * Code immediately following this macro (in intr_save) relies 464 * on r8 containing ipsw. 465 */ 466 mfctl %cr22, %r8 467 STREG %r8, PT_PSW(\regs) 468 .endm 469 470 .macro rest_specials regs 471 472 REST_SP (%sr0, PT_SR0 (\regs)) 473 REST_SP (%sr1, PT_SR1 (\regs)) 474 REST_SP (%sr2, PT_SR2 (\regs)) 475 REST_SP (%sr3, PT_SR3 (\regs)) 476 REST_SP (%sr4, PT_SR4 (\regs)) 477 REST_SP (%sr5, PT_SR5 (\regs)) 478 REST_SP (%sr6, PT_SR6 (\regs)) 479 REST_SP (%sr7, PT_SR7 (\regs)) 480 481 REST_CR (%cr17, PT_IASQ0(\regs)) 482 REST_CR (%cr17, PT_IASQ1(\regs)) 483 484 REST_CR (%cr18, PT_IAOQ0(\regs)) 485 REST_CR (%cr18, PT_IAOQ1(\regs)) 486 487 REST_CR (%cr11, PT_SAR (\regs)) 488 489 REST_CR (%cr22, PT_PSW (\regs)) 490 .endm 491 492 493 /* First step to create a "relied upon translation" 494 * See PA 2.0 Arch. page F-4 and F-5. 495 * 496 * The ssm was originally necessary due to a "PCxT bug". 497 * But someone decided it needed to be added to the architecture 498 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual. 499 * It's been carried forward into PA 2.0 Arch as well. :^( 500 * 501 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier). 502 * rsm/ssm prevents the ifetch unit from speculatively fetching 503 * instructions past this line in the code stream. 504 * PA 2.0 processor will single step all insn in the same QUAD (4 insn). 505 */ 506 .macro pcxt_ssm_bug 507 rsm PSW_SM_I,%r0 508 nop /* 1 */ 509 nop /* 2 */ 510 nop /* 3 */ 511 nop /* 4 */ 512 nop /* 5 */ 513 nop /* 6 */ 514 nop /* 7 */ 515 .endm 516 517#endif /* __ASSEMBLY__ */ 518#endif 519