1/* 2 * RouterBoard 500 Platform devices 3 * 4 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> 5 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17#include <linux/kernel.h> 18#include <linux/init.h> 19#include <linux/ctype.h> 20#include <linux/string.h> 21#include <linux/platform_device.h> 22#include <linux/mtd/nand.h> 23#include <linux/mtd/mtd.h> 24#include <linux/mtd/partitions.h> 25#include <linux/gpio_keys.h> 26#include <linux/input.h> 27#include <linux/serial_8250.h> 28 29#include <asm/bootinfo.h> 30 31#include <asm/mach-rc32434/rc32434.h> 32#include <asm/mach-rc32434/dma.h> 33#include <asm/mach-rc32434/dma_v.h> 34#include <asm/mach-rc32434/eth.h> 35#include <asm/mach-rc32434/rb.h> 36#include <asm/mach-rc32434/integ.h> 37#include <asm/mach-rc32434/gpio.h> 38#include <asm/mach-rc32434/irq.h> 39 40#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET) 41#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET) 42 43extern unsigned int idt_cpu_freq; 44 45static struct mpmc_device dev3; 46 47void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) 48{ 49 unsigned long flags; 50 51 spin_lock_irqsave(&dev3.lock, flags); 52 53 dev3.state = (dev3.state | or_mask) & ~nand_mask; 54 writeb(dev3.state, dev3.base); 55 56 spin_unlock_irqrestore(&dev3.lock, flags); 57} 58EXPORT_SYMBOL(set_latch_u5); 59 60unsigned char get_latch_u5(void) 61{ 62 return dev3.state; 63} 64EXPORT_SYMBOL(get_latch_u5); 65 66static struct resource korina_dev0_res[] = { 67 { 68 .name = "korina_regs", 69 .start = ETH0_BASE_ADDR, 70 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs), 71 .flags = IORESOURCE_MEM, 72 }, { 73 .name = "korina_rx", 74 .start = ETH0_DMA_RX_IRQ, 75 .end = ETH0_DMA_RX_IRQ, 76 .flags = IORESOURCE_IRQ 77 }, { 78 .name = "korina_tx", 79 .start = ETH0_DMA_TX_IRQ, 80 .end = ETH0_DMA_TX_IRQ, 81 .flags = IORESOURCE_IRQ 82 }, { 83 .name = "korina_ovr", 84 .start = ETH0_RX_OVR_IRQ, 85 .end = ETH0_RX_OVR_IRQ, 86 .flags = IORESOURCE_IRQ 87 }, { 88 .name = "korina_und", 89 .start = ETH0_TX_UND_IRQ, 90 .end = ETH0_TX_UND_IRQ, 91 .flags = IORESOURCE_IRQ 92 }, { 93 .name = "korina_dma_rx", 94 .start = ETH0_RX_DMA_ADDR, 95 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1, 96 .flags = IORESOURCE_MEM, 97 }, { 98 .name = "korina_dma_tx", 99 .start = ETH0_TX_DMA_ADDR, 100 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1, 101 .flags = IORESOURCE_MEM, 102 } 103}; 104 105static struct korina_device korina_dev0_data = { 106 .name = "korina0", 107 .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee} 108}; 109 110static struct platform_device korina_dev0 = { 111 .id = -1, 112 .name = "korina", 113 .resource = korina_dev0_res, 114 .num_resources = ARRAY_SIZE(korina_dev0_res), 115}; 116 117static struct resource cf_slot0_res[] = { 118 { 119 .name = "cf_membase", 120 .flags = IORESOURCE_MEM 121 }, { 122 .name = "cf_irq", 123 .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */ 124 .end = (8 + 4 * 32 + CF_GPIO_NUM), 125 .flags = IORESOURCE_IRQ 126 } 127}; 128 129static struct cf_device cf_slot0_data = { 130 .gpio_pin = CF_GPIO_NUM 131}; 132 133static struct platform_device cf_slot0 = { 134 .id = -1, 135 .name = "pata-rb532-cf", 136 .dev.platform_data = &cf_slot0_data, 137 .resource = cf_slot0_res, 138 .num_resources = ARRAY_SIZE(cf_slot0_res), 139}; 140 141/* Resources and device for NAND */ 142static int rb532_dev_ready(struct mtd_info *mtd) 143{ 144 return gpio_get_value(GPIO_RDY); 145} 146 147static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) 148{ 149 struct nand_chip *chip = mtd->priv; 150 unsigned char orbits, nandbits; 151 152 if (ctrl & NAND_CTRL_CHANGE) { 153 orbits = (ctrl & NAND_CLE) << 1; 154 orbits |= (ctrl & NAND_ALE) >> 1; 155 156 nandbits = (~ctrl & NAND_CLE) << 1; 157 nandbits |= (~ctrl & NAND_ALE) >> 1; 158 159 set_latch_u5(orbits, nandbits); 160 } 161 if (cmd != NAND_CMD_NONE) 162 writeb(cmd, chip->IO_ADDR_W); 163} 164 165static struct resource nand_slot0_res[] = { 166 [0] = { 167 .name = "nand_membase", 168 .flags = IORESOURCE_MEM 169 } 170}; 171 172static struct platform_nand_data rb532_nand_data = { 173 .ctrl.dev_ready = rb532_dev_ready, 174 .ctrl.cmd_ctrl = rb532_cmd_ctrl, 175}; 176 177static struct platform_device nand_slot0 = { 178 .name = "gen_nand", 179 .id = -1, 180 .resource = nand_slot0_res, 181 .num_resources = ARRAY_SIZE(nand_slot0_res), 182 .dev.platform_data = &rb532_nand_data, 183}; 184 185static struct mtd_partition rb532_partition_info[] = { 186 { 187 .name = "Routerboard NAND boot", 188 .offset = 0, 189 .size = 4 * 1024 * 1024, 190 }, { 191 .name = "rootfs", 192 .offset = MTDPART_OFS_NXTBLK, 193 .size = MTDPART_SIZ_FULL, 194 } 195}; 196 197static struct platform_device rb532_led = { 198 .name = "rb532-led", 199 .id = -1, 200}; 201 202static struct platform_device rb532_button = { 203 .name = "rb532-button", 204 .id = -1, 205}; 206 207static struct resource rb532_wdt_res[] = { 208 { 209 .name = "rb532_wdt_res", 210 .start = INTEG0_BASE_ADDR, 211 .end = INTEG0_BASE_ADDR + sizeof(struct integ), 212 .flags = IORESOURCE_MEM, 213 } 214}; 215 216static struct platform_device rb532_wdt = { 217 .name = "rc32434_wdt", 218 .id = -1, 219 .resource = rb532_wdt_res, 220 .num_resources = ARRAY_SIZE(rb532_wdt_res), 221}; 222 223static struct plat_serial8250_port rb532_uart_res[] = { 224 { 225 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE), 226 .irq = UART0_IRQ, 227 .regshift = 2, 228 .iotype = UPIO_MEM, 229 .flags = UPF_BOOT_AUTOCONF, 230 }, 231 { 232 .flags = 0, 233 } 234}; 235 236static struct platform_device rb532_uart = { 237 .name = "serial8250", 238 .id = PLAT8250_DEV_PLATFORM, 239 .dev.platform_data = &rb532_uart_res, 240}; 241 242static struct platform_device *rb532_devs[] = { 243 &korina_dev0, 244 &nand_slot0, 245 &cf_slot0, 246 &rb532_led, 247 &rb532_button, 248 &rb532_uart, 249 &rb532_wdt 250}; 251 252static void __init parse_mac_addr(char *macstr) 253{ 254 int i, j; 255 unsigned char result, value; 256 257 for (i = 0; i < 6; i++) { 258 result = 0; 259 260 if (i != 5 && *(macstr + 2) != ':') 261 return; 262 263 for (j = 0; j < 2; j++) { 264 if (isxdigit(*macstr) 265 && (value = 266 isdigit(*macstr) ? *macstr - 267 '0' : toupper(*macstr) - 'A' + 10) < 16) { 268 result = result * 16 + value; 269 macstr++; 270 } else 271 return; 272 } 273 274 macstr++; 275 korina_dev0_data.mac[i] = result; 276 } 277} 278 279 280/* NAND definitions */ 281#define NAND_CHIP_DELAY 25 282 283static void __init rb532_nand_setup(void) 284{ 285 switch (mips_machtype) { 286 case MACH_MIKROTIK_RB532A: 287 set_latch_u5(LO_FOFF | LO_CEX, 288 LO_ULED | LO_ALE | LO_CLE | LO_WPX); 289 break; 290 default: 291 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX, 292 LO_ULED | LO_ALE | LO_CLE); 293 break; 294 } 295 296 /* Setup NAND specific settings */ 297 rb532_nand_data.chip.nr_chips = 1; 298 rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info); 299 rb532_nand_data.chip.partitions = rb532_partition_info; 300 rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY; 301 rb532_nand_data.chip.options = NAND_NO_AUTOINCR; 302} 303 304 305static int __init plat_setup_devices(void) 306{ 307 /* Look for the CF card reader */ 308 if (!readl(IDT434_REG_BASE + DEV1MASK)) 309 rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */ 310 else { 311 cf_slot0_res[0].start = 312 readl(IDT434_REG_BASE + DEV1BASE); 313 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; 314 } 315 316 /* Read the NAND resources from the device controller */ 317 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE); 318 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; 319 320 /* Read and map device controller 3 */ 321 dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1); 322 323 if (!dev3.base) { 324 printk(KERN_ERR "rb532: cannot remap device controller 3\n"); 325 return -ENXIO; 326 } 327 328 /* Initialise the NAND device */ 329 rb532_nand_setup(); 330 331 /* set the uart clock to the current cpu frequency */ 332 rb532_uart_res[0].uartclk = idt_cpu_freq; 333 334 dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data); 335 336 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs)); 337} 338 339static int __init setup_kmac(char *s) 340{ 341 printk(KERN_INFO "korina mac = %s\n", s); 342 parse_mac_addr(s); 343 return 0; 344} 345 346__setup("kmac=", setup_kmac); 347 348arch_initcall(plat_setup_devices); 349