1/* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000, 2001, 2004, 2011 MIPS Technologies, Inc. 4 * Copyright (C) 2001 Ralf Baechle 5 * 6 * This program is free software; you can distribute it and/or modify it 7 * under the terms of the GNU General Public License (Version 2) as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 18 * 19 * Routines for generic manipulation of the interrupts found on the MIPS 20 * Malta board. 21 * The interrupt controller is located in the South Bridge a PIIX4 device 22 * with two internal 82C95 interrupt controllers. 23 */ 24#include <linux/init.h> 25#include <linux/irq.h> 26#include <linux/sched.h> 27#include <linux/smp.h> 28#include <linux/interrupt.h> 29#include <linux/io.h> 30#include <linux/kernel_stat.h> 31#include <linux/kernel.h> 32#include <linux/random.h> 33 34#include <asm/traps.h> 35#include <asm/i8259.h> 36#include <asm/irq_cpu.h> 37#include <asm/irq_regs.h> 38#include <asm/mips-boards/malta.h> 39#include <asm/mips-boards/maltaint.h> 40#include <asm/mips-boards/piix4.h> 41#include <asm/gt64120.h> 42#include <asm/mips-boards/generic.h> 43#include <asm/mips-boards/msc01_pci.h> 44#include <asm/msc01_ic.h> 45#include <asm/gic.h> 46#include <asm/gcmpregs.h> 47 48int gcmp_present = -1; 49int gic_present; 50static unsigned long _msc01_biu_base; 51static unsigned long _gcmp_base; 52static unsigned int ipi_map[NR_CPUS]; 53 54static DEFINE_RAW_SPINLOCK(mips_irq_lock); 55 56static inline int mips_pcibios_iack(void) 57{ 58 int irq; 59 60 /* 61 * Determine highest priority pending interrupt by performing 62 * a PCI Interrupt Acknowledge cycle. 63 */ 64 switch (mips_revision_sconid) { 65 case MIPS_REVISION_SCON_SOCIT: 66 case MIPS_REVISION_SCON_ROCIT: 67 case MIPS_REVISION_SCON_SOCITSC: 68 case MIPS_REVISION_SCON_SOCITSCP: 69 MSC_READ(MSC01_PCI_IACK, irq); 70 irq &= 0xff; 71 break; 72 case MIPS_REVISION_SCON_GT64120: 73 irq = GT_READ(GT_PCI0_IACK_OFS); 74 irq &= 0xff; 75 break; 76 case MIPS_REVISION_SCON_BONITO: 77 /* The following will generate a PCI IACK cycle on the 78 * Bonito controller. It's a little bit kludgy, but it 79 * was the easiest way to implement it in hardware at 80 * the given time. 81 */ 82 BONITO_PCIMAP_CFG = 0x20000; 83 84 /* Flush Bonito register block */ 85 (void) BONITO_PCIMAP_CFG; 86 iob(); /* sync */ 87 88 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); 89 iob(); /* sync */ 90 irq &= 0xff; 91 BONITO_PCIMAP_CFG = 0; 92 break; 93 default: 94 printk(KERN_WARNING "Unknown system controller.\n"); 95 return -1; 96 } 97 return irq; 98} 99 100static inline int get_int(void) 101{ 102 unsigned long flags; 103 int irq; 104 raw_spin_lock_irqsave(&mips_irq_lock, flags); 105 106 irq = mips_pcibios_iack(); 107 108 /* 109 * The only way we can decide if an interrupt is spurious 110 * is by checking the 8259 registers. This needs a spinlock 111 * on an SMP system, so leave it up to the generic code... 112 */ 113 114 raw_spin_unlock_irqrestore(&mips_irq_lock, flags); 115 116 return irq; 117} 118 119static void malta_hw0_irqdispatch(void) 120{ 121 int irq; 122 123 irq = get_int(); 124 if (irq < 0) { 125 /* interrupt has already been cleared */ 126 return; 127 } 128 129 do_IRQ(MALTA_INT_BASE + irq); 130} 131 132static void malta_ipi_irqdispatch(void) 133{ 134 int irq; 135 136 irq = gic_get_int(); 137 if (irq < 0) 138 return; /* interrupt has already been cleared */ 139 140 do_IRQ(MIPS_GIC_IRQ_BASE + irq); 141} 142 143static void corehi_irqdispatch(void) 144{ 145 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 146 unsigned int pcimstat, intisr, inten, intpol; 147 unsigned int intrcause, datalo, datahi; 148 struct pt_regs *regs = get_irq_regs(); 149 150 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); 151 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" 152 "Cause : %08lx\nbadVaddr : %08lx\n", 153 regs->cp0_epc, regs->cp0_status, 154 regs->cp0_cause, regs->cp0_badvaddr); 155 156 /* Read all the registers and then print them as there is a 157 problem with interspersed printk's upsetting the Bonito controller. 158 Do it for the others too. 159 */ 160 161 switch (mips_revision_sconid) { 162 case MIPS_REVISION_SCON_SOCIT: 163 case MIPS_REVISION_SCON_ROCIT: 164 case MIPS_REVISION_SCON_SOCITSC: 165 case MIPS_REVISION_SCON_SOCITSCP: 166 ll_msc_irq(); 167 break; 168 case MIPS_REVISION_SCON_GT64120: 169 intrcause = GT_READ(GT_INTRCAUSE_OFS); 170 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); 171 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); 172 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); 173 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", 174 datahi, datalo); 175 break; 176 case MIPS_REVISION_SCON_BONITO: 177 pcibadaddr = BONITO_PCIBADADDR; 178 pcimstat = BONITO_PCIMSTAT; 179 intisr = BONITO_INTISR; 180 inten = BONITO_INTEN; 181 intpol = BONITO_INTPOL; 182 intedge = BONITO_INTEDGE; 183 intsteer = BONITO_INTSTEER; 184 pcicmd = BONITO_PCICMD; 185 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); 186 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); 187 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); 188 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); 189 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); 190 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); 191 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); 192 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); 193 break; 194 } 195 196 die("CoreHi interrupt", regs); 197} 198 199static inline int clz(unsigned long x) 200{ 201 __asm__( 202 " .set push \n" 203 " .set mips32 \n" 204 " clz %0, %1 \n" 205 " .set pop \n" 206 : "=r" (x) 207 : "r" (x)); 208 209 return x; 210} 211 212/* 213 * Version of ffs that only looks at bits 12..15. 214 */ 215static inline unsigned int irq_ffs(unsigned int pending) 216{ 217#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 218 return -clz(pending) + 31 - CAUSEB_IP; 219#else 220 unsigned int a0 = 7; 221 unsigned int t0; 222 223 t0 = pending & 0xf000; 224 t0 = t0 < 1; 225 t0 = t0 << 2; 226 a0 = a0 - t0; 227 pending = pending << t0; 228 229 t0 = pending & 0xc000; 230 t0 = t0 < 1; 231 t0 = t0 << 1; 232 a0 = a0 - t0; 233 pending = pending << t0; 234 235 t0 = pending & 0x8000; 236 t0 = t0 < 1; 237 /* t0 = t0 << 2; */ 238 a0 = a0 - t0; 239 /* pending = pending << t0; */ 240 241 return a0; 242#endif 243} 244 245/* 246 * IRQs on the Malta board look basically (barring software IRQs which we 247 * don't use at all and all external interrupt sources are combined together 248 * on hardware interrupt 0 (MIPS IRQ 2)) like: 249 * 250 * MIPS IRQ Source 251 * -------- ------ 252 * 0 Software (ignored) 253 * 1 Software (ignored) 254 * 2 Combined hardware interrupt (hw0) 255 * 3 Hardware (ignored) 256 * 4 Hardware (ignored) 257 * 5 Hardware (ignored) 258 * 6 Hardware (ignored) 259 * 7 R4k timer (what we use) 260 * 261 * We handle the IRQ according to _our_ priority which is: 262 * 263 * Highest ---- R4k Timer 264 * Lowest ---- Combined hardware interrupt 265 * 266 * then we just return, if multiple IRQs are pending then we will just take 267 * another exception, big deal. 268 */ 269 270asmlinkage void plat_irq_dispatch(void) 271{ 272 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 273 int irq; 274 275 irq = irq_ffs(pending); 276 277 if (irq == MIPSCPU_INT_I8259A) 278 malta_hw0_irqdispatch(); 279 else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()])) 280 malta_ipi_irqdispatch(); 281 else if (irq >= 0) 282 do_IRQ(MIPS_CPU_IRQ_BASE + irq); 283 else 284 spurious_interrupt(); 285} 286 287#ifdef CONFIG_MIPS_MT_SMP 288 289 290#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3 291#define GIC_MIPS_CPU_IPI_CALL_IRQ 4 292 293#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ 294#define C_RESCHED C_SW0 295#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ 296#define C_CALL C_SW1 297static int cpu_ipi_resched_irq, cpu_ipi_call_irq; 298 299static void ipi_resched_dispatch(void) 300{ 301 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); 302} 303 304static void ipi_call_dispatch(void) 305{ 306 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); 307} 308 309static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 310{ 311 return IRQ_HANDLED; 312} 313 314static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) 315{ 316 smp_call_function_interrupt(); 317 318 return IRQ_HANDLED; 319} 320 321static struct irqaction irq_resched = { 322 .handler = ipi_resched_interrupt, 323 .flags = IRQF_DISABLED|IRQF_PERCPU, 324 .name = "IPI_resched" 325}; 326 327static struct irqaction irq_call = { 328 .handler = ipi_call_interrupt, 329 .flags = IRQF_DISABLED|IRQF_PERCPU, 330 .name = "IPI_call" 331}; 332#endif /* CONFIG_MIPS_MT_SMP */ 333 334static int gic_resched_int_base; 335static int gic_call_int_base; 336#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu)) 337#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu)) 338 339unsigned int plat_ipi_call_int_xlate(unsigned int cpu) 340{ 341 return GIC_CALL_INT(cpu); 342} 343 344unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) 345{ 346 return GIC_RESCHED_INT(cpu); 347} 348 349static struct irqaction i8259irq = { 350 .handler = no_action, 351 .name = "XT-PIC cascade" 352}; 353 354static struct irqaction corehi_irqaction = { 355 .handler = no_action, 356 .name = "CoreHi" 357}; 358 359static msc_irqmap_t __initdata msc_irqmap[] = { 360 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, 361 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, 362}; 363static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); 364 365static msc_irqmap_t __initdata msc_eicirqmap[] = { 366 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, 367 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, 368 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, 369 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, 370 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, 371 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, 372 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, 373 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, 374 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, 375 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} 376}; 377 378static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); 379 380/* 381 * This GIC specific tabular array defines the association between External 382 * Interrupts and CPUs/Core Interrupts. The nature of the External 383 * Interrupts is also defined here - polarity/trigger. 384 */ 385 386#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK 387#define X GIC_UNUSED 388 389static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { 390 { X, X, X, X, 0 }, 391 { X, X, X, X, 0 }, 392 { X, X, X, X, 0 }, 393 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 394 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 395 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 396 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 397 { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 398 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 399 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 400 { X, X, X, X, 0 }, 401 { X, X, X, X, 0 }, 402 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 403 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 404 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 405 { X, X, X, X, 0 }, 406 /* The remainder of this table is initialised by fill_ipi_map */ 407}; 408#undef X 409 410/* 411 * GCMP needs to be detected before any SMP initialisation 412 */ 413int __init gcmp_probe(unsigned long addr, unsigned long size) 414{ 415 if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { 416 gcmp_present = 0; 417 return gcmp_present; 418 } 419 420 if (gcmp_present >= 0) 421 return gcmp_present; 422 423 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); 424 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); 425 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; 426 427 if (gcmp_present) 428 pr_debug("GCMP present\n"); 429 return gcmp_present; 430} 431 432/* Return the number of IOCU's present */ 433int __init gcmp_niocu(void) 434{ 435 return gcmp_present ? 436 (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : 437 0; 438} 439 440/* Set GCMP region attributes */ 441void __init gcmp_setregion(int region, unsigned long base, 442 unsigned long mask, int type) 443{ 444 GCMPGCBn(CMxBASE, region) = base; 445 GCMPGCBn(CMxMASK, region) = mask | type; 446} 447 448#if defined(CONFIG_MIPS_MT_SMP) 449static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) 450{ 451 int intr = baseintr + cpu; 452 gic_intr_map[intr].cpunum = cpu; 453 gic_intr_map[intr].pin = cpupin; 454 gic_intr_map[intr].polarity = GIC_POL_POS; 455 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; 456 gic_intr_map[intr].flags = GIC_FLAG_IPI; 457 ipi_map[cpu] |= (1 << (cpupin + 2)); 458} 459 460static void __init fill_ipi_map(void) 461{ 462 int cpu; 463 464 for (cpu = 0; cpu < NR_CPUS; cpu++) { 465 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1); 466 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2); 467 } 468} 469#endif 470 471void __init arch_init_ipiirq(int irq, struct irqaction *action) 472{ 473 setup_irq(irq, action); 474 set_irq_handler(irq, handle_percpu_irq); 475} 476 477void __init arch_init_irq(void) 478{ 479 init_i8259_irqs(); 480 481 if (!cpu_has_veic) 482 mips_cpu_irq_init(); 483 484 if (gcmp_present) { 485 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; 486 gic_present = 1; 487 } else { 488 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { 489 _msc01_biu_base = (unsigned long) 490 ioremap_nocache(MSC01_BIU_REG_BASE, 491 MSC01_BIU_ADDRSPACE_SZ); 492 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & 493 MSC01_SC_CFG_GICPRES_MSK) >> 494 MSC01_SC_CFG_GICPRES_SHF; 495 } 496 } 497 if (gic_present) 498 pr_debug("GIC present\n"); 499 500 switch (mips_revision_sconid) { 501 case MIPS_REVISION_SCON_SOCIT: 502 case MIPS_REVISION_SCON_ROCIT: 503 if (cpu_has_veic) 504 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, 505 MSC01E_INT_BASE, msc_eicirqmap, 506 msc_nr_eicirqs); 507 else 508 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, 509 MSC01C_INT_BASE, msc_irqmap, 510 msc_nr_irqs); 511 break; 512 513 case MIPS_REVISION_SCON_SOCITSC: 514 case MIPS_REVISION_SCON_SOCITSCP: 515 if (cpu_has_veic) 516 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, 517 MSC01E_INT_BASE, msc_eicirqmap, 518 msc_nr_eicirqs); 519 else 520 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, 521 MSC01C_INT_BASE, msc_irqmap, 522 msc_nr_irqs); 523 } 524 525 if (cpu_has_veic) { 526 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); 527 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); 528 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 529 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 530 } else if (cpu_has_vint) { 531 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 532 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); 533#ifdef CONFIG_MIPS_MT_SMTC 534 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, 535 (0x100 << MIPSCPU_INT_I8259A)); 536 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 537 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); 538 /* 539 * Temporary hack to ensure that the subsidiary device 540 * interrupts coing in via the i8259A, but associated 541 * with low IRQ numbers, will restore the Status.IM 542 * value associated with the i8259A. 543 */ 544 { 545 int i; 546 547 for (i = 0; i < 16; i++) 548 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); 549 } 550#else /* Not SMTC */ 551 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 552 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 553 &corehi_irqaction); 554#endif /* CONFIG_MIPS_MT_SMTC */ 555 } else { 556 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 557 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 558 &corehi_irqaction); 559 } 560 561 if (gic_present) { 562 int i; 563#if defined(CONFIG_MIPS_MT_SMP) 564 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; 565 gic_resched_int_base = gic_call_int_base - NR_CPUS; 566 fill_ipi_map(); 567#endif 568 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, 569 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); 570 if (!gcmp_present) { 571 /* Enable the GIC */ 572 i = REG(_msc01_biu_base, MSC01_SC_CFG); 573 REG(_msc01_biu_base, MSC01_SC_CFG) = 574 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); 575 pr_debug("GIC Enabled\n"); 576 } 577#if defined(CONFIG_MIPS_MT_SMP) 578 /* set up ipi interrupts */ 579 if (cpu_has_vint) { 580 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); 581 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); 582 } 583 /* Argh.. this really needs sorting out.. */ 584 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status()); 585 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); 586 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); 587 write_c0_status(0x1100dc00); 588 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 589 for (i = 0; i < NR_CPUS; i++) { 590 arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 591 GIC_RESCHED_INT(i), &irq_resched); 592 arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 593 GIC_CALL_INT(i), &irq_call); 594 } 595#endif 596 } else { 597#if defined(CONFIG_MIPS_MT_SMP) 598 /* set up ipi interrupts */ 599 if (cpu_has_veic) { 600 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); 601 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); 602 cpu_ipi_resched_irq = MSC01E_INT_SW0; 603 cpu_ipi_call_irq = MSC01E_INT_SW1; 604 } else { 605 if (cpu_has_vint) { 606 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); 607 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); 608 } 609 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 610 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 611 } 612 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); 613 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); 614#endif 615 } 616} 617 618void malta_be_init(void) 619{ 620 if (gcmp_present) { 621 /* Could change CM error mask register */ 622 } 623} 624 625 626static char *tr[8] = { 627 "mem", "gcr", "gic", "mmio", 628 "0x04", "0x05", "0x06", "0x07" 629}; 630 631static char *mcmd[32] = { 632 [0x00] = "0x00", 633 [0x01] = "Legacy Write", 634 [0x02] = "Legacy Read", 635 [0x03] = "0x03", 636 [0x04] = "0x04", 637 [0x05] = "0x05", 638 [0x06] = "0x06", 639 [0x07] = "0x07", 640 [0x08] = "Coherent Read Own", 641 [0x09] = "Coherent Read Share", 642 [0x0a] = "Coherent Read Discard", 643 [0x0b] = "Coherent Ready Share Always", 644 [0x0c] = "Coherent Upgrade", 645 [0x0d] = "Coherent Writeback", 646 [0x0e] = "0x0e", 647 [0x0f] = "0x0f", 648 [0x10] = "Coherent Copyback", 649 [0x11] = "Coherent Copyback Invalidate", 650 [0x12] = "Coherent Invalidate", 651 [0x13] = "Coherent Write Invalidate", 652 [0x14] = "Coherent Completion Sync", 653 [0x15] = "0x15", 654 [0x16] = "0x16", 655 [0x17] = "0x17", 656 [0x18] = "0x18", 657 [0x19] = "0x19", 658 [0x1a] = "0x1a", 659 [0x1b] = "0x1b", 660 [0x1c] = "0x1c", 661 [0x1d] = "0x1d", 662 [0x1e] = "0x1e", 663 [0x1f] = "0x1f" 664}; 665 666static char *core[8] = { 667 "Invalid/OK", "Invalid/Data", 668 "Shared/OK", "Shared/Data", 669 "Modified/OK", "Modified/Data", 670 "Exclusive/OK", "Exclusive/Data" 671}; 672 673static char *causes[32] = { 674 "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR", 675 "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07", 676 "0x08", "0x09", "0x0a", "0x0b", 677 "0x0c", "0x0d", "0x0e", "0x0f", 678 "0x10", "0x11", "0x12", "0x13", 679 "0x14", "0x15", "0x16", "INTVN_WR_ERR", 680 "INTVN_RD_ERR", "0x19", "0x1a", "0x1b", 681 "0x1c", "0x1d", "0x1e", "0x1f" 682}; 683 684int malta_be_handler(struct pt_regs *regs, int is_fixup) 685{ 686 /* This duplicates the handling in do_be which seems wrong */ 687 int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; 688 689 if (gcmp_present) { 690 unsigned long cm_error = GCMPGCB(GCMEC); 691 unsigned long cm_addr = GCMPGCB(GCMEA); 692 unsigned long cm_other = GCMPGCB(GCMEO); 693 unsigned long cause, ocause; 694 char buf[256]; 695 696 cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK); 697 if (cause != 0) { 698 cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF; 699 if (cause < 16) { 700 unsigned long cca_bits = (cm_error >> 15) & 7; 701 unsigned long tr_bits = (cm_error >> 12) & 7; 702 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f; 703 unsigned long stag_bits = (cm_error >> 3) & 15; 704 unsigned long sport_bits = (cm_error >> 0) & 7; 705 706 snprintf(buf, sizeof(buf), 707 "CCA=%lu TR=%s MCmd=%s STag=%lu " 708 "SPort=%lu\n", 709 cca_bits, tr[tr_bits], mcmd[mcmd_bits], 710 stag_bits, sport_bits); 711 } else { 712 /* glob state & sresp together */ 713 unsigned long c3_bits = (cm_error >> 18) & 7; 714 unsigned long c2_bits = (cm_error >> 15) & 7; 715 unsigned long c1_bits = (cm_error >> 12) & 7; 716 unsigned long c0_bits = (cm_error >> 9) & 7; 717 unsigned long sc_bit = (cm_error >> 8) & 1; 718 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f; 719 unsigned long sport_bits = (cm_error >> 0) & 7; 720 snprintf(buf, sizeof(buf), 721 "C3=%s C2=%s C1=%s C0=%s SC=%s " 722 "MCmd=%s SPort=%lu\n", 723 core[c3_bits], core[c2_bits], 724 core[c1_bits], core[c0_bits], 725 sc_bit ? "True" : "False", 726 mcmd[mcmd_bits], sport_bits); 727 } 728 729 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> 730 GCMP_GCB_GMEO_ERROR_2ND_SHF; 731 732 printk("CM_ERROR=%08lx %s <%s>\n", cm_error, 733 causes[cause], buf); 734 printk("CM_ADDR =%08lx\n", cm_addr); 735 printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); 736 737 /* reprime cause register */ 738 GCMPGCB(GCMEC) = 0; 739 } 740 } 741 742 return retval; 743} 744 745#ifdef CONFIG_HOTPLUG_CPU 746void fixup_irqs(void) 747{ 748 pr_debug("CPU%d: fixup_irqs\n", smp_processor_id()); 749} 750#endif 751