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  • only in /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/mips/kernel/
1/*
2 * Copyright (C) 2008 Scientific-Atlanta, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17 */
18/*
19 * The file comes from kernel/csrc-r4k.c
20 */
21#include <linux/clocksource.h>
22#include <linux/init.h>
23
24#include <asm/time.h>			/* Not included in linux/time.h */
25
26#include <asm/mach-powertv/asic_regs.h>
27#include "powertv-clock.h"
28
29/* MIPS PLL Register Definitions */
30#define PLL_GET_M(x)		(((x) >> 8) & 0x000000FF)
31#define PLL_GET_N(x)		(((x) >> 16) & 0x000000FF)
32#define PLL_GET_P(x)		(((x) >> 24) & 0x00000007)
33
34/*
35 * returns:  Clock frequency in kHz
36 */
37unsigned int __init mips_get_pll_freq(void)
38{
39	unsigned int pll_reg, m, n, p;
40	unsigned int fin = 54000; /* Base frequency in kHz */
41	unsigned int fout;
42
43	/* Read PLL register setting */
44	pll_reg = asic_read(mips_pll_setup);
45	m = PLL_GET_M(pll_reg);
46	n = PLL_GET_N(pll_reg);
47	p = PLL_GET_P(pll_reg);
48	pr_info("MIPS PLL Register:0x%x  M=%d  N=%d  P=%d\n", pll_reg, m, n, p);
49
50	/* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
51	fout = ((2 * n * fin) / (m * (0x01 << p)));
52
53	pr_info("MIPS Clock Freq=%d kHz\n", fout);
54
55	return fout;
56}
57
58static cycle_t c0_hpt_read(struct clocksource *cs)
59{
60	return read_c0_count();
61}
62
63static struct clocksource clocksource_mips = {
64	.name		= "powertv-counter",
65	.read		= c0_hpt_read,
66	.mask		= CLOCKSOURCE_MASK(32),
67	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
68};
69
70static void __init powertv_c0_hpt_clocksource_init(void)
71{
72	unsigned int pll_freq = mips_get_pll_freq();
73
74	pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000,
75		(pll_freq % 1000) * 100 / 1000);
76
77	mips_hpt_frequency = pll_freq / 2 * 1000;
78
79	clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
80
81	clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
82
83	clocksource_register(&clocksource_mips);
84}
85
86/**
87 * struct tim_c - free running counter
88 * @hi:	High 16 bits of the counter
89 * @lo:	Low 32 bits of the counter
90 *
91 * Lays out the structure of the free running counter in memory. This counter
92 * increments at a rate of 27 MHz/8 on all platforms.
93 */
94struct tim_c {
95	unsigned int hi;
96	unsigned int lo;
97};
98
99static struct tim_c *tim_c;
100
101static cycle_t tim_c_read(struct clocksource *cs)
102{
103	unsigned int hi;
104	unsigned int next_hi;
105	unsigned int lo;
106
107	hi = readl(&tim_c->hi);
108
109	for (;;) {
110		lo = readl(&tim_c->lo);
111		next_hi = readl(&tim_c->hi);
112		if (next_hi == hi)
113			break;
114		hi = next_hi;
115	}
116
117pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo);
118	return ((u64) hi << 32) | lo;
119}
120
121#define TIM_C_SIZE		48		/* # bits in the timer */
122
123static struct clocksource clocksource_tim_c = {
124	.name		= "powertv-tim_c",
125	.read		= tim_c_read,
126	.mask		= CLOCKSOURCE_MASK(TIM_C_SIZE),
127	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
128};
129
130/**
131 * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
132 *
133 * The hard part here is coming up with a constant k and shift s such that
134 * the 48-bit TIM_C value multiplied by k doesn't overflow and that value,
135 * when shifted right by s, yields the corresponding number of nanoseconds.
136 * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
137 * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the
138 * number of nanoseconds. Since the TIM_C value has 48 bits and the math is
139 * done in 64 bits, avoiding an overflow means that k must be less than
140 * 64 - 48 = 16 bits.
141 */
142static void __init powertv_tim_c_clocksource_init(void)
143{
144	int			prescale;
145	unsigned long		dividend;
146	unsigned long		k;
147	int			s;
148	const int		max_k_bits = (64 - 48) - 1;
149	const unsigned long	billion = 1000000000;
150	const unsigned long	counts_per_second = 27000000 / 8;
151
152	prescale = BITS_PER_LONG - ilog2(billion) - 1;
153	dividend = billion << prescale;
154	k = dividend / counts_per_second;
155	s = ilog2(k) - max_k_bits;
156
157	if (s < 0)
158		s = prescale;
159
160	else {
161		k >>= s;
162		s += prescale;
163	}
164
165	clocksource_tim_c.mult = k;
166	clocksource_tim_c.shift = s;
167	clocksource_tim_c.rating = 200;
168
169	clocksource_register(&clocksource_tim_c);
170	tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
171}
172
173/**
174 powertv_clocksource_init - initialize all clocksources
175 */
176void __init powertv_clocksource_init(void)
177{
178	powertv_c0_hpt_clocksource_init();
179	powertv_tim_c_clocksource_init();
180}
181