1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle 7 * Copyright (C) 2007 Maciej W. Rozycki 8 */ 9#ifndef _ASM_WAR_H 10#define _ASM_WAR_H 11 12#include <war.h> 13 14#ifdef CONFIG_CPU_R4000_WORKAROUNDS 15#define R4000_WAR 1 16#else 17#define R4000_WAR 0 18#endif 19 20#ifdef CONFIG_CPU_R4400_WORKAROUNDS 21#define R4400_WAR 1 22#else 23#define R4400_WAR 0 24#endif 25 26#ifdef CONFIG_CPU_DADDI_WORKAROUNDS 27#define DADDI_WAR 1 28#else 29#define DADDI_WAR 0 30#endif 31 32/* 33 * Another R4600 erratum. Due to the lack of errata information the exact 34 * technical details aren't known. I've experimentally found that disabling 35 * interrupts during indexed I-cache flushes seems to be sufficient to deal 36 * with the issue. 37 */ 38#ifndef R4600_V1_INDEX_ICACHEOP_WAR 39#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform 40#endif 41 42/* 43 * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: 44 * 45 * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, 46 * Hit_Invalidate_D and Create_Dirty_Excl_D should only be 47 * executed if there is no other dcache activity. If the dcache is 48 * accessed for another instruction immeidately preceding when these 49 * cache instructions are executing, it is possible that the dcache 50 * tag match outputs used by these cache instructions will be 51 * incorrect. These cache instructions should be preceded by at least 52 * four instructions that are not any kind of load or store 53 * instruction. 54 * 55 * This is not allowed: lw 56 * nop 57 * nop 58 * nop 59 * cache Hit_Writeback_Invalidate_D 60 * 61 * This is allowed: lw 62 * nop 63 * nop 64 * nop 65 * nop 66 * cache Hit_Writeback_Invalidate_D 67 */ 68#ifndef R4600_V1_HIT_CACHEOP_WAR 69#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform 70#endif 71 72 73/* 74 * Writeback and invalidate the primary cache dcache before DMA. 75 * 76 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, 77 * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only 78 * operate correctly if the internal data cache refill buffer is empty. These 79 * CACHE instructions should be separated from any potential data cache miss 80 * by a load instruction to an uncached address to empty the response buffer." 81 * (Revision 2.0 device errata from IDT available on http://www.idt.com/ 82 * in .pdf format.) 83 */ 84#ifndef R4600_V2_HIT_CACHEOP_WAR 85#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform 86#endif 87 88#ifndef R5432_CP0_INTERRUPT_WAR 89#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform 90#endif 91 92#ifndef BCM1250_M3_WAR 93#error Check setting of BCM1250_M3_WAR for your platform 94#endif 95 96#ifndef SIBYTE_1956_WAR 97#error Check setting of SIBYTE_1956_WAR for your platform 98#endif 99 100#ifndef MIPS4K_ICACHE_REFILL_WAR 101#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform 102#endif 103 104#ifndef MIPS_CACHE_SYNC_WAR 105#error Check setting of MIPS_CACHE_SYNC_WAR for your platform 106#endif 107 108#ifndef TX49XX_ICACHE_INDEX_INV_WAR 109#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform 110#endif 111 112/* 113 * On the RM9000 there is a problem which makes the CreateDirtyExclusive 114 * eache operation unusable on SMP systems. 115 */ 116#ifndef RM9000_CDEX_SMP_WAR 117#error Check setting of RM9000_CDEX_SMP_WAR for your platform 118#endif 119 120/* 121 * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra 122 * opposes it being called that) where invalid instructions in the same 123 * I-cache line worth of instructions being fetched may case spurious 124 * exceptions. 125 */ 126#ifndef ICACHE_REFILLS_WORKAROUND_WAR 127#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform 128#endif 129 130/* 131 * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that 132 * may cause ll / sc and lld / scd sequences to execute non-atomically. 133 */ 134#ifndef R10000_LLSC_WAR 135#error Check setting of R10000_LLSC_WAR for your platform 136#endif 137 138/* 139 * 34K core erratum: "Problems Executing the TLBR Instruction" 140 */ 141#ifndef MIPS34K_MISSED_ITLB_WAR 142#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform 143#endif 144 145#endif /* _ASM_WAR_H */ 146