1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_PESCX_DEFS_H__ 29#define __CVMX_PESCX_DEFS_H__ 30 31#define CVMX_PESCX_BIST_STATUS(block_id) \ 32 CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull)) 33#define CVMX_PESCX_BIST_STATUS2(block_id) \ 34 CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull)) 35#define CVMX_PESCX_CFG_RD(block_id) \ 36 CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull)) 37#define CVMX_PESCX_CFG_WR(block_id) \ 38 CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull)) 39#define CVMX_PESCX_CPL_LUT_VALID(block_id) \ 40 CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull)) 41#define CVMX_PESCX_CTL_STATUS(block_id) \ 42 CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull)) 43#define CVMX_PESCX_CTL_STATUS2(block_id) \ 44 CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull)) 45#define CVMX_PESCX_DBG_INFO(block_id) \ 46 CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull)) 47#define CVMX_PESCX_DBG_INFO_EN(block_id) \ 48 CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull)) 49#define CVMX_PESCX_DIAG_STATUS(block_id) \ 50 CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull)) 51#define CVMX_PESCX_P2N_BAR0_START(block_id) \ 52 CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull)) 53#define CVMX_PESCX_P2N_BAR1_START(block_id) \ 54 CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull)) 55#define CVMX_PESCX_P2N_BAR2_START(block_id) \ 56 CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull)) 57#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \ 58 CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull)) 59#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \ 60 CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull)) 61#define CVMX_PESCX_TLP_CREDITS(block_id) \ 62 CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull)) 63 64union cvmx_pescx_bist_status { 65 uint64_t u64; 66 struct cvmx_pescx_bist_status_s { 67 uint64_t reserved_13_63:51; 68 uint64_t rqdata5:1; 69 uint64_t ctlp_or:1; 70 uint64_t ntlp_or:1; 71 uint64_t ptlp_or:1; 72 uint64_t retry:1; 73 uint64_t rqdata0:1; 74 uint64_t rqdata1:1; 75 uint64_t rqdata2:1; 76 uint64_t rqdata3:1; 77 uint64_t rqdata4:1; 78 uint64_t rqhdr1:1; 79 uint64_t rqhdr0:1; 80 uint64_t sot:1; 81 } s; 82 struct cvmx_pescx_bist_status_s cn52xx; 83 struct cvmx_pescx_bist_status_cn52xxp1 { 84 uint64_t reserved_12_63:52; 85 uint64_t ctlp_or:1; 86 uint64_t ntlp_or:1; 87 uint64_t ptlp_or:1; 88 uint64_t retry:1; 89 uint64_t rqdata0:1; 90 uint64_t rqdata1:1; 91 uint64_t rqdata2:1; 92 uint64_t rqdata3:1; 93 uint64_t rqdata4:1; 94 uint64_t rqhdr1:1; 95 uint64_t rqhdr0:1; 96 uint64_t sot:1; 97 } cn52xxp1; 98 struct cvmx_pescx_bist_status_s cn56xx; 99 struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1; 100}; 101 102union cvmx_pescx_bist_status2 { 103 uint64_t u64; 104 struct cvmx_pescx_bist_status2_s { 105 uint64_t reserved_14_63:50; 106 uint64_t cto_p2e:1; 107 uint64_t e2p_cpl:1; 108 uint64_t e2p_n:1; 109 uint64_t e2p_p:1; 110 uint64_t e2p_rsl:1; 111 uint64_t dbg_p2e:1; 112 uint64_t peai_p2e:1; 113 uint64_t rsl_p2e:1; 114 uint64_t pef_tpf1:1; 115 uint64_t pef_tpf0:1; 116 uint64_t pef_tnf:1; 117 uint64_t pef_tcf1:1; 118 uint64_t pef_tc0:1; 119 uint64_t ppf:1; 120 } s; 121 struct cvmx_pescx_bist_status2_s cn52xx; 122 struct cvmx_pescx_bist_status2_s cn52xxp1; 123 struct cvmx_pescx_bist_status2_s cn56xx; 124 struct cvmx_pescx_bist_status2_s cn56xxp1; 125}; 126 127union cvmx_pescx_cfg_rd { 128 uint64_t u64; 129 struct cvmx_pescx_cfg_rd_s { 130 uint64_t data:32; 131 uint64_t addr:32; 132 } s; 133 struct cvmx_pescx_cfg_rd_s cn52xx; 134 struct cvmx_pescx_cfg_rd_s cn52xxp1; 135 struct cvmx_pescx_cfg_rd_s cn56xx; 136 struct cvmx_pescx_cfg_rd_s cn56xxp1; 137}; 138 139union cvmx_pescx_cfg_wr { 140 uint64_t u64; 141 struct cvmx_pescx_cfg_wr_s { 142 uint64_t data:32; 143 uint64_t addr:32; 144 } s; 145 struct cvmx_pescx_cfg_wr_s cn52xx; 146 struct cvmx_pescx_cfg_wr_s cn52xxp1; 147 struct cvmx_pescx_cfg_wr_s cn56xx; 148 struct cvmx_pescx_cfg_wr_s cn56xxp1; 149}; 150 151union cvmx_pescx_cpl_lut_valid { 152 uint64_t u64; 153 struct cvmx_pescx_cpl_lut_valid_s { 154 uint64_t reserved_32_63:32; 155 uint64_t tag:32; 156 } s; 157 struct cvmx_pescx_cpl_lut_valid_s cn52xx; 158 struct cvmx_pescx_cpl_lut_valid_s cn52xxp1; 159 struct cvmx_pescx_cpl_lut_valid_s cn56xx; 160 struct cvmx_pescx_cpl_lut_valid_s cn56xxp1; 161}; 162 163union cvmx_pescx_ctl_status { 164 uint64_t u64; 165 struct cvmx_pescx_ctl_status_s { 166 uint64_t reserved_28_63:36; 167 uint64_t dnum:5; 168 uint64_t pbus:8; 169 uint64_t qlm_cfg:2; 170 uint64_t lane_swp:1; 171 uint64_t pm_xtoff:1; 172 uint64_t pm_xpme:1; 173 uint64_t ob_p_cmd:1; 174 uint64_t reserved_7_8:2; 175 uint64_t nf_ecrc:1; 176 uint64_t dly_one:1; 177 uint64_t lnk_enb:1; 178 uint64_t ro_ctlp:1; 179 uint64_t reserved_2_2:1; 180 uint64_t inv_ecrc:1; 181 uint64_t inv_lcrc:1; 182 } s; 183 struct cvmx_pescx_ctl_status_s cn52xx; 184 struct cvmx_pescx_ctl_status_s cn52xxp1; 185 struct cvmx_pescx_ctl_status_cn56xx { 186 uint64_t reserved_28_63:36; 187 uint64_t dnum:5; 188 uint64_t pbus:8; 189 uint64_t qlm_cfg:2; 190 uint64_t reserved_12_12:1; 191 uint64_t pm_xtoff:1; 192 uint64_t pm_xpme:1; 193 uint64_t ob_p_cmd:1; 194 uint64_t reserved_7_8:2; 195 uint64_t nf_ecrc:1; 196 uint64_t dly_one:1; 197 uint64_t lnk_enb:1; 198 uint64_t ro_ctlp:1; 199 uint64_t reserved_2_2:1; 200 uint64_t inv_ecrc:1; 201 uint64_t inv_lcrc:1; 202 } cn56xx; 203 struct cvmx_pescx_ctl_status_cn56xx cn56xxp1; 204}; 205 206union cvmx_pescx_ctl_status2 { 207 uint64_t u64; 208 struct cvmx_pescx_ctl_status2_s { 209 uint64_t reserved_2_63:62; 210 uint64_t pclk_run:1; 211 uint64_t pcierst:1; 212 } s; 213 struct cvmx_pescx_ctl_status2_s cn52xx; 214 struct cvmx_pescx_ctl_status2_cn52xxp1 { 215 uint64_t reserved_1_63:63; 216 uint64_t pcierst:1; 217 } cn52xxp1; 218 struct cvmx_pescx_ctl_status2_s cn56xx; 219 struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1; 220}; 221 222union cvmx_pescx_dbg_info { 223 uint64_t u64; 224 struct cvmx_pescx_dbg_info_s { 225 uint64_t reserved_31_63:33; 226 uint64_t ecrc_e:1; 227 uint64_t rawwpp:1; 228 uint64_t racpp:1; 229 uint64_t ramtlp:1; 230 uint64_t rarwdns:1; 231 uint64_t caar:1; 232 uint64_t racca:1; 233 uint64_t racur:1; 234 uint64_t rauc:1; 235 uint64_t rqo:1; 236 uint64_t fcuv:1; 237 uint64_t rpe:1; 238 uint64_t fcpvwt:1; 239 uint64_t dpeoosd:1; 240 uint64_t rtwdle:1; 241 uint64_t rdwdle:1; 242 uint64_t mre:1; 243 uint64_t rte:1; 244 uint64_t acto:1; 245 uint64_t rvdm:1; 246 uint64_t rumep:1; 247 uint64_t rptamrc:1; 248 uint64_t rpmerc:1; 249 uint64_t rfemrc:1; 250 uint64_t rnfemrc:1; 251 uint64_t rcemrc:1; 252 uint64_t rpoison:1; 253 uint64_t recrce:1; 254 uint64_t rtlplle:1; 255 uint64_t rtlpmal:1; 256 uint64_t spoison:1; 257 } s; 258 struct cvmx_pescx_dbg_info_s cn52xx; 259 struct cvmx_pescx_dbg_info_s cn52xxp1; 260 struct cvmx_pescx_dbg_info_s cn56xx; 261 struct cvmx_pescx_dbg_info_s cn56xxp1; 262}; 263 264union cvmx_pescx_dbg_info_en { 265 uint64_t u64; 266 struct cvmx_pescx_dbg_info_en_s { 267 uint64_t reserved_31_63:33; 268 uint64_t ecrc_e:1; 269 uint64_t rawwpp:1; 270 uint64_t racpp:1; 271 uint64_t ramtlp:1; 272 uint64_t rarwdns:1; 273 uint64_t caar:1; 274 uint64_t racca:1; 275 uint64_t racur:1; 276 uint64_t rauc:1; 277 uint64_t rqo:1; 278 uint64_t fcuv:1; 279 uint64_t rpe:1; 280 uint64_t fcpvwt:1; 281 uint64_t dpeoosd:1; 282 uint64_t rtwdle:1; 283 uint64_t rdwdle:1; 284 uint64_t mre:1; 285 uint64_t rte:1; 286 uint64_t acto:1; 287 uint64_t rvdm:1; 288 uint64_t rumep:1; 289 uint64_t rptamrc:1; 290 uint64_t rpmerc:1; 291 uint64_t rfemrc:1; 292 uint64_t rnfemrc:1; 293 uint64_t rcemrc:1; 294 uint64_t rpoison:1; 295 uint64_t recrce:1; 296 uint64_t rtlplle:1; 297 uint64_t rtlpmal:1; 298 uint64_t spoison:1; 299 } s; 300 struct cvmx_pescx_dbg_info_en_s cn52xx; 301 struct cvmx_pescx_dbg_info_en_s cn52xxp1; 302 struct cvmx_pescx_dbg_info_en_s cn56xx; 303 struct cvmx_pescx_dbg_info_en_s cn56xxp1; 304}; 305 306union cvmx_pescx_diag_status { 307 uint64_t u64; 308 struct cvmx_pescx_diag_status_s { 309 uint64_t reserved_4_63:60; 310 uint64_t pm_dst:1; 311 uint64_t pm_stat:1; 312 uint64_t pm_en:1; 313 uint64_t aux_en:1; 314 } s; 315 struct cvmx_pescx_diag_status_s cn52xx; 316 struct cvmx_pescx_diag_status_s cn52xxp1; 317 struct cvmx_pescx_diag_status_s cn56xx; 318 struct cvmx_pescx_diag_status_s cn56xxp1; 319}; 320 321union cvmx_pescx_p2n_bar0_start { 322 uint64_t u64; 323 struct cvmx_pescx_p2n_bar0_start_s { 324 uint64_t addr:50; 325 uint64_t reserved_0_13:14; 326 } s; 327 struct cvmx_pescx_p2n_bar0_start_s cn52xx; 328 struct cvmx_pescx_p2n_bar0_start_s cn52xxp1; 329 struct cvmx_pescx_p2n_bar0_start_s cn56xx; 330 struct cvmx_pescx_p2n_bar0_start_s cn56xxp1; 331}; 332 333union cvmx_pescx_p2n_bar1_start { 334 uint64_t u64; 335 struct cvmx_pescx_p2n_bar1_start_s { 336 uint64_t addr:38; 337 uint64_t reserved_0_25:26; 338 } s; 339 struct cvmx_pescx_p2n_bar1_start_s cn52xx; 340 struct cvmx_pescx_p2n_bar1_start_s cn52xxp1; 341 struct cvmx_pescx_p2n_bar1_start_s cn56xx; 342 struct cvmx_pescx_p2n_bar1_start_s cn56xxp1; 343}; 344 345union cvmx_pescx_p2n_bar2_start { 346 uint64_t u64; 347 struct cvmx_pescx_p2n_bar2_start_s { 348 uint64_t addr:25; 349 uint64_t reserved_0_38:39; 350 } s; 351 struct cvmx_pescx_p2n_bar2_start_s cn52xx; 352 struct cvmx_pescx_p2n_bar2_start_s cn52xxp1; 353 struct cvmx_pescx_p2n_bar2_start_s cn56xx; 354 struct cvmx_pescx_p2n_bar2_start_s cn56xxp1; 355}; 356 357union cvmx_pescx_p2p_barx_end { 358 uint64_t u64; 359 struct cvmx_pescx_p2p_barx_end_s { 360 uint64_t addr:52; 361 uint64_t reserved_0_11:12; 362 } s; 363 struct cvmx_pescx_p2p_barx_end_s cn52xx; 364 struct cvmx_pescx_p2p_barx_end_s cn52xxp1; 365 struct cvmx_pescx_p2p_barx_end_s cn56xx; 366 struct cvmx_pescx_p2p_barx_end_s cn56xxp1; 367}; 368 369union cvmx_pescx_p2p_barx_start { 370 uint64_t u64; 371 struct cvmx_pescx_p2p_barx_start_s { 372 uint64_t addr:52; 373 uint64_t reserved_0_11:12; 374 } s; 375 struct cvmx_pescx_p2p_barx_start_s cn52xx; 376 struct cvmx_pescx_p2p_barx_start_s cn52xxp1; 377 struct cvmx_pescx_p2p_barx_start_s cn56xx; 378 struct cvmx_pescx_p2p_barx_start_s cn56xxp1; 379}; 380 381union cvmx_pescx_tlp_credits { 382 uint64_t u64; 383 struct cvmx_pescx_tlp_credits_s { 384 uint64_t reserved_0_63:64; 385 } s; 386 struct cvmx_pescx_tlp_credits_cn52xx { 387 uint64_t reserved_56_63:8; 388 uint64_t peai_ppf:8; 389 uint64_t pesc_cpl:8; 390 uint64_t pesc_np:8; 391 uint64_t pesc_p:8; 392 uint64_t npei_cpl:8; 393 uint64_t npei_np:8; 394 uint64_t npei_p:8; 395 } cn52xx; 396 struct cvmx_pescx_tlp_credits_cn52xxp1 { 397 uint64_t reserved_38_63:26; 398 uint64_t peai_ppf:8; 399 uint64_t pesc_cpl:5; 400 uint64_t pesc_np:5; 401 uint64_t pesc_p:5; 402 uint64_t npei_cpl:5; 403 uint64_t npei_np:5; 404 uint64_t npei_p:5; 405 } cn52xxp1; 406 struct cvmx_pescx_tlp_credits_cn52xx cn56xx; 407 struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1; 408}; 409 410#endif 411