1/* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 4 * 5 * This program is free software; you can distribute it and/or modify it 6 * under the terms of the GNU General Public License (Version 2) as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 18 * Defines of the MIPS boards specific address-MAP, registers, etc. 19 */ 20#ifndef __ASM_MIPS_BOARDS_GENERIC_H 21#define __ASM_MIPS_BOARDS_GENERIC_H 22 23#include <asm/addrspace.h> 24#include <asm/byteorder.h> 25#include <asm/mips-boards/bonito64.h> 26 27/* 28 * Display register base. 29 */ 30#define ASCII_DISPLAY_WORD_BASE 0x1f000410 31#define ASCII_DISPLAY_POS_BASE 0x1f000418 32#define LCD_DISPLAY_POS_BASE 0x1f000400 /* SEAD3 BOARDS */ 33 34 35/* 36 * Yamon Prom print address. 37 */ 38#define YAMON_PROM_PRINT_ADDR 0x1fc00504 39 40 41/* 42 * Reset register. 43 */ 44#define SOFTRES_REG 0x1f000500 45#define GORESET 0x42 46 47/* 48 * Revision register. 49 */ 50#define MIPS_REVISION_REG 0x1fc00010 51#define MIPS_REVISION_CORID_QED_RM5261 0 52#define MIPS_REVISION_CORID_CORE_LV 1 53#define MIPS_REVISION_CORID_BONITO64 2 54#define MIPS_REVISION_CORID_CORE_20K 3 55#define MIPS_REVISION_CORID_CORE_FPGA 4 56#define MIPS_REVISION_CORID_CORE_MSC 5 57#define MIPS_REVISION_CORID_CORE_EMUL 6 58#define MIPS_REVISION_CORID_CORE_FPGA2 7 59#define MIPS_REVISION_CORID_CORE_FPGAR2 8 60#define MIPS_REVISION_CORID_CORE_FPGA3 9 61#define MIPS_REVISION_CORID_CORE_24K 10 62#define MIPS_REVISION_CORID_CORE_FPGA4 11 63#define MIPS_REVISION_CORID_CORE_FPGA5 12 64 65/**** Artificial corid defines ****/ 66/* 67 * CoreEMUL with Bonito System Controller is treated like a Core20K 68 * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC 69 */ 70#define MIPS_REVISION_CORID_CORE_EMUL_BON -1 71#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 72 73#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) 74 75#define MIPS_REVISION_SCON_OTHER 0 76#define MIPS_REVISION_SCON_SOCITSC 1 77#define MIPS_REVISION_SCON_SOCITSCP 2 78 79/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ 80#define MIPS_REVISION_SCON_UNKNOWN -1 81#define MIPS_REVISION_SCON_GT64120 -2 82#define MIPS_REVISION_SCON_BONITO -3 83#define MIPS_REVISION_SCON_BRTL -4 84#define MIPS_REVISION_SCON_SOCIT -5 85#define MIPS_REVISION_SCON_ROCIT -6 86 87#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) 88 89extern int mips_revision_sconid; 90 91#ifdef CONFIG_PCI 92extern void mips_pcibios_init(void); 93#else 94#define mips_pcibios_init() do { } while (0) 95#endif 96 97#ifdef CONFIG_KGDB 98extern void kgdb_config(void); 99#endif 100 101#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 102