1/* 2 * AMD Alchemy Semi PB1550 Referrence Board 3 * Board Registers defines. 4 * 5 * Copyright 2004 Embedded Edge LLC. 6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org) 7 * 8 * ######################################################################## 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 22 * 23 * ######################################################################## 24 * 25 * 26 */ 27#ifndef __ASM_PB1550_H 28#define __ASM_PB1550_H 29 30#include <linux/types.h> 31#include <asm/mach-au1x00/au1xxx_psc.h> 32 33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 37 38#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define AC97_PSC_BASE PSC1_BASE_ADDR 40#define SMBUS_PSC_BASE PSC2_BASE_ADDR 41#define I2S_PSC_BASE PSC3_BASE_ADDR 42 43/* 44 * Timing values as described in databook, * ns value stripped of 45 * lower 2 bits. 46 * These defines are here rather than an SOC1550 generic file because 47 * the parts chosen on another board may be different and may require 48 * different timings. 49 */ 50#define NAND_T_H (18 >> 2) 51#define NAND_T_PUL (30 >> 2) 52#define NAND_T_SU (30 >> 2) 53#define NAND_T_WH (30 >> 2) 54 55/* Bitfield shift amounts */ 56#define NAND_T_H_SHIFT 0 57#define NAND_T_PUL_SHIFT 4 58#define NAND_T_SU_SHIFT 8 59#define NAND_T_WH_SHIFT 12 60 61#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 62 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 63 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 64 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) 65 66#define NAND_CS 1 67 68/* Should be done by YAMON */ 69#define NAND_STCFG 0x00400005 /* 8-bit NAND */ 70#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */ 71#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ 72 73#endif /* __ASM_PB1550_H */ 74