1/* 2 * AMD Alchemy DBAu1x00 Reference Boards 3 * 4 * Copyright 2001, 2008 MontaVista Software Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com> 6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 7 * 8 * ######################################################################## 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 22 * 23 * ######################################################################## 24 * 25 * 26 */ 27#ifndef __ASM_DB1X00_H 28#define __ASM_DB1X00_H 29 30#include <asm/mach-au1x00/au1xxx_psc.h> 31 32#ifdef CONFIG_MIPS_DB1550 33 34#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 35#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 36#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 37#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 38 39#define SPI_PSC_BASE PSC0_BASE_ADDR 40#define AC97_PSC_BASE PSC1_BASE_ADDR 41#define SMBUS_PSC_BASE PSC2_BASE_ADDR 42#define I2S_PSC_BASE PSC3_BASE_ADDR 43 44#define NAND_PHYS_ADDR 0x20000000 45 46#endif 47 48/* 49 * NAND defines 50 * 51 * Timing values as described in databook, * ns value stripped of the 52 * lower 2 bits. 53 * These defines are here rather than an Au1550 generic file because 54 * the parts chosen on another board may be different and may require 55 * different timings. 56 */ 57#define NAND_T_H (18 >> 2) 58#define NAND_T_PUL (30 >> 2) 59#define NAND_T_SU (30 >> 2) 60#define NAND_T_WH (30 >> 2) 61 62/* Bitfield shift amounts */ 63#define NAND_T_H_SHIFT 0 64#define NAND_T_PUL_SHIFT 4 65#define NAND_T_SU_SHIFT 8 66#define NAND_T_WH_SHIFT 12 67 68#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 69 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 70 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 71 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)) 72#define NAND_CS 1 73 74/* Should be done by YAMON */ 75#define NAND_STCFG 0x00400005 /* 8-bit NAND */ 76#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */ 77#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ 78 79#endif /* __ASM_DB1X00_H */ 80