1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org> 7 * Copyright (C) MIPS Technologies, Inc. 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 */ 10#ifndef _ASM_HAZARDS_H 11#define _ASM_HAZARDS_H 12 13#ifdef __ASSEMBLY__ 14#define ASMMACRO(name, code...) .macro name; code; .endm 15#else 16 17#include <asm/cpu-features.h> 18 19#define ASMMACRO(name, code...) \ 20__asm__(".macro " #name "; " #code "; .endm"); \ 21 \ 22static inline void name(void) \ 23{ \ 24 __asm__ __volatile__ (#name); \ 25} 26 27/* 28 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. 29 */ 30extern void mips_ihb(void); 31 32#endif 33 34ASMMACRO(_ssnop, 35 sll $0, $0, 1 36 ) 37 38ASMMACRO(_ehb, 39 sll $0, $0, 3 40 ) 41 42/* 43 * TLB hazards 44 */ 45#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON) 46 47/* 48 * MIPSR2 defines ehb for hazard avoidance 49 */ 50 51ASMMACRO(mtc0_tlbw_hazard, 52 _ehb 53 ) 54ASMMACRO(tlbw_use_hazard, 55 _ehb 56 ) 57ASMMACRO(tlb_probe_hazard, 58 _ehb 59 ) 60ASMMACRO(irq_enable_hazard, 61 _ehb 62 ) 63ASMMACRO(irq_disable_hazard, 64 _ehb 65 ) 66ASMMACRO(back_to_back_c0_hazard, 67 _ehb 68 ) 69/* 70 * gcc has a tradition of misscompiling the previous construct using the 71 * address of a label as argument to inline assembler. Gas otoh has the 72 * annoying difference between la and dla which are only usable for 32-bit 73 * rsp. 64-bit code, so can't be used without conditional compilation. 74 * The alterantive is switching the assembler to 64-bit code which happens 75 * to work right even for 32-bit code ... 76 */ 77#define instruction_hazard() \ 78do { \ 79 unsigned long tmp; \ 80 \ 81 __asm__ __volatile__( \ 82 " .set mips64r2 \n" \ 83 " dla %0, 1f \n" \ 84 " jr.hb %0 \n" \ 85 " .set mips0 \n" \ 86 "1: \n" \ 87 : "=r" (tmp)); \ 88} while (0) 89 90#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY) 91 92/* 93 * These are slightly complicated by the fact that we guarantee R1 kernels to 94 * run fine on R2 processors. 95 */ 96ASMMACRO(mtc0_tlbw_hazard, 97 _ssnop; _ssnop; _ehb 98 ) 99ASMMACRO(tlbw_use_hazard, 100 _ssnop; _ssnop; _ssnop; _ehb 101 ) 102ASMMACRO(tlb_probe_hazard, 103 _ssnop; _ssnop; _ssnop; _ehb 104 ) 105ASMMACRO(irq_enable_hazard, 106 _ssnop; _ssnop; _ssnop; _ehb 107 ) 108ASMMACRO(irq_disable_hazard, 109 _ssnop; _ssnop; _ssnop; _ehb 110 ) 111ASMMACRO(back_to_back_c0_hazard, 112 _ssnop; _ssnop; _ssnop; _ehb 113 ) 114/* 115 * gcc has a tradition of misscompiling the previous construct using the 116 * address of a label as argument to inline assembler. Gas otoh has the 117 * annoying difference between la and dla which are only usable for 32-bit 118 * rsp. 64-bit code, so can't be used without conditional compilation. 119 * The alterantive is switching the assembler to 64-bit code which happens 120 * to work right even for 32-bit code ... 121 */ 122#define __instruction_hazard() \ 123do { \ 124 unsigned long tmp; \ 125 \ 126 __asm__ __volatile__( \ 127 " .set mips64r2 \n" \ 128 " dla %0, 1f \n" \ 129 " jr.hb %0 \n" \ 130 " .set mips0 \n" \ 131 "1: \n" \ 132 : "=r" (tmp)); \ 133} while (0) 134 135#define instruction_hazard() \ 136do { \ 137 if (cpu_has_mips_r2) \ 138 __instruction_hazard(); \ 139} while (0) 140 141#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 142 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ 143 defined(CONFIG_CPU_R5500) 144 145/* 146 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 147 */ 148 149ASMMACRO(mtc0_tlbw_hazard, 150 ) 151ASMMACRO(tlbw_use_hazard, 152 ) 153ASMMACRO(tlb_probe_hazard, 154 ) 155ASMMACRO(irq_enable_hazard, 156 ) 157ASMMACRO(irq_disable_hazard, 158 ) 159ASMMACRO(back_to_back_c0_hazard, 160 ) 161#define instruction_hazard() do { } while (0) 162 163#elif defined(CONFIG_CPU_RM9000) 164 165/* 166 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent 167 * use of the JTLB for instructions should not occur for 4 cpu cycles and use 168 * for data translations should not occur for 3 cpu cycles. 169 */ 170 171ASMMACRO(mtc0_tlbw_hazard, 172 _ssnop; _ssnop; _ssnop; _ssnop 173 ) 174ASMMACRO(tlbw_use_hazard, 175 _ssnop; _ssnop; _ssnop; _ssnop 176 ) 177ASMMACRO(tlb_probe_hazard, 178 _ssnop; _ssnop; _ssnop; _ssnop 179 ) 180ASMMACRO(irq_enable_hazard, 181 ) 182ASMMACRO(irq_disable_hazard, 183 ) 184ASMMACRO(back_to_back_c0_hazard, 185 ) 186#define instruction_hazard() do { } while (0) 187 188#elif defined(CONFIG_CPU_SB1) 189 190/* 191 * Mostly like R4000 for historic reasons 192 */ 193ASMMACRO(mtc0_tlbw_hazard, 194 ) 195ASMMACRO(tlbw_use_hazard, 196 ) 197ASMMACRO(tlb_probe_hazard, 198 ) 199ASMMACRO(irq_enable_hazard, 200 ) 201ASMMACRO(irq_disable_hazard, 202 _ssnop; _ssnop; _ssnop 203 ) 204ASMMACRO(back_to_back_c0_hazard, 205 ) 206#define instruction_hazard() do { } while (0) 207 208#else 209 210/* 211 * Finally the catchall case for all other processors including R4000, R4400, 212 * R4600, R4700, R5000, RM7000, NEC VR41xx etc. 213 * 214 * The taken branch will result in a two cycle penalty for the two killed 215 * instructions on R4000 / R4400. Other processors only have a single cycle 216 * hazard so this is nice trick to have an optimal code for a range of 217 * processors. 218 */ 219ASMMACRO(mtc0_tlbw_hazard, 220 nop; nop 221 ) 222ASMMACRO(tlbw_use_hazard, 223 nop; nop; nop 224 ) 225ASMMACRO(tlb_probe_hazard, 226 nop; nop; nop 227 ) 228ASMMACRO(irq_enable_hazard, 229 _ssnop; _ssnop; _ssnop; 230 ) 231ASMMACRO(irq_disable_hazard, 232 nop; nop; nop 233 ) 234ASMMACRO(back_to_back_c0_hazard, 235 _ssnop; _ssnop; _ssnop; 236 ) 237#define instruction_hazard() do { } while (0) 238 239#endif 240 241 242/* FPU hazards */ 243 244#if defined(CONFIG_CPU_SB1) 245ASMMACRO(enable_fpu_hazard, 246 .set push; 247 .set mips64; 248 .set noreorder; 249 _ssnop; 250 bnezl $0, .+4; 251 _ssnop; 252 .set pop 253) 254ASMMACRO(disable_fpu_hazard, 255) 256 257#elif defined(CONFIG_CPU_MIPSR2) 258ASMMACRO(enable_fpu_hazard, 259 _ehb 260) 261ASMMACRO(disable_fpu_hazard, 262 _ehb 263) 264#else 265ASMMACRO(enable_fpu_hazard, 266 nop; nop; nop; nop 267) 268ASMMACRO(disable_fpu_hazard, 269 _ehb 270) 271#endif 272 273#endif /* _ASM_HAZARDS_H */ 274