1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9#ifndef __ASM_CPU_FEATURES_H 10#define __ASM_CPU_FEATURES_H 11 12#include <asm/cpu.h> 13#include <asm/cpu-info.h> 14#include <cpu-feature-overrides.h> 15 16#ifndef current_cpu_type 17#define current_cpu_type() current_cpu_data.cputype 18#endif 19 20/* 21 * SMP assumption: Options of CPU 0 are a superset of all processors. 22 * This is true for all known MIPS systems. 23 */ 24#ifndef cpu_has_tlb 25#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 26#endif 27#ifndef cpu_has_4kex 28#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 29#endif 30#ifndef cpu_has_3k_cache 31#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) 32#endif 33#define cpu_has_6k_cache 0 34#define cpu_has_8k_cache 0 35#ifndef cpu_has_4k_cache 36#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) 37#endif 38#ifndef cpu_has_tx39_cache 39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 40#endif 41#ifndef cpu_has_octeon_cache 42#define cpu_has_octeon_cache 0 43#endif 44#ifndef cpu_has_fpu 45#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 46#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 47#else 48#define raw_cpu_has_fpu cpu_has_fpu 49#endif 50#ifndef cpu_has_32fpr 51#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) 52#endif 53#ifndef cpu_has_counter 54#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) 55#endif 56#ifndef cpu_has_watch 57#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 58#endif 59#ifndef cpu_has_divec 60#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 61#endif 62#ifndef cpu_has_vce 63#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) 64#endif 65#ifndef cpu_has_cache_cdex_p 66#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) 67#endif 68#ifndef cpu_has_cache_cdex_s 69#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) 70#endif 71#ifndef cpu_has_prefetch 72#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) 73#endif 74#ifndef cpu_has_mcheck 75#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) 76#endif 77#ifndef cpu_has_ejtag 78#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) 79#endif 80#ifndef cpu_has_llsc 81#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 82#endif 83#ifndef kernel_uses_llsc 84#define kernel_uses_llsc cpu_has_llsc 85#endif 86#ifndef cpu_has_mmips 87#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 88#endif 89#ifndef cpu_has_mips16 90#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 91#endif 92#ifndef cpu_has_mdmx 93#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 94#endif 95#ifndef cpu_has_mips3d 96#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 97#endif 98#ifndef cpu_has_smartmips 99#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 100#endif 101#ifndef kernel_uses_smartmips_rixi 102#define kernel_uses_smartmips_rixi 0 103#endif 104#ifndef cpu_has_vtag_icache 105#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 106#endif 107#ifndef cpu_has_vtag_dcache 108#define cpu_has_vtag_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_VTAG) 109#endif 110#ifndef cpu_has_dc_aliases 111#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 112#endif 113#ifndef cpu_has_ic_fills_f_dc 114#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 115#endif 116#ifndef cpu_has_pindexed_dcache 117#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 118#endif 119 120/* Page Global Directory ptr comes from memory */ 121#ifndef cpu_has_pgdc_in_memory 122#if defined(CONFIG_SMP) && defined(CONFIG_MIPS_MT_SMTC) 123#define cpu_has_pgdc_in_memory (1) 124#else 125#define cpu_has_pgdc_in_memory (!(cpu_has_pgdc_in_context || cpu_has_pgdc_in_errorepc)) 126#endif 127#endif 128 129/* Page Global Directory ptr comes from Context 130 * 131 * SMP is supported when ErrorEPC is used to store smp_processor_id(). 132 * Uniprocessor is always supported 133 * 134 * SMTC is not supported as Context is per-VPE. 135 * - SMTC is excluded in Kconfig 136 * 137 */ 138#ifndef cpu_has_pgdc_in_context 139#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && \ 140 defined(CONFIG_MIPS_TLB_SMPID_ERROREPC)) 141#define cpu_has_pgdc_in_context (cpu_data[0].options & MIPS_CPU_PGDC_CC) 142#else 143#define cpu_has_pgdc_in_context (0) 144#endif 145#endif 146 147/* Page Global Directory ptr is stored in ErrorEPC 148 * - avoids load from memory to load page table base 149 * - on SMP, also avoids index from SMP ID in Context 150 */ 151#ifndef cpu_has_pgdc_in_errorepc 152#if defined(CONFIG_MIPS_TLB_PGD_ERROREPC) 153#define cpu_has_pgdc_in_errorepc (1) 154#else 155#define cpu_has_pgdc_in_errorepc (0) 156#endif 157#endif 158 159/* smp_processor_id() is stored in ErrorEPC 160 * - allows use of ContextConfig with SMP kernel 161 */ 162#ifndef cpu_has_smpid_in_errorepc 163#if defined(CONFIG_MIPS_TLB_SMPID_ERROREPC) 164#define cpu_has_smpid_in_errorepc (1) 165#else 166#define cpu_has_smpid_in_errorepc (0) 167#endif 168#endif 169 170/* 171 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 172 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 173 * don't. For maintaining I-cache coherency this means we need to flush the 174 * D-cache all the way back to whever the I-cache does refills from, so the 175 * I-cache has a chance to see the new data at all. Then we have to flush the 176 * I-cache also. 177 * Note we may have been rescheduled and may no longer be running on the CPU 178 * that did the store so we can't optimize this into only doing the flush on 179 * the local CPU. 180 */ 181#ifndef cpu_icache_snoops_remote_store 182#ifdef CONFIG_SMP 183#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 184#else 185#define cpu_icache_snoops_remote_store 1 186#endif 187#endif 188 189# ifndef cpu_has_mips32r1 190# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 191# endif 192# ifndef cpu_has_mips32r2 193# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 194# endif 195# ifndef cpu_has_mips64r1 196# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 197# endif 198# ifndef cpu_has_mips64r2 199# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 200# endif 201 202/* 203 * Shortcuts ... 204 */ 205#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) 206#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) 207#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 208#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 209#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 210 cpu_has_mips64r1 | cpu_has_mips64r2) 211 212#ifndef cpu_has_mips_r2_exec_hazard 213#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2 214#endif 215 216/* 217 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 218 * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 219 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 220 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 221 */ 222# ifndef cpu_has_clo_clz 223# define cpu_has_clo_clz cpu_has_mips_r 224# endif 225 226#ifndef cpu_has_dsp 227#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 228#endif 229 230#ifndef cpu_has_mipsmt 231#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 232#endif 233 234#ifndef cpu_has_userlocal 235#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) 236#endif 237 238#ifndef cpu_has_contextconfig 239#define cpu_has_contextconfig ((cpu_data[0].options & MIPS_CPU_CTXTC) || cpu_has_smartmips) 240#endif 241 242#ifdef CONFIG_32BIT 243# ifndef cpu_has_nofpuex 244# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 245# endif 246# ifndef cpu_has_64bits 247# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 248# endif 249# ifndef cpu_has_64bit_zero_reg 250# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 251# endif 252# ifndef cpu_has_64bit_gp_regs 253# define cpu_has_64bit_gp_regs 0 254# endif 255# ifndef cpu_has_64bit_addresses 256# define cpu_has_64bit_addresses 0 257# endif 258# ifndef cpu_vmbits 259# define cpu_vmbits 31 260# endif 261#endif 262 263#ifdef CONFIG_64BIT 264# ifndef cpu_has_nofpuex 265# define cpu_has_nofpuex 0 266# endif 267# ifndef cpu_has_64bits 268# define cpu_has_64bits 1 269# endif 270# ifndef cpu_has_64bit_zero_reg 271# define cpu_has_64bit_zero_reg 1 272# endif 273# ifndef cpu_has_64bit_gp_regs 274# define cpu_has_64bit_gp_regs 1 275# endif 276# ifndef cpu_has_64bit_addresses 277# define cpu_has_64bit_addresses 1 278# endif 279# ifndef cpu_vmbits 280# define cpu_vmbits cpu_data[0].vmbits 281# define __NEED_VMBITS_PROBE 282# endif 283#endif 284 285#if (defined(CONFIG_MIPS_SEAD3) || defined(CONFIG_CPU_MIPSR2_IRQ_VI)) && \ 286 !defined(cpu_has_vint) 287# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 288#elif !defined(cpu_has_vint) 289# define cpu_has_vint 0 290#endif 291 292#if (defined(CONFIG_MIPS_SEAD3) || defined(CONFIG_CPU_MIPSR2_IRQ_EI)) && \ 293 !defined(cpu_has_veic) 294# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 295#elif !defined(cpu_has_veic) 296# define cpu_has_veic 0 297#endif 298 299#ifndef cpu_has_inclusive_pcaches 300#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) 301#endif 302 303#ifndef cpu_dcache_line_size 304#define cpu_dcache_line_size() cpu_data[0].dcache.linesz 305#endif 306#ifndef cpu_icache_line_size 307#define cpu_icache_line_size() cpu_data[0].icache.linesz 308#endif 309#ifndef cpu_scache_line_size 310#define cpu_scache_line_size() cpu_data[0].scache.linesz 311#endif 312 313#ifndef cpu_hwrena_impl_bits 314#define cpu_hwrena_impl_bits 0 315#endif 316 317#endif /* __ASM_CPU_FEATURES_H */ 318