1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * Alchemy Db1x00 board setup. 5 * 6 * Copyright 2000, 2008 MontaVista Software Inc. 7 * Author: MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 */ 29 30#include <linux/gpio.h> 31#include <linux/init.h> 32#include <linux/interrupt.h> 33#include <linux/pm.h> 34 35#include <asm/mach-au1x00/au1000.h> 36#include <asm/mach-au1x00/au1xxx_eth.h> 37#include <asm/mach-db1x00/db1x00.h> 38#include <asm/mach-db1x00/bcsr.h> 39#include <asm/reboot.h> 40 41#include <prom.h> 42 43#ifdef CONFIG_MIPS_DB1500 44char irq_tab_alchemy[][5] __initdata = { 45 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */ 46 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ 47}; 48 49#endif 50 51 52#ifdef CONFIG_MIPS_DB1550 53char irq_tab_alchemy[][5] __initdata = { 54 [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */ 55 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */ 56 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */ 57}; 58#endif 59 60 61#ifdef CONFIG_MIPS_BOSPORUS 62char irq_tab_alchemy[][5] __initdata = { 63 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */ 64 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */ 65 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ 66}; 67 68/* 69 * Micrel/Kendin 5 port switch attached to MAC0, 70 * MAC0 is associated with PHY address 5 (== WAN port) 71 * MAC1 is not associated with any PHY, since it's connected directly 72 * to the switch. 73 * no interrupts are used 74 */ 75static struct au1000_eth_platform_data eth0_pdata = { 76 .phy_static_config = 1, 77 .phy_addr = 5, 78}; 79 80static void bosporus_power_off(void) 81{ 82 while (1) 83 asm volatile (".set mips3 ; wait ; .set mips0"); 84} 85 86const char *get_system_type(void) 87{ 88 return "Alchemy Bosporus Gateway Reference"; 89} 90#endif 91 92 93#ifdef CONFIG_MIPS_MIRAGE 94char irq_tab_alchemy[][5] __initdata = { 95 [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */ 96 [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */ 97 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */ 98}; 99 100static void mirage_power_off(void) 101{ 102 alchemy_gpio_direction_output(210, 1); 103} 104 105const char *get_system_type(void) 106{ 107 return "Alchemy Mirage"; 108} 109#endif 110 111 112#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) 113static void mips_softreset(void) 114{ 115 asm volatile ("jr\t%0" : : "r"(0xbfc00000)); 116} 117 118#else 119 120const char *get_system_type(void) 121{ 122 return "Alchemy Db1x00"; 123} 124#endif 125 126 127void __init board_setup(void) 128{ 129 unsigned long bcsr1, bcsr2; 130 131 bcsr1 = DB1000_BCSR_PHYS_ADDR; 132 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS; 133 134#ifdef CONFIG_MIPS_DB1000 135 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); 136#endif 137#ifdef CONFIG_MIPS_DB1500 138 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n"); 139#endif 140#ifdef CONFIG_MIPS_DB1100 141 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); 142#endif 143#ifdef CONFIG_MIPS_BOSPORUS 144 au1xxx_override_eth_cfg(0, ð0_pdata); 145 146 printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); 147#endif 148#ifdef CONFIG_MIPS_MIRAGE 149 printk(KERN_INFO "AMD Alchemy Mirage Board\n"); 150#endif 151#ifdef CONFIG_MIPS_DB1550 152 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n"); 153 154 bcsr1 = DB1550_BCSR_PHYS_ADDR; 155 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS; 156#endif 157 158 /* initialize board register space */ 159 bcsr_init(bcsr1, bcsr2); 160 161 /* Not valid for Au1550 */ 162#if defined(CONFIG_IRDA) && (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100)) 163 { 164 u32 pin_func; 165 166 /* Set IRFIRSEL instead of GPIO15 */ 167 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; 168 au_writel(pin_func, SYS_PINFUNC); 169 /* Power off until the driver is in use */ 170 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, 171 BCSR_RESETS_IRDA_MODE_OFF); 172 } 173#endif 174 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ 175 176 /* Enable GPIO[31:0] inputs */ 177 alchemy_gpio1_input_enable(); 178 179#ifdef CONFIG_MIPS_MIRAGE 180 { 181 u32 pin_func; 182 183 /* GPIO[20] is output */ 184 alchemy_gpio_direction_output(20, 0); 185 186 /* Set GPIO[210:208] instead of SSI_0 */ 187 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; 188 189 /* Set GPIO[215:211] for LEDs */ 190 pin_func |= 5 << 2; 191 192 /* Set GPIO[214:213] for more LEDs */ 193 pin_func |= 5 << 12; 194 195 /* Set GPIO[207:200] instead of PCMCIA/LCD */ 196 pin_func |= SYS_PF_LCD | SYS_PF_PC; 197 au_writel(pin_func, SYS_PINFUNC); 198 199 /* 200 * Enable speaker amplifier. This should 201 * be part of the audio driver. 202 */ 203 alchemy_gpio_direction_output(209, 1); 204 205 pm_power_off = mirage_power_off; 206 _machine_halt = mirage_power_off; 207 _machine_restart = (void(*)(char *))mips_softreset; 208 } 209#endif 210 211#ifdef CONFIG_MIPS_BOSPORUS 212 pm_power_off = bosporus_power_off; 213 _machine_halt = bosporus_power_off; 214 _machine_restart = (void(*)(char *))mips_softreset; 215#endif 216 au_sync(); 217} 218 219static int __init db1x00_init_irq(void) 220{ 221#if defined(CONFIG_MIPS_MIRAGE) 222 set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ 223#elif defined(CONFIG_MIPS_DB1550) 224 set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 225 set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ 226 set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 227 set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 228 set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 229 set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 230#elif defined(CONFIG_MIPS_DB1500) 231 set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 232 set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 233 set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 234 set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 235 set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 236 set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 237#elif defined(CONFIG_MIPS_DB1100) 238 set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 239 set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 240 set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 241 set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 242 set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 243 set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 244#elif defined(CONFIG_MIPS_DB1000) 245 set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 246 set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 247 set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 248 set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 249 set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 250 set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 251#endif 252 return 0; 253} 254arch_initcall(db1x00_init_irq); 255