1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * The Descriptor Based DMA channel manager that first appeared 5 * on the Au1550. I started with dma.c, but I think all that is 6 * left is this initial comment :-) 7 * 8 * Copyright 2004 Embedded Edge, LLC 9 * dan@embeddededge.com 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 */ 32 33#include <linux/init.h> 34#include <linux/kernel.h> 35#include <linux/slab.h> 36#include <linux/spinlock.h> 37#include <linux/interrupt.h> 38#include <linux/module.h> 39#include <linux/sysdev.h> 40#include <asm/mach-au1x00/au1000.h> 41#include <asm/mach-au1x00/au1xxx_dbdma.h> 42 43#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 44 45/* 46 * The Descriptor Based DMA supports up to 16 channels. 47 * 48 * There are 32 devices defined. We keep an internal structure 49 * of devices using these channels, along with additional 50 * information. 51 * 52 * We allocate the descriptors and allow access to them through various 53 * functions. The drivers allocate the data buffers and assign them 54 * to the descriptors. 55 */ 56static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); 57 58/* I couldn't find a macro that did this... */ 59#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) 60 61static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; 62static int dbdma_initialized; 63 64static dbdev_tab_t dbdev_tab[] = { 65#ifdef CONFIG_SOC_AU1550 66 /* UARTS */ 67 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, 68 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, 69 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, 70 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, 71 72 /* EXT DMA */ 73 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, 74 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, 75 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, 76 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, 77 78 /* USB DEV */ 79 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, 80 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, 81 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, 82 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, 83 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, 84 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, 85 86 /* PSC 0 */ 87 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, 88 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, 89 90 /* PSC 1 */ 91 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, 92 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, 93 94 /* PSC 2 */ 95 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, 96 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, 97 98 /* PSC 3 */ 99 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 }, 100 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 }, 101 102 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */ 103 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */ 104 105 /* MAC 0 */ 106 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 107 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 108 109 /* MAC 1 */ 110 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 111 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, 112 113#endif /* CONFIG_SOC_AU1550 */ 114 115#ifdef CONFIG_SOC_AU1200 116 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, 117 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, 118 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 }, 119 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 }, 120 121 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, 122 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, 123 124 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 125 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 126 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 127 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 128 129 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, 130 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, 131 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, 132 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, 133 134 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, 135 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, 136 137 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, 138 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, 139 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 140 141 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, 142 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, 143 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 144 145 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, 146 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, 147 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, 148 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 149 150 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, 151 152#endif /* CONFIG_SOC_AU1200 */ 153 154 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 155 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, 156 157 /* Provide 16 user definable device types */ 158 { ~0, 0, 0, 0, 0, 0, 0 }, 159 { ~0, 0, 0, 0, 0, 0, 0 }, 160 { ~0, 0, 0, 0, 0, 0, 0 }, 161 { ~0, 0, 0, 0, 0, 0, 0 }, 162 { ~0, 0, 0, 0, 0, 0, 0 }, 163 { ~0, 0, 0, 0, 0, 0, 0 }, 164 { ~0, 0, 0, 0, 0, 0, 0 }, 165 { ~0, 0, 0, 0, 0, 0, 0 }, 166 { ~0, 0, 0, 0, 0, 0, 0 }, 167 { ~0, 0, 0, 0, 0, 0, 0 }, 168 { ~0, 0, 0, 0, 0, 0, 0 }, 169 { ~0, 0, 0, 0, 0, 0, 0 }, 170 { ~0, 0, 0, 0, 0, 0, 0 }, 171 { ~0, 0, 0, 0, 0, 0, 0 }, 172 { ~0, 0, 0, 0, 0, 0, 0 }, 173 { ~0, 0, 0, 0, 0, 0, 0 }, 174}; 175 176#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) 177 178 179static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; 180 181static dbdev_tab_t *find_dbdev_id(u32 id) 182{ 183 int i; 184 dbdev_tab_t *p; 185 for (i = 0; i < DBDEV_TAB_SIZE; ++i) { 186 p = &dbdev_tab[i]; 187 if (p->dev_id == id) 188 return p; 189 } 190 return NULL; 191} 192 193void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp) 194{ 195 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 196} 197EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt); 198 199u32 au1xxx_ddma_add_device(dbdev_tab_t *dev) 200{ 201 u32 ret = 0; 202 dbdev_tab_t *p; 203 static u16 new_id = 0x1000; 204 205 p = find_dbdev_id(~0); 206 if (NULL != p) { 207 memcpy(p, dev, sizeof(dbdev_tab_t)); 208 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id); 209 ret = p->dev_id; 210 new_id++; 211 } 212 213 return ret; 214} 215EXPORT_SYMBOL(au1xxx_ddma_add_device); 216 217void au1xxx_ddma_del_device(u32 devid) 218{ 219 dbdev_tab_t *p = find_dbdev_id(devid); 220 221 if (p != NULL) { 222 memset(p, 0, sizeof(dbdev_tab_t)); 223 p->dev_id = ~0; 224 } 225} 226EXPORT_SYMBOL(au1xxx_ddma_del_device); 227 228/* Allocate a channel and return a non-zero descriptor if successful. */ 229u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, 230 void (*callback)(int, void *), void *callparam) 231{ 232 unsigned long flags; 233 u32 used, chan; 234 u32 dcp; 235 int i; 236 dbdev_tab_t *stp, *dtp; 237 chan_tab_t *ctp; 238 au1x_dma_chan_t *cp; 239 240 /* 241 * We do the intialization on the first channel allocation. 242 * We have to wait because of the interrupt handler initialization 243 * which can't be done successfully during board set up. 244 */ 245 if (!dbdma_initialized) 246 return 0; 247 248 stp = find_dbdev_id(srcid); 249 if (stp == NULL) 250 return 0; 251 dtp = find_dbdev_id(destid); 252 if (dtp == NULL) 253 return 0; 254 255 used = 0; 256 257 /* Check to see if we can get both channels. */ 258 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); 259 if (!(stp->dev_flags & DEV_FLAGS_INUSE) || 260 (stp->dev_flags & DEV_FLAGS_ANYUSE)) { 261 /* Got source */ 262 stp->dev_flags |= DEV_FLAGS_INUSE; 263 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) || 264 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) { 265 /* Got destination */ 266 dtp->dev_flags |= DEV_FLAGS_INUSE; 267 } else { 268 /* Can't get dest. Release src. */ 269 stp->dev_flags &= ~DEV_FLAGS_INUSE; 270 used++; 271 } 272 } else 273 used++; 274 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); 275 276 if (used) 277 return 0; 278 279 /* Let's see if we can allocate a channel for it. */ 280 ctp = NULL; 281 chan = 0; 282 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); 283 for (i = 0; i < NUM_DBDMA_CHANS; i++) 284 if (chan_tab_ptr[i] == NULL) { 285 /* 286 * If kmalloc fails, it is caught below same 287 * as a channel not available. 288 */ 289 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC); 290 chan_tab_ptr[i] = ctp; 291 break; 292 } 293 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); 294 295 if (ctp != NULL) { 296 memset(ctp, 0, sizeof(chan_tab_t)); 297 ctp->chan_index = chan = i; 298 dcp = DDMA_CHANNEL_BASE; 299 dcp += (0x0100 * chan); 300 ctp->chan_ptr = (au1x_dma_chan_t *)dcp; 301 cp = (au1x_dma_chan_t *)dcp; 302 ctp->chan_src = stp; 303 ctp->chan_dest = dtp; 304 ctp->chan_callback = callback; 305 ctp->chan_callparam = callparam; 306 307 /* Initialize channel configuration. */ 308 i = 0; 309 if (stp->dev_intlevel) 310 i |= DDMA_CFG_SED; 311 if (stp->dev_intpolarity) 312 i |= DDMA_CFG_SP; 313 if (dtp->dev_intlevel) 314 i |= DDMA_CFG_DED; 315 if (dtp->dev_intpolarity) 316 i |= DDMA_CFG_DP; 317 if ((stp->dev_flags & DEV_FLAGS_SYNC) || 318 (dtp->dev_flags & DEV_FLAGS_SYNC)) 319 i |= DDMA_CFG_SYNC; 320 cp->ddma_cfg = i; 321 au_sync(); 322 323 /* 324 * Return a non-zero value that can be used to find the channel 325 * information in subsequent operations. 326 */ 327 return (u32)(&chan_tab_ptr[chan]); 328 } 329 330 /* Release devices */ 331 stp->dev_flags &= ~DEV_FLAGS_INUSE; 332 dtp->dev_flags &= ~DEV_FLAGS_INUSE; 333 334 return 0; 335} 336EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); 337 338/* 339 * Set the device width if source or destination is a FIFO. 340 * Should be 8, 16, or 32 bits. 341 */ 342u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits) 343{ 344 u32 rv; 345 chan_tab_t *ctp; 346 dbdev_tab_t *stp, *dtp; 347 348 ctp = *((chan_tab_t **)chanid); 349 stp = ctp->chan_src; 350 dtp = ctp->chan_dest; 351 rv = 0; 352 353 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */ 354 rv = stp->dev_devwidth; 355 stp->dev_devwidth = bits; 356 } 357 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */ 358 rv = dtp->dev_devwidth; 359 dtp->dev_devwidth = bits; 360 } 361 362 return rv; 363} 364EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth); 365 366/* Allocate a descriptor ring, initializing as much as possible. */ 367u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries) 368{ 369 int i; 370 u32 desc_base, srcid, destid; 371 u32 cmd0, cmd1, src1, dest1; 372 u32 src0, dest0; 373 chan_tab_t *ctp; 374 dbdev_tab_t *stp, *dtp; 375 au1x_ddma_desc_t *dp; 376 377 /* 378 * I guess we could check this to be within the 379 * range of the table...... 380 */ 381 ctp = *((chan_tab_t **)chanid); 382 stp = ctp->chan_src; 383 dtp = ctp->chan_dest; 384 385 /* 386 * The descriptors must be 32-byte aligned. There is a 387 * possibility the allocation will give us such an address, 388 * and if we try that first we are likely to not waste larger 389 * slabs of memory. 390 */ 391 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), 392 GFP_KERNEL|GFP_DMA); 393 if (desc_base == 0) 394 return 0; 395 396 if (desc_base & 0x1f) { 397 /* 398 * Lost....do it again, allocate extra, and round 399 * the address base. 400 */ 401 kfree((const void *)desc_base); 402 i = entries * sizeof(au1x_ddma_desc_t); 403 i += (sizeof(au1x_ddma_desc_t) - 1); 404 desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA); 405 if (desc_base == 0) 406 return 0; 407 408 ctp->cdb_membase = desc_base; 409 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); 410 } else 411 ctp->cdb_membase = desc_base; 412 413 dp = (au1x_ddma_desc_t *)desc_base; 414 415 /* Keep track of the base descriptor. */ 416 ctp->chan_desc_base = dp; 417 418 /* Initialize the rings with as much information as we know. */ 419 srcid = stp->dev_id; 420 destid = dtp->dev_id; 421 422 cmd0 = cmd1 = src1 = dest1 = 0; 423 src0 = dest0 = 0; 424 425 cmd0 |= DSCR_CMD0_SID(srcid); 426 cmd0 |= DSCR_CMD0_DID(destid); 427 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV; 428 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE); 429 430 /* Is it mem to mem transfer? */ 431 if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || 432 (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) && 433 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || 434 (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) 435 cmd0 |= DSCR_CMD0_MEM; 436 437 switch (stp->dev_devwidth) { 438 case 8: 439 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE); 440 break; 441 case 16: 442 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD); 443 break; 444 case 32: 445 default: 446 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD); 447 break; 448 } 449 450 switch (dtp->dev_devwidth) { 451 case 8: 452 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE); 453 break; 454 case 16: 455 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD); 456 break; 457 case 32: 458 default: 459 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD); 460 break; 461 } 462 463 /* 464 * If the device is marked as an in/out FIFO, ensure it is 465 * set non-coherent. 466 */ 467 if (stp->dev_flags & DEV_FLAGS_IN) 468 cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */ 469 if (dtp->dev_flags & DEV_FLAGS_OUT) 470 cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */ 471 472 /* 473 * Set up source1. For now, assume no stride and increment. 474 * A channel attribute update can change this later. 475 */ 476 switch (stp->dev_tsize) { 477 case 1: 478 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1); 479 break; 480 case 2: 481 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2); 482 break; 483 case 4: 484 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4); 485 break; 486 case 8: 487 default: 488 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8); 489 break; 490 } 491 492 /* If source input is FIFO, set static address. */ 493 if (stp->dev_flags & DEV_FLAGS_IN) { 494 if (stp->dev_flags & DEV_FLAGS_BURSTABLE) 495 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); 496 else 497 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); 498 } 499 500 if (stp->dev_physaddr) 501 src0 = stp->dev_physaddr; 502 503 /* 504 * Set up dest1. For now, assume no stride and increment. 505 * A channel attribute update can change this later. 506 */ 507 switch (dtp->dev_tsize) { 508 case 1: 509 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1); 510 break; 511 case 2: 512 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2); 513 break; 514 case 4: 515 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4); 516 break; 517 case 8: 518 default: 519 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8); 520 break; 521 } 522 523 /* If destination output is FIFO, set static address. */ 524 if (dtp->dev_flags & DEV_FLAGS_OUT) { 525 if (dtp->dev_flags & DEV_FLAGS_BURSTABLE) 526 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST); 527 else 528 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); 529 } 530 531 if (dtp->dev_physaddr) 532 dest0 = dtp->dev_physaddr; 533 534 for (i = 0; i < entries; i++) { 535 dp->dscr_cmd0 = cmd0; 536 dp->dscr_cmd1 = cmd1; 537 dp->dscr_source0 = src0; 538 dp->dscr_source1 = src1; 539 dp->dscr_dest0 = dest0; 540 dp->dscr_dest1 = dest1; 541 dp->dscr_stat = 0; 542 dp->sw_context = 0; 543 dp->sw_status = 0; 544 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); 545 dp++; 546 } 547 548 /* Make last descrptor point to the first. */ 549 dp--; 550 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base)); 551 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; 552 553 return (u32)ctp->chan_desc_base; 554} 555EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc); 556 557/* 558 * Put a source buffer into the DMA ring. 559 * This updates the source pointer and byte count. Normally used 560 * for memory to fifo transfers. 561 */ 562u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) 563{ 564 chan_tab_t *ctp; 565 au1x_ddma_desc_t *dp; 566 567 /* 568 * I guess we could check this to be within the 569 * range of the table...... 570 */ 571 ctp = *(chan_tab_t **)chanid; 572 573 /* 574 * We should have multiple callers for a particular channel, 575 * an interrupt doesn't affect this pointer nor the descriptor, 576 * so no locking should be needed. 577 */ 578 dp = ctp->put_ptr; 579 580 /* 581 * If the descriptor is valid, we are way ahead of the DMA 582 * engine, so just return an error condition. 583 */ 584 if (dp->dscr_cmd0 & DSCR_CMD0_V) 585 return 0; 586 587 /* Load up buffer address and byte count. */ 588 dp->dscr_source0 = buf & ~0UL; 589 dp->dscr_cmd1 = nbytes; 590 /* Check flags */ 591 if (flags & DDMA_FLAGS_IE) 592 dp->dscr_cmd0 |= DSCR_CMD0_IE; 593 if (flags & DDMA_FLAGS_NOIE) 594 dp->dscr_cmd0 &= ~DSCR_CMD0_IE; 595 596 /* 597 * There is an errata on the Au1200/Au1550 parts that could result 598 * in "stale" data being DMA'ed. It has to do with the snoop logic on 599 * the cache eviction buffer. DMA_NONCOHERENT is on by default for 600 * these parts. If it is fixed in the future, these dma_cache_inv will 601 * just be nothing more than empty macros. See io.h. 602 */ 603 dma_cache_wback_inv((unsigned long)buf, nbytes); 604 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 605 au_sync(); 606 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); 607 ctp->chan_ptr->ddma_dbell = 0; 608 609 /* Get next descriptor pointer. */ 610 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 611 612 /* Return something non-zero. */ 613 return nbytes; 614} 615EXPORT_SYMBOL(au1xxx_dbdma_put_source); 616 617/* Put a destination buffer into the DMA ring. 618 * This updates the destination pointer and byte count. Normally used 619 * to place an empty buffer into the ring for fifo to memory transfers. 620 */ 621u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) 622{ 623 chan_tab_t *ctp; 624 au1x_ddma_desc_t *dp; 625 626 /* I guess we could check this to be within the 627 * range of the table...... 628 */ 629 ctp = *((chan_tab_t **)chanid); 630 631 /* We should have multiple callers for a particular channel, 632 * an interrupt doesn't affect this pointer nor the descriptor, 633 * so no locking should be needed. 634 */ 635 dp = ctp->put_ptr; 636 637 /* If the descriptor is valid, we are way ahead of the DMA 638 * engine, so just return an error condition. 639 */ 640 if (dp->dscr_cmd0 & DSCR_CMD0_V) 641 return 0; 642 643 /* Load up buffer address and byte count */ 644 645 /* Check flags */ 646 if (flags & DDMA_FLAGS_IE) 647 dp->dscr_cmd0 |= DSCR_CMD0_IE; 648 if (flags & DDMA_FLAGS_NOIE) 649 dp->dscr_cmd0 &= ~DSCR_CMD0_IE; 650 651 dp->dscr_dest0 = buf & ~0UL; 652 dp->dscr_cmd1 = nbytes; 653 /* 654 * There is an errata on the Au1200/Au1550 parts that could result in 655 * "stale" data being DMA'ed. It has to do with the snoop logic on the 656 * cache eviction buffer. DMA_NONCOHERENT is on by default for these 657 * parts. If it is fixed in the future, these dma_cache_inv will just 658 * be nothing more than empty macros. See io.h. 659 */ 660 dma_cache_inv((unsigned long)buf, nbytes); 661 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 662 au_sync(); 663 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); 664 ctp->chan_ptr->ddma_dbell = 0; 665 666 /* Get next descriptor pointer. */ 667 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 668 669 /* Return something non-zero. */ 670 return nbytes; 671} 672EXPORT_SYMBOL(au1xxx_dbdma_put_dest); 673 674/* 675 * Get a destination buffer into the DMA ring. 676 * Normally used to get a full buffer from the ring during fifo 677 * to memory transfers. This does not set the valid bit, you will 678 * have to put another destination buffer to keep the DMA going. 679 */ 680u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) 681{ 682 chan_tab_t *ctp; 683 au1x_ddma_desc_t *dp; 684 u32 rv; 685 686 /* 687 * I guess we could check this to be within the 688 * range of the table...... 689 */ 690 ctp = *((chan_tab_t **)chanid); 691 692 /* 693 * We should have multiple callers for a particular channel, 694 * an interrupt doesn't affect this pointer nor the descriptor, 695 * so no locking should be needed. 696 */ 697 dp = ctp->get_ptr; 698 699 /* 700 * If the descriptor is valid, we are way ahead of the DMA 701 * engine, so just return an error condition. 702 */ 703 if (dp->dscr_cmd0 & DSCR_CMD0_V) 704 return 0; 705 706 /* Return buffer address and byte count. */ 707 *buf = (void *)(phys_to_virt(dp->dscr_dest0)); 708 *nbytes = dp->dscr_cmd1; 709 rv = dp->dscr_stat; 710 711 /* Get next descriptor pointer. */ 712 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 713 714 /* Return something non-zero. */ 715 return rv; 716} 717EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest); 718 719void au1xxx_dbdma_stop(u32 chanid) 720{ 721 chan_tab_t *ctp; 722 au1x_dma_chan_t *cp; 723 int halt_timeout = 0; 724 725 ctp = *((chan_tab_t **)chanid); 726 727 cp = ctp->chan_ptr; 728 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */ 729 au_sync(); 730 while (!(cp->ddma_stat & DDMA_STAT_H)) { 731 udelay(1); 732 halt_timeout++; 733 if (halt_timeout > 100) { 734 printk(KERN_WARNING "warning: DMA channel won't halt\n"); 735 break; 736 } 737 } 738 /* clear current desc valid and doorbell */ 739 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); 740 au_sync(); 741} 742EXPORT_SYMBOL(au1xxx_dbdma_stop); 743 744/* 745 * Start using the current descriptor pointer. If the DBDMA encounters 746 * a non-valid descriptor, it will stop. In this case, we can just 747 * continue by adding a buffer to the list and starting again. 748 */ 749void au1xxx_dbdma_start(u32 chanid) 750{ 751 chan_tab_t *ctp; 752 au1x_dma_chan_t *cp; 753 754 ctp = *((chan_tab_t **)chanid); 755 cp = ctp->chan_ptr; 756 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); 757 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ 758 au_sync(); 759 cp->ddma_dbell = 0; 760 au_sync(); 761} 762EXPORT_SYMBOL(au1xxx_dbdma_start); 763 764void au1xxx_dbdma_reset(u32 chanid) 765{ 766 chan_tab_t *ctp; 767 au1x_ddma_desc_t *dp; 768 769 au1xxx_dbdma_stop(chanid); 770 771 ctp = *((chan_tab_t **)chanid); 772 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; 773 774 /* Run through the descriptors and reset the valid indicator. */ 775 dp = ctp->chan_desc_base; 776 777 do { 778 dp->dscr_cmd0 &= ~DSCR_CMD0_V; 779 /* 780 * Reset our software status -- this is used to determine 781 * if a descriptor is in use by upper level software. Since 782 * posting can reset 'V' bit. 783 */ 784 dp->sw_status = 0; 785 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 786 } while (dp != ctp->chan_desc_base); 787} 788EXPORT_SYMBOL(au1xxx_dbdma_reset); 789 790u32 au1xxx_get_dma_residue(u32 chanid) 791{ 792 chan_tab_t *ctp; 793 au1x_dma_chan_t *cp; 794 u32 rv; 795 796 ctp = *((chan_tab_t **)chanid); 797 cp = ctp->chan_ptr; 798 799 /* This is only valid if the channel is stopped. */ 800 rv = cp->ddma_bytecnt; 801 au_sync(); 802 803 return rv; 804} 805EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue); 806 807void au1xxx_dbdma_chan_free(u32 chanid) 808{ 809 chan_tab_t *ctp; 810 dbdev_tab_t *stp, *dtp; 811 812 ctp = *((chan_tab_t **)chanid); 813 stp = ctp->chan_src; 814 dtp = ctp->chan_dest; 815 816 au1xxx_dbdma_stop(chanid); 817 818 kfree((void *)ctp->cdb_membase); 819 820 stp->dev_flags &= ~DEV_FLAGS_INUSE; 821 dtp->dev_flags &= ~DEV_FLAGS_INUSE; 822 chan_tab_ptr[ctp->chan_index] = NULL; 823 824 kfree(ctp); 825} 826EXPORT_SYMBOL(au1xxx_dbdma_chan_free); 827 828static irqreturn_t dbdma_interrupt(int irq, void *dev_id) 829{ 830 u32 intstat; 831 u32 chan_index; 832 chan_tab_t *ctp; 833 au1x_ddma_desc_t *dp; 834 au1x_dma_chan_t *cp; 835 836 intstat = dbdma_gptr->ddma_intstat; 837 au_sync(); 838 chan_index = __ffs(intstat); 839 840 ctp = chan_tab_ptr[chan_index]; 841 cp = ctp->chan_ptr; 842 dp = ctp->cur_ptr; 843 844 /* Reset interrupt. */ 845 cp->ddma_irq = 0; 846 au_sync(); 847 848 if (ctp->chan_callback) 849 ctp->chan_callback(irq, ctp->chan_callparam); 850 851 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 852 return IRQ_RETVAL(1); 853} 854 855void au1xxx_dbdma_dump(u32 chanid) 856{ 857 chan_tab_t *ctp; 858 au1x_ddma_desc_t *dp; 859 dbdev_tab_t *stp, *dtp; 860 au1x_dma_chan_t *cp; 861 u32 i = 0; 862 863 ctp = *((chan_tab_t **)chanid); 864 stp = ctp->chan_src; 865 dtp = ctp->chan_dest; 866 cp = ctp->chan_ptr; 867 868 printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d)\n", 869 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, 870 dtp - dbdev_tab); 871 printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n", 872 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr), 873 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr)); 874 875 printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp); 876 printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n", 877 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr); 878 printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n", 879 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, 880 cp->ddma_bytecnt); 881 882 /* Run through the descriptors */ 883 dp = ctp->chan_desc_base; 884 885 do { 886 printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n", 887 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); 888 printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n", 889 dp->dscr_source0, dp->dscr_source1, 890 dp->dscr_dest0, dp->dscr_dest1); 891 printk(KERN_DEBUG "stat %08x, nxtptr %08x\n", 892 dp->dscr_stat, dp->dscr_nxtptr); 893 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 894 } while (dp != ctp->chan_desc_base); 895} 896 897/* Put a descriptor into the DMA ring. 898 * This updates the source/destination pointers and byte count. 899 */ 900u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) 901{ 902 chan_tab_t *ctp; 903 au1x_ddma_desc_t *dp; 904 u32 nbytes = 0; 905 906 /* 907 * I guess we could check this to be within the 908 * range of the table...... 909 */ 910 ctp = *((chan_tab_t **)chanid); 911 912 /* 913 * We should have multiple callers for a particular channel, 914 * an interrupt doesn't affect this pointer nor the descriptor, 915 * so no locking should be needed. 916 */ 917 dp = ctp->put_ptr; 918 919 /* 920 * If the descriptor is valid, we are way ahead of the DMA 921 * engine, so just return an error condition. 922 */ 923 if (dp->dscr_cmd0 & DSCR_CMD0_V) 924 return 0; 925 926 /* Load up buffer addresses and byte count. */ 927 dp->dscr_dest0 = dscr->dscr_dest0; 928 dp->dscr_source0 = dscr->dscr_source0; 929 dp->dscr_dest1 = dscr->dscr_dest1; 930 dp->dscr_source1 = dscr->dscr_source1; 931 dp->dscr_cmd1 = dscr->dscr_cmd1; 932 nbytes = dscr->dscr_cmd1; 933 /* Allow the caller to specifiy if an interrupt is generated */ 934 dp->dscr_cmd0 &= ~DSCR_CMD0_IE; 935 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; 936 ctp->chan_ptr->ddma_dbell = 0; 937 938 /* Get next descriptor pointer. */ 939 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 940 941 /* Return something non-zero. */ 942 return nbytes; 943} 944 945 946struct alchemy_dbdma_sysdev { 947 struct sys_device sysdev; 948 u32 pm_regs[NUM_DBDMA_CHANS + 1][6]; 949}; 950 951static int alchemy_dbdma_suspend(struct sys_device *dev, 952 pm_message_t state) 953{ 954 struct alchemy_dbdma_sysdev *sdev = 955 container_of(dev, struct alchemy_dbdma_sysdev, sysdev); 956 int i; 957 u32 addr; 958 959 addr = DDMA_GLOBAL_BASE; 960 sdev->pm_regs[0][0] = au_readl(addr + 0x00); 961 sdev->pm_regs[0][1] = au_readl(addr + 0x04); 962 sdev->pm_regs[0][2] = au_readl(addr + 0x08); 963 sdev->pm_regs[0][3] = au_readl(addr + 0x0c); 964 965 /* save channel configurations */ 966 for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { 967 sdev->pm_regs[i][0] = au_readl(addr + 0x00); 968 sdev->pm_regs[i][1] = au_readl(addr + 0x04); 969 sdev->pm_regs[i][2] = au_readl(addr + 0x08); 970 sdev->pm_regs[i][3] = au_readl(addr + 0x0c); 971 sdev->pm_regs[i][4] = au_readl(addr + 0x10); 972 sdev->pm_regs[i][5] = au_readl(addr + 0x14); 973 974 /* halt channel */ 975 au_writel(sdev->pm_regs[i][0] & ~1, addr + 0x00); 976 au_sync(); 977 while (!(au_readl(addr + 0x14) & 1)) 978 au_sync(); 979 980 addr += 0x100; /* next channel base */ 981 } 982 /* disable channel interrupts */ 983 au_writel(0, DDMA_GLOBAL_BASE + 0x0c); 984 au_sync(); 985 986 return 0; 987} 988 989static int alchemy_dbdma_resume(struct sys_device *dev) 990{ 991 struct alchemy_dbdma_sysdev *sdev = 992 container_of(dev, struct alchemy_dbdma_sysdev, sysdev); 993 int i; 994 u32 addr; 995 996 addr = DDMA_GLOBAL_BASE; 997 au_writel(sdev->pm_regs[0][0], addr + 0x00); 998 au_writel(sdev->pm_regs[0][1], addr + 0x04); 999 au_writel(sdev->pm_regs[0][2], addr + 0x08); 1000 au_writel(sdev->pm_regs[0][3], addr + 0x0c); 1001 1002 /* restore channel configurations */ 1003 for (i = 1, addr = DDMA_CHANNEL_BASE; i <= NUM_DBDMA_CHANS; i++) { 1004 au_writel(sdev->pm_regs[i][0], addr + 0x00); 1005 au_writel(sdev->pm_regs[i][1], addr + 0x04); 1006 au_writel(sdev->pm_regs[i][2], addr + 0x08); 1007 au_writel(sdev->pm_regs[i][3], addr + 0x0c); 1008 au_writel(sdev->pm_regs[i][4], addr + 0x10); 1009 au_writel(sdev->pm_regs[i][5], addr + 0x14); 1010 au_sync(); 1011 addr += 0x100; /* next channel base */ 1012 } 1013 1014 return 0; 1015} 1016 1017static struct sysdev_class alchemy_dbdma_sysdev_class = { 1018 .name = "dbdma", 1019 .suspend = alchemy_dbdma_suspend, 1020 .resume = alchemy_dbdma_resume, 1021}; 1022 1023static int __init alchemy_dbdma_sysdev_init(void) 1024{ 1025 struct alchemy_dbdma_sysdev *sdev; 1026 int ret; 1027 1028 ret = sysdev_class_register(&alchemy_dbdma_sysdev_class); 1029 if (ret) 1030 return ret; 1031 1032 sdev = kzalloc(sizeof(struct alchemy_dbdma_sysdev), GFP_KERNEL); 1033 if (!sdev) 1034 return -ENOMEM; 1035 1036 sdev->sysdev.id = -1; 1037 sdev->sysdev.cls = &alchemy_dbdma_sysdev_class; 1038 ret = sysdev_register(&sdev->sysdev); 1039 if (ret) 1040 kfree(sdev); 1041 1042 return ret; 1043} 1044 1045static int __init au1xxx_dbdma_init(void) 1046{ 1047 int irq_nr, ret; 1048 1049 dbdma_gptr->ddma_config = 0; 1050 dbdma_gptr->ddma_throttle = 0; 1051 dbdma_gptr->ddma_inten = 0xffff; 1052 au_sync(); 1053 1054 switch (alchemy_get_cputype()) { 1055 case ALCHEMY_CPU_AU1550: 1056 irq_nr = AU1550_DDMA_INT; 1057 break; 1058 case ALCHEMY_CPU_AU1200: 1059 irq_nr = AU1200_DDMA_INT; 1060 break; 1061 default: 1062 return -ENODEV; 1063 } 1064 1065 ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, 1066 "Au1xxx dbdma", (void *)dbdma_gptr); 1067 if (ret) 1068 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); 1069 else { 1070 dbdma_initialized = 1; 1071 printk(KERN_INFO "Alchemy DBDMA initialized\n"); 1072 ret = alchemy_dbdma_sysdev_init(); 1073 if (ret) { 1074 printk(KERN_ERR "DBDMA PM init failed\n"); 1075 ret = 0; 1076 } 1077 } 1078 1079 return ret; 1080} 1081subsys_initcall(au1xxx_dbdma_init); 1082 1083#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ 1084