1/* 2 * Device Tree Generator version: 1.1 3 * 4 * (C) Copyright 2007-2008 Xilinx, Inc. 5 * (C) Copyright 2007-2009 Michal Simek 6 * 7 * Michal SIMEK <monstr@monstr.eu> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 * 24 * CAUTION: This file is automatically generated by libgen. 25 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6 26 * 27 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101 28 */ 29 30/dts-v1/; 31/ { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 compatible = "xlnx,microblaze"; 35 hard-reset-gpios = <&LEDs_8Bit 2 1>; 36 model = "testing"; 37 DDR2_SDRAM: memory@90000000 { 38 device_type = "memory"; 39 reg = < 0x90000000 0x10000000 >; 40 } ; 41 aliases { 42 ethernet0 = &Hard_Ethernet_MAC; 43 serial0 = &RS232_Uart_1; 44 } ; 45 chosen { 46 bootargs = "console=ttyUL0,115200 highres=on"; 47 linux,stdout-path = "/plb@0/serial@84000000"; 48 } ; 49 cpus { 50 #address-cells = <1>; 51 #cpus = <0x1>; 52 #size-cells = <0>; 53 microblaze_0: cpu@0 { 54 clock-frequency = <125000000>; 55 compatible = "xlnx,microblaze-7.10.d"; 56 d-cache-baseaddr = <0x90000000>; 57 d-cache-highaddr = <0x9fffffff>; 58 d-cache-line-size = <0x10>; 59 d-cache-size = <0x2000>; 60 device_type = "cpu"; 61 i-cache-baseaddr = <0x90000000>; 62 i-cache-highaddr = <0x9fffffff>; 63 i-cache-line-size = <0x10>; 64 i-cache-size = <0x2000>; 65 model = "microblaze,7.10.d"; 66 reg = <0>; 67 timebase-frequency = <125000000>; 68 xlnx,addr-tag-bits = <0xf>; 69 xlnx,allow-dcache-wr = <0x1>; 70 xlnx,allow-icache-wr = <0x1>; 71 xlnx,area-optimized = <0x0>; 72 xlnx,cache-byte-size = <0x2000>; 73 xlnx,d-lmb = <0x1>; 74 xlnx,d-opb = <0x0>; 75 xlnx,d-plb = <0x1>; 76 xlnx,data-size = <0x20>; 77 xlnx,dcache-addr-tag = <0xf>; 78 xlnx,dcache-always-used = <0x1>; 79 xlnx,dcache-byte-size = <0x2000>; 80 xlnx,dcache-line-len = <0x4>; 81 xlnx,dcache-use-fsl = <0x1>; 82 xlnx,debug-enabled = <0x1>; 83 xlnx,div-zero-exception = <0x1>; 84 xlnx,dopb-bus-exception = <0x0>; 85 xlnx,dynamic-bus-sizing = <0x1>; 86 xlnx,edge-is-positive = <0x1>; 87 xlnx,family = "virtex5"; 88 xlnx,fpu-exception = <0x1>; 89 xlnx,fsl-data-size = <0x20>; 90 xlnx,fsl-exception = <0x0>; 91 xlnx,fsl-links = <0x0>; 92 xlnx,i-lmb = <0x1>; 93 xlnx,i-opb = <0x0>; 94 xlnx,i-plb = <0x1>; 95 xlnx,icache-always-used = <0x1>; 96 xlnx,icache-line-len = <0x4>; 97 xlnx,icache-use-fsl = <0x1>; 98 xlnx,ill-opcode-exception = <0x1>; 99 xlnx,instance = "microblaze_0"; 100 xlnx,interconnect = <0x1>; 101 xlnx,interrupt-is-edge = <0x0>; 102 xlnx,iopb-bus-exception = <0x0>; 103 xlnx,mmu-dtlb-size = <0x4>; 104 xlnx,mmu-itlb-size = <0x2>; 105 xlnx,mmu-tlb-access = <0x3>; 106 xlnx,mmu-zones = <0x10>; 107 xlnx,number-of-pc-brk = <0x1>; 108 xlnx,number-of-rd-addr-brk = <0x0>; 109 xlnx,number-of-wr-addr-brk = <0x0>; 110 xlnx,opcode-0x0-illegal = <0x1>; 111 xlnx,pvr = <0x2>; 112 xlnx,pvr-user1 = <0x0>; 113 xlnx,pvr-user2 = <0x0>; 114 xlnx,reset-msr = <0x0>; 115 xlnx,sco = <0x0>; 116 xlnx,unaligned-exceptions = <0x1>; 117 xlnx,use-barrel = <0x1>; 118 xlnx,use-dcache = <0x1>; 119 xlnx,use-div = <0x1>; 120 xlnx,use-ext-brk = <0x1>; 121 xlnx,use-ext-nm-brk = <0x1>; 122 xlnx,use-extended-fsl-instr = <0x0>; 123 xlnx,use-fpu = <0x2>; 124 xlnx,use-hw-mul = <0x2>; 125 xlnx,use-icache = <0x1>; 126 xlnx,use-interrupt = <0x1>; 127 xlnx,use-mmu = <0x3>; 128 xlnx,use-msr-instr = <0x1>; 129 xlnx,use-pcmp-instr = <0x1>; 130 } ; 131 } ; 132 mb_plb: plb@0 { 133 #address-cells = <1>; 134 #size-cells = <1>; 135 compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus"; 136 ranges ; 137 FLASH: flash@a0000000 { 138 bank-width = <2>; 139 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; 140 reg = < 0xa0000000 0x2000000 >; 141 xlnx,family = "virtex5"; 142 xlnx,include-datawidth-matching-0 = <0x1>; 143 xlnx,include-datawidth-matching-1 = <0x0>; 144 xlnx,include-datawidth-matching-2 = <0x0>; 145 xlnx,include-datawidth-matching-3 = <0x0>; 146 xlnx,include-negedge-ioregs = <0x0>; 147 xlnx,include-plb-ipif = <0x1>; 148 xlnx,include-wrbuf = <0x1>; 149 xlnx,max-mem-width = <0x10>; 150 xlnx,mch-native-dwidth = <0x20>; 151 xlnx,mch-plb-clk-period-ps = <0x1f40>; 152 xlnx,mch-splb-awidth = <0x20>; 153 xlnx,mch0-accessbuf-depth = <0x10>; 154 xlnx,mch0-protocol = <0x0>; 155 xlnx,mch0-rddatabuf-depth = <0x10>; 156 xlnx,mch1-accessbuf-depth = <0x10>; 157 xlnx,mch1-protocol = <0x0>; 158 xlnx,mch1-rddatabuf-depth = <0x10>; 159 xlnx,mch2-accessbuf-depth = <0x10>; 160 xlnx,mch2-protocol = <0x0>; 161 xlnx,mch2-rddatabuf-depth = <0x10>; 162 xlnx,mch3-accessbuf-depth = <0x10>; 163 xlnx,mch3-protocol = <0x0>; 164 xlnx,mch3-rddatabuf-depth = <0x10>; 165 xlnx,mem0-width = <0x10>; 166 xlnx,mem1-width = <0x20>; 167 xlnx,mem2-width = <0x20>; 168 xlnx,mem3-width = <0x20>; 169 xlnx,num-banks-mem = <0x1>; 170 xlnx,num-channels = <0x0>; 171 xlnx,priority-mode = <0x0>; 172 xlnx,synch-mem-0 = <0x0>; 173 xlnx,synch-mem-1 = <0x0>; 174 xlnx,synch-mem-2 = <0x0>; 175 xlnx,synch-mem-3 = <0x0>; 176 xlnx,synch-pipedelay-0 = <0x2>; 177 xlnx,synch-pipedelay-1 = <0x2>; 178 xlnx,synch-pipedelay-2 = <0x2>; 179 xlnx,synch-pipedelay-3 = <0x2>; 180 xlnx,tavdv-ps-mem-0 = <0x1adb0>; 181 xlnx,tavdv-ps-mem-1 = <0x3a98>; 182 xlnx,tavdv-ps-mem-2 = <0x3a98>; 183 xlnx,tavdv-ps-mem-3 = <0x3a98>; 184 xlnx,tcedv-ps-mem-0 = <0x1adb0>; 185 xlnx,tcedv-ps-mem-1 = <0x3a98>; 186 xlnx,tcedv-ps-mem-2 = <0x3a98>; 187 xlnx,tcedv-ps-mem-3 = <0x3a98>; 188 xlnx,thzce-ps-mem-0 = <0x88b8>; 189 xlnx,thzce-ps-mem-1 = <0x1b58>; 190 xlnx,thzce-ps-mem-2 = <0x1b58>; 191 xlnx,thzce-ps-mem-3 = <0x1b58>; 192 xlnx,thzoe-ps-mem-0 = <0x1b58>; 193 xlnx,thzoe-ps-mem-1 = <0x1b58>; 194 xlnx,thzoe-ps-mem-2 = <0x1b58>; 195 xlnx,thzoe-ps-mem-3 = <0x1b58>; 196 xlnx,tlzwe-ps-mem-0 = <0x88b8>; 197 xlnx,tlzwe-ps-mem-1 = <0x0>; 198 xlnx,tlzwe-ps-mem-2 = <0x0>; 199 xlnx,tlzwe-ps-mem-3 = <0x0>; 200 xlnx,twc-ps-mem-0 = <0x2af8>; 201 xlnx,twc-ps-mem-1 = <0x3a98>; 202 xlnx,twc-ps-mem-2 = <0x3a98>; 203 xlnx,twc-ps-mem-3 = <0x3a98>; 204 xlnx,twp-ps-mem-0 = <0x11170>; 205 xlnx,twp-ps-mem-1 = <0x2ee0>; 206 xlnx,twp-ps-mem-2 = <0x2ee0>; 207 xlnx,twp-ps-mem-3 = <0x2ee0>; 208 xlnx,xcl0-linesize = <0x4>; 209 xlnx,xcl0-writexfer = <0x1>; 210 xlnx,xcl1-linesize = <0x4>; 211 xlnx,xcl1-writexfer = <0x1>; 212 xlnx,xcl2-linesize = <0x4>; 213 xlnx,xcl2-writexfer = <0x1>; 214 xlnx,xcl3-linesize = <0x4>; 215 xlnx,xcl3-writexfer = <0x1>; 216 } ; 217 Hard_Ethernet_MAC: xps-ll-temac@81c00000 { 218 #address-cells = <1>; 219 #size-cells = <1>; 220 compatible = "xlnx,compound"; 221 ethernet@81c00000 { 222 compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a"; 223 device_type = "network"; 224 interrupt-parent = <&xps_intc_0>; 225 interrupts = < 5 2 >; 226 llink-connected = <&PIM3>; 227 local-mac-address = [ 00 0a 35 00 00 00 ]; 228 reg = < 0x81c00000 0x40 >; 229 xlnx,bus2core-clk-ratio = <0x1>; 230 xlnx,phy-type = <0x1>; 231 xlnx,phyaddr = <0x1>; 232 xlnx,rxcsum = <0x0>; 233 xlnx,rxfifo = <0x1000>; 234 xlnx,temac-type = <0x0>; 235 xlnx,txcsum = <0x0>; 236 xlnx,txfifo = <0x1000>; 237 } ; 238 } ; 239 IIC_EEPROM: i2c@81600000 { 240 compatible = "xlnx,xps-iic-2.00.a"; 241 interrupt-parent = <&xps_intc_0>; 242 interrupts = < 6 2 >; 243 reg = < 0x81600000 0x10000 >; 244 xlnx,clk-freq = <0x7735940>; 245 xlnx,family = "virtex5"; 246 xlnx,gpo-width = <0x1>; 247 xlnx,iic-freq = <0x186a0>; 248 xlnx,scl-inertial-delay = <0x0>; 249 xlnx,sda-inertial-delay = <0x0>; 250 xlnx,ten-bit-adr = <0x0>; 251 } ; 252 LEDs_8Bit: gpio@81400000 { 253 compatible = "xlnx,xps-gpio-1.00.a"; 254 interrupt-parent = <&xps_intc_0>; 255 interrupts = < 7 2 >; 256 reg = < 0x81400000 0x10000 >; 257 xlnx,all-inputs = <0x0>; 258 xlnx,all-inputs-2 = <0x0>; 259 xlnx,dout-default = <0x0>; 260 xlnx,dout-default-2 = <0x0>; 261 xlnx,family = "virtex5"; 262 xlnx,gpio-width = <0x8>; 263 xlnx,interrupt-present = <0x1>; 264 xlnx,is-bidir = <0x1>; 265 xlnx,is-bidir-2 = <0x1>; 266 xlnx,is-dual = <0x0>; 267 xlnx,tri-default = <0xffffffff>; 268 xlnx,tri-default-2 = <0xffffffff>; 269 #gpio-cells = <2>; 270 gpio-controller; 271 } ; 272 273 gpio-leds { 274 compatible = "gpio-leds"; 275 276 heartbeat { 277 label = "Heartbeat"; 278 gpios = <&LEDs_8Bit 4 1>; 279 linux,default-trigger = "heartbeat"; 280 }; 281 282 yellow { 283 label = "Yellow"; 284 gpios = <&LEDs_8Bit 5 1>; 285 }; 286 287 red { 288 label = "Red"; 289 gpios = <&LEDs_8Bit 6 1>; 290 }; 291 292 green { 293 label = "Green"; 294 gpios = <&LEDs_8Bit 7 1>; 295 }; 296 } ; 297 RS232_Uart_1: serial@84000000 { 298 clock-frequency = <125000000>; 299 compatible = "xlnx,xps-uartlite-1.00.a"; 300 current-speed = <115200>; 301 device_type = "serial"; 302 interrupt-parent = <&xps_intc_0>; 303 interrupts = < 8 0 >; 304 port-number = <0>; 305 reg = < 0x84000000 0x10000 >; 306 xlnx,baudrate = <0x1c200>; 307 xlnx,data-bits = <0x8>; 308 xlnx,family = "virtex5"; 309 xlnx,odd-parity = <0x0>; 310 xlnx,use-parity = <0x0>; 311 } ; 312 SysACE_CompactFlash: sysace@83600000 { 313 compatible = "xlnx,xps-sysace-1.00.a"; 314 interrupt-parent = <&xps_intc_0>; 315 interrupts = < 4 2 >; 316 reg = < 0x83600000 0x10000 >; 317 xlnx,family = "virtex5"; 318 xlnx,mem-width = <0x10>; 319 } ; 320 debug_module: debug@84400000 { 321 compatible = "xlnx,mdm-1.00.d"; 322 reg = < 0x84400000 0x10000 >; 323 xlnx,family = "virtex5"; 324 xlnx,interconnect = <0x1>; 325 xlnx,jtag-chain = <0x2>; 326 xlnx,mb-dbg-ports = <0x1>; 327 xlnx,uart-width = <0x8>; 328 xlnx,use-uart = <0x1>; 329 xlnx,write-fsl-ports = <0x0>; 330 } ; 331 mpmc@90000000 { 332 #address-cells = <1>; 333 #size-cells = <1>; 334 compatible = "xlnx,mpmc-4.02.a"; 335 PIM3: sdma@84600180 { 336 compatible = "xlnx,ll-dma-1.00.a"; 337 interrupt-parent = <&xps_intc_0>; 338 interrupts = < 2 2 1 2 >; 339 reg = < 0x84600180 0x80 >; 340 } ; 341 } ; 342 xps_intc_0: interrupt-controller@81800000 { 343 #interrupt-cells = <0x2>; 344 compatible = "xlnx,xps-intc-1.00.a"; 345 interrupt-controller ; 346 reg = < 0x81800000 0x10000 >; 347 xlnx,kind-of-intr = <0x100>; 348 xlnx,num-intr-inputs = <0x9>; 349 } ; 350 xps_timer_1: timer@83c00000 { 351 compatible = "xlnx,xps-timer-1.00.a"; 352 interrupt-parent = <&xps_intc_0>; 353 interrupts = < 3 2 >; 354 reg = < 0x83c00000 0x10000 >; 355 xlnx,count-width = <0x20>; 356 xlnx,family = "virtex5"; 357 xlnx,gen0-assert = <0x1>; 358 xlnx,gen1-assert = <0x1>; 359 xlnx,one-timer-only = <0x0>; 360 xlnx,trig0-assert = <0x1>; 361 xlnx,trig1-assert = <0x1>; 362 } ; 363 } ; 364} ; 365