1/* 2 * Support for MicroBlaze PVR (processor version register) 3 * 4 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 5 * Copyright (C) 2007-2009 PetaLogix 6 * Copyright (C) 2007 John Williams <john.williams@petalogix.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13#include <linux/init.h> 14#include <linux/string.h> 15#include <asm/pvr.h> 16#include <asm/cpuinfo.h> 17 18/* 19 * Helper macro to map between fields in our struct cpuinfo, and 20 * the PVR macros in pvr.h. 21 */ 22 23#define CI(c, p) { ci->c = PVR_##p(pvr); } 24 25#if defined(CONFIG_EARLY_PRINTK) && defined(CONFIG_SERIAL_UARTLITE_CONSOLE) 26#define err_printk(x) \ 27 early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n"); 28#else 29#define err_printk(x) \ 30 printk(KERN_INFO "ERROR: Microblaze " x "-different for PVR and DTS\n"); 31#endif 32 33void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) 34{ 35 struct pvr_s pvr; 36 int temp; /* for saving temp value */ 37 get_pvr(&pvr); 38 39 CI(ver_code, VERSION); 40 if (!ci->ver_code) { 41 printk(KERN_ERR "ERROR: MB has broken PVR regs " 42 "-> use DTS setting\n"); 43 return; 44 } 45 46 temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |\ 47 PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr); 48 if (ci->use_instr != temp) 49 err_printk("BARREL, MSR, PCMP or DIV"); 50 ci->use_instr = temp; 51 52 temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr); 53 if (ci->use_mult != temp) 54 err_printk("HW_MUL"); 55 ci->use_mult = temp; 56 57 temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr); 58 if (ci->use_fpu != temp) 59 err_printk("HW_FPU"); 60 ci->use_fpu = temp; 61 62 ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |\ 63 PVR_UNALIGNED_EXCEPTION(pvr) |\ 64 PVR_ILL_OPCODE_EXCEPTION(pvr) |\ 65 PVR_IOPB_BUS_EXCEPTION(pvr) |\ 66 PVR_DOPB_BUS_EXCEPTION(pvr) |\ 67 PVR_DIV_ZERO_EXCEPTION(pvr) |\ 68 PVR_FPU_EXCEPTION(pvr) |\ 69 PVR_FSL_EXCEPTION(pvr); 70 71 CI(pvr_user1, USER1); 72 CI(pvr_user2, USER2); 73 74 CI(mmu, USE_MMU); 75 76 CI(use_icache, USE_ICACHE); 77 CI(icache_tagbits, ICACHE_ADDR_TAG_BITS); 78 CI(icache_write, ICACHE_ALLOW_WR); 79 ci->icache_line_length = PVR_ICACHE_LINE_LEN(pvr) << 2; 80 CI(icache_size, ICACHE_BYTE_SIZE); 81 CI(icache_base, ICACHE_BASEADDR); 82 CI(icache_high, ICACHE_HIGHADDR); 83 84 CI(use_dcache, USE_DCACHE); 85 CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS); 86 CI(dcache_write, DCACHE_ALLOW_WR); 87 ci->dcache_line_length = PVR_DCACHE_LINE_LEN(pvr) << 2; 88 CI(dcache_size, DCACHE_BYTE_SIZE); 89 CI(dcache_base, DCACHE_BASEADDR); 90 CI(dcache_high, DCACHE_HIGHADDR); 91 92 temp = PVR_DCACHE_USE_WRITEBACK(pvr); 93 if (ci->dcache_wb != temp) 94 err_printk("DCACHE WB"); 95 ci->dcache_wb = temp; 96 97 CI(use_dopb, D_OPB); 98 CI(use_iopb, I_OPB); 99 CI(use_dlmb, D_LMB); 100 CI(use_ilmb, I_LMB); 101 CI(num_fsl, FSL_LINKS); 102 103 CI(irq_edge, INTERRUPT_IS_EDGE); 104 CI(irq_positive, EDGE_IS_POSITIVE); 105 106 CI(area_optimised, AREA_OPTIMISED); 107 108 CI(hw_debug, DEBUG_ENABLED); 109 CI(num_pc_brk, NUMBER_OF_PC_BRK); 110 CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK); 111 CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK); 112 113 CI(fpga_family_code, TARGET_FAMILY); 114 115 /* take timebase-frequency from DTS */ 116 ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency"); 117} 118