1/* 2 * General Purpose functions for the global management of the 3 * Communication Processor Module. 4 * 5 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> 6 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 7 * 8 * In addition to the individual control of the communication 9 * channels, there are a few functions that globally affect the 10 * communication processor. 11 * 12 * Buffer descriptors must be allocated from the dual ported memory 13 * space. The allocator for that is here. When the communication 14 * process is reset, we reclaim the memory available. There is 15 * currently no deallocator for this memory. 16 * The amount of space available is platform dependent. On the 17 * MBX, the EPPC software loads additional microcode into the 18 * communication processor, and uses some of the DP ram for this 19 * purpose. Current, the first 512 bytes and the last 256 bytes of 20 * memory are used. Right now I am conservative and only use the 21 * memory that can never be used for microcode. If there are 22 * applications that require more DP ram, we can expand the boundaries 23 * but then we have to be careful of any downloaded microcode. 24 * 25 */ 26 27/* 28 * Michael Leslie <mleslie@lineo.com> 29 * adapted Dan Malek's ppc8xx drivers to M68360 30 * 31 */ 32 33#include <linux/errno.h> 34#include <linux/sched.h> 35#include <linux/kernel.h> 36#include <linux/param.h> 37#include <linux/string.h> 38#include <linux/mm.h> 39#include <linux/interrupt.h> 40#include <asm/irq.h> 41#include <asm/m68360.h> 42#include <asm/commproc.h> 43 44/* #include <asm/page.h> */ 45/* #include <asm/pgtable.h> */ 46extern void *_quicc_base; 47extern unsigned int system_clock; 48 49 50static uint dp_alloc_base; /* Starting offset in DP ram */ 51static uint dp_alloc_top; /* Max offset + 1 */ 52 53 54/* struct cpm360_t *cpmp; */ /* Pointer to comm processor space */ 55 56QUICC *pquicc; 57/* QUICC *quicc_dpram; */ /* mleslie - temporary; use extern pquicc elsewhere instead */ 58 59 60/* CPM interrupt vector functions. */ 61struct cpm_action { 62 void (*handler)(void *); 63 void *dev_id; 64}; 65static struct cpm_action cpm_vecs[CPMVEC_NR]; 66static void cpm_interrupt(int irq, void * dev, struct pt_regs * regs); 67static void cpm_error_interrupt(void *); 68 69/* prototypes: */ 70void cpm_install_handler(int vec, void (*handler)(), void *dev_id); 71void m360_cpm_reset(void); 72 73 74 75 76void m360_cpm_reset() 77{ 78/* pte_t *pte; */ 79 80 pquicc = (struct quicc *)(_quicc_base); /* initialized in crt0_rXm.S */ 81 82 /* Perform a CPM reset. */ 83 pquicc->cp_cr = (SOFTWARE_RESET | CMD_FLAG); 84 85 /* Wait for CPM to become ready (should be 2 clocks). */ 86 while (pquicc->cp_cr & CMD_FLAG); 87 88 /* On the recommendation of the 68360 manual, p. 7-60 89 * - Set sdma interrupt service mask to 7 90 * - Set sdma arbitration ID to 4 91 */ 92 pquicc->sdma_sdcr = 0x0740; 93 94 95 /* Claim the DP memory for our use. 96 */ 97 dp_alloc_base = CPM_DATAONLY_BASE; 98 dp_alloc_top = dp_alloc_base + CPM_DATAONLY_SIZE; 99 100 101 /* Set the host page for allocation. 102 */ 103 /* host_buffer = host_page_addr; */ 104 /* host_end = host_page_addr + PAGE_SIZE; */ 105 106 /* pte = find_pte(&init_mm, host_page_addr); */ 107 /* pte_val(*pte) |= _PAGE_NO_CACHE; */ 108 /* flush_tlb_page(current->mm->mmap, host_buffer); */ 109 110 /* Tell everyone where the comm processor resides. 111 */ 112/* cpmp = (cpm360_t *)commproc; */ 113} 114 115 116/* This is called during init_IRQ. We used to do it above, but this 117 * was too early since init_IRQ was not yet called. 118 */ 119void 120cpm_interrupt_init(void) 121{ 122 /* Initialize the CPM interrupt controller. 123 * NOTE THAT pquicc had better have been initialized! 124 * reference: MC68360UM p. 7-377 125 */ 126 pquicc->intr_cicr = 127 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | 128 (CPM_INTERRUPT << 13) | 129 CICR_HP_MASK | 130 (CPM_VECTOR_BASE << 5) | 131 CICR_SPS; 132 133 /* mask all CPM interrupts from reaching the cpu32 core: */ 134 pquicc->intr_cimr = 0; 135 136 137 /* mles - If I understand correctly, the 360 just pops over to the CPM 138 * specific vector, obviating the necessity to vector through the IRQ 139 * whose priority the CPM is set to. This needs a closer look, though. 140 */ 141 142 /* Set our interrupt handler with the core CPU. */ 143/* if (request_irq(CPM_INTERRUPT, cpm_interrupt, 0, "cpm", NULL) != 0) */ 144/* panic("Could not allocate CPM IRQ!"); */ 145 146 /* Install our own error handler. 147 */ 148 /* I think we want to hold off on this one for the moment - mles */ 149 /* cpm_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL); */ 150 151 /* master CPM interrupt enable */ 152 /* pquicc->intr_cicr |= CICR_IEN; */ /* no such animal for 360 */ 153} 154 155 156 157/* CPM interrupt controller interrupt. 158*/ 159static void 160cpm_interrupt(int irq, void * dev, struct pt_regs * regs) 161{ 162 /* uint vec; */ 163 164 /* mles: Note that this stuff is currently being performed by 165 * M68360_do_irq(int vec, struct pt_regs *fp), in ../ints.c */ 166 167 /* figure out the vector */ 168 /* call that vector's handler */ 169 /* clear the irq's bit in the service register */ 170 171 172} 173 174/* The CPM can generate the error interrupt when there is a race condition 175 * between generating and masking interrupts. All we have to do is ACK it 176 * and return. This is a no-op function so we don't need any special 177 * tests in the interrupt handler. 178 */ 179static void 180cpm_error_interrupt(void *dev) 181{ 182} 183 184/* Install a CPM interrupt handler. 185*/ 186void 187cpm_install_handler(int vec, void (*handler)(), void *dev_id) 188{ 189 190 request_irq(vec, handler, IRQ_FLG_LOCK, "timer", dev_id); 191 192/* if (cpm_vecs[vec].handler != 0) */ 193/* printk(KERN_INFO "CPM interrupt %x replacing %x\n", */ 194/* (uint)handler, (uint)cpm_vecs[vec].handler); */ 195/* cpm_vecs[vec].handler = handler; */ 196/* cpm_vecs[vec].dev_id = dev_id; */ 197 198 /* ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << vec); */ 199/* pquicc->intr_cimr |= (1 << vec); */ 200 201} 202 203/* Free a CPM interrupt handler. 204*/ 205void 206cpm_free_handler(int vec) 207{ 208 cpm_vecs[vec].handler = NULL; 209 cpm_vecs[vec].dev_id = NULL; 210 /* ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec); */ 211 pquicc->intr_cimr &= ~(1 << vec); 212} 213 214 215 216 217/* Allocate some memory from the dual ported ram. We may want to 218 * enforce alignment restrictions, but right now everyone is a good 219 * citizen. 220 */ 221uint 222m360_cpm_dpalloc(uint size) 223{ 224 uint retloc; 225 226 if ((dp_alloc_base + size) >= dp_alloc_top) 227 return(CPM_DP_NOSPACE); 228 229 retloc = dp_alloc_base; 230 dp_alloc_base += size; 231 232 return(retloc); 233} 234 235 236 237 238/* Set a baud rate generator. This needs lots of work. There are 239 * four BRGs, any of which can be wired to any channel. 240 * The internal baud rate clock is the system clock divided by 16. 241 * This assumes the baudrate is 16x oversampled by the uart. 242 */ 243/* #define BRG_INT_CLK (((bd_t *)__res)->bi_intfreq * 1000000) */ 244#define BRG_INT_CLK system_clock 245#define BRG_UART_CLK (BRG_INT_CLK/16) 246 247void 248m360_cpm_setbrg(uint brg, uint rate) 249{ 250 volatile uint *bp; 251 252 /* This is good enough to get SMCs running..... 253 */ 254 /* bp = (uint *)&cpmp->cp_brgc1; */ 255 bp = (volatile uint *)(&pquicc->brgc[0].l); 256 bp += brg; 257 *bp = ((BRG_UART_CLK / rate - 1) << 1) | CPM_BRG_EN; 258} 259 260 261/* 262 * Local variables: 263 * c-indent-level: 4 264 * c-basic-offset: 4 265 * tab-width: 4 266 * End: 267 */ 268