1#ifndef __pinmux_defs_asm_h 2#define __pinmux_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r 7 * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp 8 * last modfied: Mon Apr 11 16:09:11 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r 11 * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_pa, scope pinmux, type rw */ 57#define reg_pinmux_rw_pa___pa0___lsb 0 58#define reg_pinmux_rw_pa___pa0___width 1 59#define reg_pinmux_rw_pa___pa0___bit 0 60#define reg_pinmux_rw_pa___pa1___lsb 1 61#define reg_pinmux_rw_pa___pa1___width 1 62#define reg_pinmux_rw_pa___pa1___bit 1 63#define reg_pinmux_rw_pa___pa2___lsb 2 64#define reg_pinmux_rw_pa___pa2___width 1 65#define reg_pinmux_rw_pa___pa2___bit 2 66#define reg_pinmux_rw_pa___pa3___lsb 3 67#define reg_pinmux_rw_pa___pa3___width 1 68#define reg_pinmux_rw_pa___pa3___bit 3 69#define reg_pinmux_rw_pa___pa4___lsb 4 70#define reg_pinmux_rw_pa___pa4___width 1 71#define reg_pinmux_rw_pa___pa4___bit 4 72#define reg_pinmux_rw_pa___pa5___lsb 5 73#define reg_pinmux_rw_pa___pa5___width 1 74#define reg_pinmux_rw_pa___pa5___bit 5 75#define reg_pinmux_rw_pa___pa6___lsb 6 76#define reg_pinmux_rw_pa___pa6___width 1 77#define reg_pinmux_rw_pa___pa6___bit 6 78#define reg_pinmux_rw_pa___pa7___lsb 7 79#define reg_pinmux_rw_pa___pa7___width 1 80#define reg_pinmux_rw_pa___pa7___bit 7 81#define reg_pinmux_rw_pa___csp2_n___lsb 8 82#define reg_pinmux_rw_pa___csp2_n___width 1 83#define reg_pinmux_rw_pa___csp2_n___bit 8 84#define reg_pinmux_rw_pa___csp3_n___lsb 9 85#define reg_pinmux_rw_pa___csp3_n___width 1 86#define reg_pinmux_rw_pa___csp3_n___bit 9 87#define reg_pinmux_rw_pa___csp5_n___lsb 10 88#define reg_pinmux_rw_pa___csp5_n___width 1 89#define reg_pinmux_rw_pa___csp5_n___bit 10 90#define reg_pinmux_rw_pa___csp6_n___lsb 11 91#define reg_pinmux_rw_pa___csp6_n___width 1 92#define reg_pinmux_rw_pa___csp6_n___bit 11 93#define reg_pinmux_rw_pa___hsh4___lsb 12 94#define reg_pinmux_rw_pa___hsh4___width 1 95#define reg_pinmux_rw_pa___hsh4___bit 12 96#define reg_pinmux_rw_pa___hsh5___lsb 13 97#define reg_pinmux_rw_pa___hsh5___width 1 98#define reg_pinmux_rw_pa___hsh5___bit 13 99#define reg_pinmux_rw_pa___hsh6___lsb 14 100#define reg_pinmux_rw_pa___hsh6___width 1 101#define reg_pinmux_rw_pa___hsh6___bit 14 102#define reg_pinmux_rw_pa___hsh7___lsb 15 103#define reg_pinmux_rw_pa___hsh7___width 1 104#define reg_pinmux_rw_pa___hsh7___bit 15 105#define reg_pinmux_rw_pa_offset 0 106 107/* Register rw_hwprot, scope pinmux, type rw */ 108#define reg_pinmux_rw_hwprot___ser1___lsb 0 109#define reg_pinmux_rw_hwprot___ser1___width 1 110#define reg_pinmux_rw_hwprot___ser1___bit 0 111#define reg_pinmux_rw_hwprot___ser2___lsb 1 112#define reg_pinmux_rw_hwprot___ser2___width 1 113#define reg_pinmux_rw_hwprot___ser2___bit 1 114#define reg_pinmux_rw_hwprot___ser3___lsb 2 115#define reg_pinmux_rw_hwprot___ser3___width 1 116#define reg_pinmux_rw_hwprot___ser3___bit 2 117#define reg_pinmux_rw_hwprot___sser0___lsb 3 118#define reg_pinmux_rw_hwprot___sser0___width 1 119#define reg_pinmux_rw_hwprot___sser0___bit 3 120#define reg_pinmux_rw_hwprot___sser1___lsb 4 121#define reg_pinmux_rw_hwprot___sser1___width 1 122#define reg_pinmux_rw_hwprot___sser1___bit 4 123#define reg_pinmux_rw_hwprot___ata0___lsb 5 124#define reg_pinmux_rw_hwprot___ata0___width 1 125#define reg_pinmux_rw_hwprot___ata0___bit 5 126#define reg_pinmux_rw_hwprot___ata1___lsb 6 127#define reg_pinmux_rw_hwprot___ata1___width 1 128#define reg_pinmux_rw_hwprot___ata1___bit 6 129#define reg_pinmux_rw_hwprot___ata2___lsb 7 130#define reg_pinmux_rw_hwprot___ata2___width 1 131#define reg_pinmux_rw_hwprot___ata2___bit 7 132#define reg_pinmux_rw_hwprot___ata3___lsb 8 133#define reg_pinmux_rw_hwprot___ata3___width 1 134#define reg_pinmux_rw_hwprot___ata3___bit 8 135#define reg_pinmux_rw_hwprot___ata___lsb 9 136#define reg_pinmux_rw_hwprot___ata___width 1 137#define reg_pinmux_rw_hwprot___ata___bit 9 138#define reg_pinmux_rw_hwprot___eth1___lsb 10 139#define reg_pinmux_rw_hwprot___eth1___width 1 140#define reg_pinmux_rw_hwprot___eth1___bit 10 141#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 142#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 143#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 144#define reg_pinmux_rw_hwprot___timer___lsb 12 145#define reg_pinmux_rw_hwprot___timer___width 1 146#define reg_pinmux_rw_hwprot___timer___bit 12 147#define reg_pinmux_rw_hwprot___p21___lsb 13 148#define reg_pinmux_rw_hwprot___p21___width 1 149#define reg_pinmux_rw_hwprot___p21___bit 13 150#define reg_pinmux_rw_hwprot_offset 4 151 152/* Register rw_pb_gio, scope pinmux, type rw */ 153#define reg_pinmux_rw_pb_gio___pb0___lsb 0 154#define reg_pinmux_rw_pb_gio___pb0___width 1 155#define reg_pinmux_rw_pb_gio___pb0___bit 0 156#define reg_pinmux_rw_pb_gio___pb1___lsb 1 157#define reg_pinmux_rw_pb_gio___pb1___width 1 158#define reg_pinmux_rw_pb_gio___pb1___bit 1 159#define reg_pinmux_rw_pb_gio___pb2___lsb 2 160#define reg_pinmux_rw_pb_gio___pb2___width 1 161#define reg_pinmux_rw_pb_gio___pb2___bit 2 162#define reg_pinmux_rw_pb_gio___pb3___lsb 3 163#define reg_pinmux_rw_pb_gio___pb3___width 1 164#define reg_pinmux_rw_pb_gio___pb3___bit 3 165#define reg_pinmux_rw_pb_gio___pb4___lsb 4 166#define reg_pinmux_rw_pb_gio___pb4___width 1 167#define reg_pinmux_rw_pb_gio___pb4___bit 4 168#define reg_pinmux_rw_pb_gio___pb5___lsb 5 169#define reg_pinmux_rw_pb_gio___pb5___width 1 170#define reg_pinmux_rw_pb_gio___pb5___bit 5 171#define reg_pinmux_rw_pb_gio___pb6___lsb 6 172#define reg_pinmux_rw_pb_gio___pb6___width 1 173#define reg_pinmux_rw_pb_gio___pb6___bit 6 174#define reg_pinmux_rw_pb_gio___pb7___lsb 7 175#define reg_pinmux_rw_pb_gio___pb7___width 1 176#define reg_pinmux_rw_pb_gio___pb7___bit 7 177#define reg_pinmux_rw_pb_gio___pb8___lsb 8 178#define reg_pinmux_rw_pb_gio___pb8___width 1 179#define reg_pinmux_rw_pb_gio___pb8___bit 8 180#define reg_pinmux_rw_pb_gio___pb9___lsb 9 181#define reg_pinmux_rw_pb_gio___pb9___width 1 182#define reg_pinmux_rw_pb_gio___pb9___bit 9 183#define reg_pinmux_rw_pb_gio___pb10___lsb 10 184#define reg_pinmux_rw_pb_gio___pb10___width 1 185#define reg_pinmux_rw_pb_gio___pb10___bit 10 186#define reg_pinmux_rw_pb_gio___pb11___lsb 11 187#define reg_pinmux_rw_pb_gio___pb11___width 1 188#define reg_pinmux_rw_pb_gio___pb11___bit 11 189#define reg_pinmux_rw_pb_gio___pb12___lsb 12 190#define reg_pinmux_rw_pb_gio___pb12___width 1 191#define reg_pinmux_rw_pb_gio___pb12___bit 12 192#define reg_pinmux_rw_pb_gio___pb13___lsb 13 193#define reg_pinmux_rw_pb_gio___pb13___width 1 194#define reg_pinmux_rw_pb_gio___pb13___bit 13 195#define reg_pinmux_rw_pb_gio___pb14___lsb 14 196#define reg_pinmux_rw_pb_gio___pb14___width 1 197#define reg_pinmux_rw_pb_gio___pb14___bit 14 198#define reg_pinmux_rw_pb_gio___pb15___lsb 15 199#define reg_pinmux_rw_pb_gio___pb15___width 1 200#define reg_pinmux_rw_pb_gio___pb15___bit 15 201#define reg_pinmux_rw_pb_gio___pb16___lsb 16 202#define reg_pinmux_rw_pb_gio___pb16___width 1 203#define reg_pinmux_rw_pb_gio___pb16___bit 16 204#define reg_pinmux_rw_pb_gio___pb17___lsb 17 205#define reg_pinmux_rw_pb_gio___pb17___width 1 206#define reg_pinmux_rw_pb_gio___pb17___bit 17 207#define reg_pinmux_rw_pb_gio_offset 8 208 209/* Register rw_pb_iop, scope pinmux, type rw */ 210#define reg_pinmux_rw_pb_iop___pb0___lsb 0 211#define reg_pinmux_rw_pb_iop___pb0___width 1 212#define reg_pinmux_rw_pb_iop___pb0___bit 0 213#define reg_pinmux_rw_pb_iop___pb1___lsb 1 214#define reg_pinmux_rw_pb_iop___pb1___width 1 215#define reg_pinmux_rw_pb_iop___pb1___bit 1 216#define reg_pinmux_rw_pb_iop___pb2___lsb 2 217#define reg_pinmux_rw_pb_iop___pb2___width 1 218#define reg_pinmux_rw_pb_iop___pb2___bit 2 219#define reg_pinmux_rw_pb_iop___pb3___lsb 3 220#define reg_pinmux_rw_pb_iop___pb3___width 1 221#define reg_pinmux_rw_pb_iop___pb3___bit 3 222#define reg_pinmux_rw_pb_iop___pb4___lsb 4 223#define reg_pinmux_rw_pb_iop___pb4___width 1 224#define reg_pinmux_rw_pb_iop___pb4___bit 4 225#define reg_pinmux_rw_pb_iop___pb5___lsb 5 226#define reg_pinmux_rw_pb_iop___pb5___width 1 227#define reg_pinmux_rw_pb_iop___pb5___bit 5 228#define reg_pinmux_rw_pb_iop___pb6___lsb 6 229#define reg_pinmux_rw_pb_iop___pb6___width 1 230#define reg_pinmux_rw_pb_iop___pb6___bit 6 231#define reg_pinmux_rw_pb_iop___pb7___lsb 7 232#define reg_pinmux_rw_pb_iop___pb7___width 1 233#define reg_pinmux_rw_pb_iop___pb7___bit 7 234#define reg_pinmux_rw_pb_iop___pb8___lsb 8 235#define reg_pinmux_rw_pb_iop___pb8___width 1 236#define reg_pinmux_rw_pb_iop___pb8___bit 8 237#define reg_pinmux_rw_pb_iop___pb9___lsb 9 238#define reg_pinmux_rw_pb_iop___pb9___width 1 239#define reg_pinmux_rw_pb_iop___pb9___bit 9 240#define reg_pinmux_rw_pb_iop___pb10___lsb 10 241#define reg_pinmux_rw_pb_iop___pb10___width 1 242#define reg_pinmux_rw_pb_iop___pb10___bit 10 243#define reg_pinmux_rw_pb_iop___pb11___lsb 11 244#define reg_pinmux_rw_pb_iop___pb11___width 1 245#define reg_pinmux_rw_pb_iop___pb11___bit 11 246#define reg_pinmux_rw_pb_iop___pb12___lsb 12 247#define reg_pinmux_rw_pb_iop___pb12___width 1 248#define reg_pinmux_rw_pb_iop___pb12___bit 12 249#define reg_pinmux_rw_pb_iop___pb13___lsb 13 250#define reg_pinmux_rw_pb_iop___pb13___width 1 251#define reg_pinmux_rw_pb_iop___pb13___bit 13 252#define reg_pinmux_rw_pb_iop___pb14___lsb 14 253#define reg_pinmux_rw_pb_iop___pb14___width 1 254#define reg_pinmux_rw_pb_iop___pb14___bit 14 255#define reg_pinmux_rw_pb_iop___pb15___lsb 15 256#define reg_pinmux_rw_pb_iop___pb15___width 1 257#define reg_pinmux_rw_pb_iop___pb15___bit 15 258#define reg_pinmux_rw_pb_iop___pb16___lsb 16 259#define reg_pinmux_rw_pb_iop___pb16___width 1 260#define reg_pinmux_rw_pb_iop___pb16___bit 16 261#define reg_pinmux_rw_pb_iop___pb17___lsb 17 262#define reg_pinmux_rw_pb_iop___pb17___width 1 263#define reg_pinmux_rw_pb_iop___pb17___bit 17 264#define reg_pinmux_rw_pb_iop_offset 12 265 266/* Register rw_pc_gio, scope pinmux, type rw */ 267#define reg_pinmux_rw_pc_gio___pc0___lsb 0 268#define reg_pinmux_rw_pc_gio___pc0___width 1 269#define reg_pinmux_rw_pc_gio___pc0___bit 0 270#define reg_pinmux_rw_pc_gio___pc1___lsb 1 271#define reg_pinmux_rw_pc_gio___pc1___width 1 272#define reg_pinmux_rw_pc_gio___pc1___bit 1 273#define reg_pinmux_rw_pc_gio___pc2___lsb 2 274#define reg_pinmux_rw_pc_gio___pc2___width 1 275#define reg_pinmux_rw_pc_gio___pc2___bit 2 276#define reg_pinmux_rw_pc_gio___pc3___lsb 3 277#define reg_pinmux_rw_pc_gio___pc3___width 1 278#define reg_pinmux_rw_pc_gio___pc3___bit 3 279#define reg_pinmux_rw_pc_gio___pc4___lsb 4 280#define reg_pinmux_rw_pc_gio___pc4___width 1 281#define reg_pinmux_rw_pc_gio___pc4___bit 4 282#define reg_pinmux_rw_pc_gio___pc5___lsb 5 283#define reg_pinmux_rw_pc_gio___pc5___width 1 284#define reg_pinmux_rw_pc_gio___pc5___bit 5 285#define reg_pinmux_rw_pc_gio___pc6___lsb 6 286#define reg_pinmux_rw_pc_gio___pc6___width 1 287#define reg_pinmux_rw_pc_gio___pc6___bit 6 288#define reg_pinmux_rw_pc_gio___pc7___lsb 7 289#define reg_pinmux_rw_pc_gio___pc7___width 1 290#define reg_pinmux_rw_pc_gio___pc7___bit 7 291#define reg_pinmux_rw_pc_gio___pc8___lsb 8 292#define reg_pinmux_rw_pc_gio___pc8___width 1 293#define reg_pinmux_rw_pc_gio___pc8___bit 8 294#define reg_pinmux_rw_pc_gio___pc9___lsb 9 295#define reg_pinmux_rw_pc_gio___pc9___width 1 296#define reg_pinmux_rw_pc_gio___pc9___bit 9 297#define reg_pinmux_rw_pc_gio___pc10___lsb 10 298#define reg_pinmux_rw_pc_gio___pc10___width 1 299#define reg_pinmux_rw_pc_gio___pc10___bit 10 300#define reg_pinmux_rw_pc_gio___pc11___lsb 11 301#define reg_pinmux_rw_pc_gio___pc11___width 1 302#define reg_pinmux_rw_pc_gio___pc11___bit 11 303#define reg_pinmux_rw_pc_gio___pc12___lsb 12 304#define reg_pinmux_rw_pc_gio___pc12___width 1 305#define reg_pinmux_rw_pc_gio___pc12___bit 12 306#define reg_pinmux_rw_pc_gio___pc13___lsb 13 307#define reg_pinmux_rw_pc_gio___pc13___width 1 308#define reg_pinmux_rw_pc_gio___pc13___bit 13 309#define reg_pinmux_rw_pc_gio___pc14___lsb 14 310#define reg_pinmux_rw_pc_gio___pc14___width 1 311#define reg_pinmux_rw_pc_gio___pc14___bit 14 312#define reg_pinmux_rw_pc_gio___pc15___lsb 15 313#define reg_pinmux_rw_pc_gio___pc15___width 1 314#define reg_pinmux_rw_pc_gio___pc15___bit 15 315#define reg_pinmux_rw_pc_gio___pc16___lsb 16 316#define reg_pinmux_rw_pc_gio___pc16___width 1 317#define reg_pinmux_rw_pc_gio___pc16___bit 16 318#define reg_pinmux_rw_pc_gio___pc17___lsb 17 319#define reg_pinmux_rw_pc_gio___pc17___width 1 320#define reg_pinmux_rw_pc_gio___pc17___bit 17 321#define reg_pinmux_rw_pc_gio_offset 16 322 323/* Register rw_pc_iop, scope pinmux, type rw */ 324#define reg_pinmux_rw_pc_iop___pc0___lsb 0 325#define reg_pinmux_rw_pc_iop___pc0___width 1 326#define reg_pinmux_rw_pc_iop___pc0___bit 0 327#define reg_pinmux_rw_pc_iop___pc1___lsb 1 328#define reg_pinmux_rw_pc_iop___pc1___width 1 329#define reg_pinmux_rw_pc_iop___pc1___bit 1 330#define reg_pinmux_rw_pc_iop___pc2___lsb 2 331#define reg_pinmux_rw_pc_iop___pc2___width 1 332#define reg_pinmux_rw_pc_iop___pc2___bit 2 333#define reg_pinmux_rw_pc_iop___pc3___lsb 3 334#define reg_pinmux_rw_pc_iop___pc3___width 1 335#define reg_pinmux_rw_pc_iop___pc3___bit 3 336#define reg_pinmux_rw_pc_iop___pc4___lsb 4 337#define reg_pinmux_rw_pc_iop___pc4___width 1 338#define reg_pinmux_rw_pc_iop___pc4___bit 4 339#define reg_pinmux_rw_pc_iop___pc5___lsb 5 340#define reg_pinmux_rw_pc_iop___pc5___width 1 341#define reg_pinmux_rw_pc_iop___pc5___bit 5 342#define reg_pinmux_rw_pc_iop___pc6___lsb 6 343#define reg_pinmux_rw_pc_iop___pc6___width 1 344#define reg_pinmux_rw_pc_iop___pc6___bit 6 345#define reg_pinmux_rw_pc_iop___pc7___lsb 7 346#define reg_pinmux_rw_pc_iop___pc7___width 1 347#define reg_pinmux_rw_pc_iop___pc7___bit 7 348#define reg_pinmux_rw_pc_iop___pc8___lsb 8 349#define reg_pinmux_rw_pc_iop___pc8___width 1 350#define reg_pinmux_rw_pc_iop___pc8___bit 8 351#define reg_pinmux_rw_pc_iop___pc9___lsb 9 352#define reg_pinmux_rw_pc_iop___pc9___width 1 353#define reg_pinmux_rw_pc_iop___pc9___bit 9 354#define reg_pinmux_rw_pc_iop___pc10___lsb 10 355#define reg_pinmux_rw_pc_iop___pc10___width 1 356#define reg_pinmux_rw_pc_iop___pc10___bit 10 357#define reg_pinmux_rw_pc_iop___pc11___lsb 11 358#define reg_pinmux_rw_pc_iop___pc11___width 1 359#define reg_pinmux_rw_pc_iop___pc11___bit 11 360#define reg_pinmux_rw_pc_iop___pc12___lsb 12 361#define reg_pinmux_rw_pc_iop___pc12___width 1 362#define reg_pinmux_rw_pc_iop___pc12___bit 12 363#define reg_pinmux_rw_pc_iop___pc13___lsb 13 364#define reg_pinmux_rw_pc_iop___pc13___width 1 365#define reg_pinmux_rw_pc_iop___pc13___bit 13 366#define reg_pinmux_rw_pc_iop___pc14___lsb 14 367#define reg_pinmux_rw_pc_iop___pc14___width 1 368#define reg_pinmux_rw_pc_iop___pc14___bit 14 369#define reg_pinmux_rw_pc_iop___pc15___lsb 15 370#define reg_pinmux_rw_pc_iop___pc15___width 1 371#define reg_pinmux_rw_pc_iop___pc15___bit 15 372#define reg_pinmux_rw_pc_iop___pc16___lsb 16 373#define reg_pinmux_rw_pc_iop___pc16___width 1 374#define reg_pinmux_rw_pc_iop___pc16___bit 16 375#define reg_pinmux_rw_pc_iop___pc17___lsb 17 376#define reg_pinmux_rw_pc_iop___pc17___width 1 377#define reg_pinmux_rw_pc_iop___pc17___bit 17 378#define reg_pinmux_rw_pc_iop_offset 20 379 380/* Register rw_pd_gio, scope pinmux, type rw */ 381#define reg_pinmux_rw_pd_gio___pd0___lsb 0 382#define reg_pinmux_rw_pd_gio___pd0___width 1 383#define reg_pinmux_rw_pd_gio___pd0___bit 0 384#define reg_pinmux_rw_pd_gio___pd1___lsb 1 385#define reg_pinmux_rw_pd_gio___pd1___width 1 386#define reg_pinmux_rw_pd_gio___pd1___bit 1 387#define reg_pinmux_rw_pd_gio___pd2___lsb 2 388#define reg_pinmux_rw_pd_gio___pd2___width 1 389#define reg_pinmux_rw_pd_gio___pd2___bit 2 390#define reg_pinmux_rw_pd_gio___pd3___lsb 3 391#define reg_pinmux_rw_pd_gio___pd3___width 1 392#define reg_pinmux_rw_pd_gio___pd3___bit 3 393#define reg_pinmux_rw_pd_gio___pd4___lsb 4 394#define reg_pinmux_rw_pd_gio___pd4___width 1 395#define reg_pinmux_rw_pd_gio___pd4___bit 4 396#define reg_pinmux_rw_pd_gio___pd5___lsb 5 397#define reg_pinmux_rw_pd_gio___pd5___width 1 398#define reg_pinmux_rw_pd_gio___pd5___bit 5 399#define reg_pinmux_rw_pd_gio___pd6___lsb 6 400#define reg_pinmux_rw_pd_gio___pd6___width 1 401#define reg_pinmux_rw_pd_gio___pd6___bit 6 402#define reg_pinmux_rw_pd_gio___pd7___lsb 7 403#define reg_pinmux_rw_pd_gio___pd7___width 1 404#define reg_pinmux_rw_pd_gio___pd7___bit 7 405#define reg_pinmux_rw_pd_gio___pd8___lsb 8 406#define reg_pinmux_rw_pd_gio___pd8___width 1 407#define reg_pinmux_rw_pd_gio___pd8___bit 8 408#define reg_pinmux_rw_pd_gio___pd9___lsb 9 409#define reg_pinmux_rw_pd_gio___pd9___width 1 410#define reg_pinmux_rw_pd_gio___pd9___bit 9 411#define reg_pinmux_rw_pd_gio___pd10___lsb 10 412#define reg_pinmux_rw_pd_gio___pd10___width 1 413#define reg_pinmux_rw_pd_gio___pd10___bit 10 414#define reg_pinmux_rw_pd_gio___pd11___lsb 11 415#define reg_pinmux_rw_pd_gio___pd11___width 1 416#define reg_pinmux_rw_pd_gio___pd11___bit 11 417#define reg_pinmux_rw_pd_gio___pd12___lsb 12 418#define reg_pinmux_rw_pd_gio___pd12___width 1 419#define reg_pinmux_rw_pd_gio___pd12___bit 12 420#define reg_pinmux_rw_pd_gio___pd13___lsb 13 421#define reg_pinmux_rw_pd_gio___pd13___width 1 422#define reg_pinmux_rw_pd_gio___pd13___bit 13 423#define reg_pinmux_rw_pd_gio___pd14___lsb 14 424#define reg_pinmux_rw_pd_gio___pd14___width 1 425#define reg_pinmux_rw_pd_gio___pd14___bit 14 426#define reg_pinmux_rw_pd_gio___pd15___lsb 15 427#define reg_pinmux_rw_pd_gio___pd15___width 1 428#define reg_pinmux_rw_pd_gio___pd15___bit 15 429#define reg_pinmux_rw_pd_gio___pd16___lsb 16 430#define reg_pinmux_rw_pd_gio___pd16___width 1 431#define reg_pinmux_rw_pd_gio___pd16___bit 16 432#define reg_pinmux_rw_pd_gio___pd17___lsb 17 433#define reg_pinmux_rw_pd_gio___pd17___width 1 434#define reg_pinmux_rw_pd_gio___pd17___bit 17 435#define reg_pinmux_rw_pd_gio_offset 24 436 437/* Register rw_pd_iop, scope pinmux, type rw */ 438#define reg_pinmux_rw_pd_iop___pd0___lsb 0 439#define reg_pinmux_rw_pd_iop___pd0___width 1 440#define reg_pinmux_rw_pd_iop___pd0___bit 0 441#define reg_pinmux_rw_pd_iop___pd1___lsb 1 442#define reg_pinmux_rw_pd_iop___pd1___width 1 443#define reg_pinmux_rw_pd_iop___pd1___bit 1 444#define reg_pinmux_rw_pd_iop___pd2___lsb 2 445#define reg_pinmux_rw_pd_iop___pd2___width 1 446#define reg_pinmux_rw_pd_iop___pd2___bit 2 447#define reg_pinmux_rw_pd_iop___pd3___lsb 3 448#define reg_pinmux_rw_pd_iop___pd3___width 1 449#define reg_pinmux_rw_pd_iop___pd3___bit 3 450#define reg_pinmux_rw_pd_iop___pd4___lsb 4 451#define reg_pinmux_rw_pd_iop___pd4___width 1 452#define reg_pinmux_rw_pd_iop___pd4___bit 4 453#define reg_pinmux_rw_pd_iop___pd5___lsb 5 454#define reg_pinmux_rw_pd_iop___pd5___width 1 455#define reg_pinmux_rw_pd_iop___pd5___bit 5 456#define reg_pinmux_rw_pd_iop___pd6___lsb 6 457#define reg_pinmux_rw_pd_iop___pd6___width 1 458#define reg_pinmux_rw_pd_iop___pd6___bit 6 459#define reg_pinmux_rw_pd_iop___pd7___lsb 7 460#define reg_pinmux_rw_pd_iop___pd7___width 1 461#define reg_pinmux_rw_pd_iop___pd7___bit 7 462#define reg_pinmux_rw_pd_iop___pd8___lsb 8 463#define reg_pinmux_rw_pd_iop___pd8___width 1 464#define reg_pinmux_rw_pd_iop___pd8___bit 8 465#define reg_pinmux_rw_pd_iop___pd9___lsb 9 466#define reg_pinmux_rw_pd_iop___pd9___width 1 467#define reg_pinmux_rw_pd_iop___pd9___bit 9 468#define reg_pinmux_rw_pd_iop___pd10___lsb 10 469#define reg_pinmux_rw_pd_iop___pd10___width 1 470#define reg_pinmux_rw_pd_iop___pd10___bit 10 471#define reg_pinmux_rw_pd_iop___pd11___lsb 11 472#define reg_pinmux_rw_pd_iop___pd11___width 1 473#define reg_pinmux_rw_pd_iop___pd11___bit 11 474#define reg_pinmux_rw_pd_iop___pd12___lsb 12 475#define reg_pinmux_rw_pd_iop___pd12___width 1 476#define reg_pinmux_rw_pd_iop___pd12___bit 12 477#define reg_pinmux_rw_pd_iop___pd13___lsb 13 478#define reg_pinmux_rw_pd_iop___pd13___width 1 479#define reg_pinmux_rw_pd_iop___pd13___bit 13 480#define reg_pinmux_rw_pd_iop___pd14___lsb 14 481#define reg_pinmux_rw_pd_iop___pd14___width 1 482#define reg_pinmux_rw_pd_iop___pd14___bit 14 483#define reg_pinmux_rw_pd_iop___pd15___lsb 15 484#define reg_pinmux_rw_pd_iop___pd15___width 1 485#define reg_pinmux_rw_pd_iop___pd15___bit 15 486#define reg_pinmux_rw_pd_iop___pd16___lsb 16 487#define reg_pinmux_rw_pd_iop___pd16___width 1 488#define reg_pinmux_rw_pd_iop___pd16___bit 16 489#define reg_pinmux_rw_pd_iop___pd17___lsb 17 490#define reg_pinmux_rw_pd_iop___pd17___width 1 491#define reg_pinmux_rw_pd_iop___pd17___bit 17 492#define reg_pinmux_rw_pd_iop_offset 28 493 494/* Register rw_pe_gio, scope pinmux, type rw */ 495#define reg_pinmux_rw_pe_gio___pe0___lsb 0 496#define reg_pinmux_rw_pe_gio___pe0___width 1 497#define reg_pinmux_rw_pe_gio___pe0___bit 0 498#define reg_pinmux_rw_pe_gio___pe1___lsb 1 499#define reg_pinmux_rw_pe_gio___pe1___width 1 500#define reg_pinmux_rw_pe_gio___pe1___bit 1 501#define reg_pinmux_rw_pe_gio___pe2___lsb 2 502#define reg_pinmux_rw_pe_gio___pe2___width 1 503#define reg_pinmux_rw_pe_gio___pe2___bit 2 504#define reg_pinmux_rw_pe_gio___pe3___lsb 3 505#define reg_pinmux_rw_pe_gio___pe3___width 1 506#define reg_pinmux_rw_pe_gio___pe3___bit 3 507#define reg_pinmux_rw_pe_gio___pe4___lsb 4 508#define reg_pinmux_rw_pe_gio___pe4___width 1 509#define reg_pinmux_rw_pe_gio___pe4___bit 4 510#define reg_pinmux_rw_pe_gio___pe5___lsb 5 511#define reg_pinmux_rw_pe_gio___pe5___width 1 512#define reg_pinmux_rw_pe_gio___pe5___bit 5 513#define reg_pinmux_rw_pe_gio___pe6___lsb 6 514#define reg_pinmux_rw_pe_gio___pe6___width 1 515#define reg_pinmux_rw_pe_gio___pe6___bit 6 516#define reg_pinmux_rw_pe_gio___pe7___lsb 7 517#define reg_pinmux_rw_pe_gio___pe7___width 1 518#define reg_pinmux_rw_pe_gio___pe7___bit 7 519#define reg_pinmux_rw_pe_gio___pe8___lsb 8 520#define reg_pinmux_rw_pe_gio___pe8___width 1 521#define reg_pinmux_rw_pe_gio___pe8___bit 8 522#define reg_pinmux_rw_pe_gio___pe9___lsb 9 523#define reg_pinmux_rw_pe_gio___pe9___width 1 524#define reg_pinmux_rw_pe_gio___pe9___bit 9 525#define reg_pinmux_rw_pe_gio___pe10___lsb 10 526#define reg_pinmux_rw_pe_gio___pe10___width 1 527#define reg_pinmux_rw_pe_gio___pe10___bit 10 528#define reg_pinmux_rw_pe_gio___pe11___lsb 11 529#define reg_pinmux_rw_pe_gio___pe11___width 1 530#define reg_pinmux_rw_pe_gio___pe11___bit 11 531#define reg_pinmux_rw_pe_gio___pe12___lsb 12 532#define reg_pinmux_rw_pe_gio___pe12___width 1 533#define reg_pinmux_rw_pe_gio___pe12___bit 12 534#define reg_pinmux_rw_pe_gio___pe13___lsb 13 535#define reg_pinmux_rw_pe_gio___pe13___width 1 536#define reg_pinmux_rw_pe_gio___pe13___bit 13 537#define reg_pinmux_rw_pe_gio___pe14___lsb 14 538#define reg_pinmux_rw_pe_gio___pe14___width 1 539#define reg_pinmux_rw_pe_gio___pe14___bit 14 540#define reg_pinmux_rw_pe_gio___pe15___lsb 15 541#define reg_pinmux_rw_pe_gio___pe15___width 1 542#define reg_pinmux_rw_pe_gio___pe15___bit 15 543#define reg_pinmux_rw_pe_gio___pe16___lsb 16 544#define reg_pinmux_rw_pe_gio___pe16___width 1 545#define reg_pinmux_rw_pe_gio___pe16___bit 16 546#define reg_pinmux_rw_pe_gio___pe17___lsb 17 547#define reg_pinmux_rw_pe_gio___pe17___width 1 548#define reg_pinmux_rw_pe_gio___pe17___bit 17 549#define reg_pinmux_rw_pe_gio_offset 32 550 551/* Register rw_pe_iop, scope pinmux, type rw */ 552#define reg_pinmux_rw_pe_iop___pe0___lsb 0 553#define reg_pinmux_rw_pe_iop___pe0___width 1 554#define reg_pinmux_rw_pe_iop___pe0___bit 0 555#define reg_pinmux_rw_pe_iop___pe1___lsb 1 556#define reg_pinmux_rw_pe_iop___pe1___width 1 557#define reg_pinmux_rw_pe_iop___pe1___bit 1 558#define reg_pinmux_rw_pe_iop___pe2___lsb 2 559#define reg_pinmux_rw_pe_iop___pe2___width 1 560#define reg_pinmux_rw_pe_iop___pe2___bit 2 561#define reg_pinmux_rw_pe_iop___pe3___lsb 3 562#define reg_pinmux_rw_pe_iop___pe3___width 1 563#define reg_pinmux_rw_pe_iop___pe3___bit 3 564#define reg_pinmux_rw_pe_iop___pe4___lsb 4 565#define reg_pinmux_rw_pe_iop___pe4___width 1 566#define reg_pinmux_rw_pe_iop___pe4___bit 4 567#define reg_pinmux_rw_pe_iop___pe5___lsb 5 568#define reg_pinmux_rw_pe_iop___pe5___width 1 569#define reg_pinmux_rw_pe_iop___pe5___bit 5 570#define reg_pinmux_rw_pe_iop___pe6___lsb 6 571#define reg_pinmux_rw_pe_iop___pe6___width 1 572#define reg_pinmux_rw_pe_iop___pe6___bit 6 573#define reg_pinmux_rw_pe_iop___pe7___lsb 7 574#define reg_pinmux_rw_pe_iop___pe7___width 1 575#define reg_pinmux_rw_pe_iop___pe7___bit 7 576#define reg_pinmux_rw_pe_iop___pe8___lsb 8 577#define reg_pinmux_rw_pe_iop___pe8___width 1 578#define reg_pinmux_rw_pe_iop___pe8___bit 8 579#define reg_pinmux_rw_pe_iop___pe9___lsb 9 580#define reg_pinmux_rw_pe_iop___pe9___width 1 581#define reg_pinmux_rw_pe_iop___pe9___bit 9 582#define reg_pinmux_rw_pe_iop___pe10___lsb 10 583#define reg_pinmux_rw_pe_iop___pe10___width 1 584#define reg_pinmux_rw_pe_iop___pe10___bit 10 585#define reg_pinmux_rw_pe_iop___pe11___lsb 11 586#define reg_pinmux_rw_pe_iop___pe11___width 1 587#define reg_pinmux_rw_pe_iop___pe11___bit 11 588#define reg_pinmux_rw_pe_iop___pe12___lsb 12 589#define reg_pinmux_rw_pe_iop___pe12___width 1 590#define reg_pinmux_rw_pe_iop___pe12___bit 12 591#define reg_pinmux_rw_pe_iop___pe13___lsb 13 592#define reg_pinmux_rw_pe_iop___pe13___width 1 593#define reg_pinmux_rw_pe_iop___pe13___bit 13 594#define reg_pinmux_rw_pe_iop___pe14___lsb 14 595#define reg_pinmux_rw_pe_iop___pe14___width 1 596#define reg_pinmux_rw_pe_iop___pe14___bit 14 597#define reg_pinmux_rw_pe_iop___pe15___lsb 15 598#define reg_pinmux_rw_pe_iop___pe15___width 1 599#define reg_pinmux_rw_pe_iop___pe15___bit 15 600#define reg_pinmux_rw_pe_iop___pe16___lsb 16 601#define reg_pinmux_rw_pe_iop___pe16___width 1 602#define reg_pinmux_rw_pe_iop___pe16___bit 16 603#define reg_pinmux_rw_pe_iop___pe17___lsb 17 604#define reg_pinmux_rw_pe_iop___pe17___width 1 605#define reg_pinmux_rw_pe_iop___pe17___bit 17 606#define reg_pinmux_rw_pe_iop_offset 36 607 608/* Register rw_usb_phy, scope pinmux, type rw */ 609#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 610#define reg_pinmux_rw_usb_phy___en_usb0___width 1 611#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 612#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 613#define reg_pinmux_rw_usb_phy___en_usb1___width 1 614#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 615#define reg_pinmux_rw_usb_phy_offset 40 616 617 618/* Constants */ 619#define regk_pinmux_no 0x00000000 620#define regk_pinmux_rw_hwprot_default 0x00000000 621#define regk_pinmux_rw_pa_default 0x00000000 622#define regk_pinmux_rw_pb_gio_default 0x00000000 623#define regk_pinmux_rw_pb_iop_default 0x00000000 624#define regk_pinmux_rw_pc_gio_default 0x00000000 625#define regk_pinmux_rw_pc_iop_default 0x00000000 626#define regk_pinmux_rw_pd_gio_default 0x00000000 627#define regk_pinmux_rw_pd_iop_default 0x00000000 628#define regk_pinmux_rw_pe_gio_default 0x00000000 629#define regk_pinmux_rw_pe_iop_default 0x00000000 630#define regk_pinmux_rw_usb_phy_default 0x00000000 631#define regk_pinmux_yes 0x00000001 632#endif /* __pinmux_defs_asm_h */ 633