1#ifndef __iop_sw_cfg_defs_asm_h 2#define __iop_sw_cfg_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r 7 * id: <not found> 8 * last modfied: Mon Apr 11 16:10:19 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r 11 * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ 57#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0 58#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2 59#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0 60 61/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ 62#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0 63#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2 64#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4 65 66/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ 67#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0 68#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2 69#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8 70 71/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ 72#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0 73#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2 74#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12 75 76/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ 77#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0 78#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2 79#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16 80 81/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ 82#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0 83#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2 84#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20 85 86/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ 87#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0 88#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2 89#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24 90 91/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ 92#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0 93#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2 94#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28 95 96/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ 97#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0 98#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2 99#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32 100 101/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ 102#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0 103#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2 104#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36 105 106/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ 107#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0 108#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2 109#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40 110 111/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ 112#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0 113#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2 114#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44 115 116/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ 117#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0 118#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2 119#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48 120 121/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ 122#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0 123#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2 124#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52 125 126/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ 127#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 128#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 129#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56 130 131/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ 132#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 133#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 134#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60 135 136/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ 137#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0 138#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2 139#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64 140 141/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ 142#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0 143#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2 144#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68 145 146/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ 147#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0 148#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2 149#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72 150 151/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ 152#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0 153#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2 154#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76 155 156/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ 157#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0 158#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2 159#define reg_iop_sw_cfg_rw_spu0_owner_offset 80 160 161/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ 162#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0 163#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2 164#define reg_iop_sw_cfg_rw_spu1_owner_offset 84 165 166/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ 167#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 168#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 169#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88 170 171/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ 172#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 173#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 174#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92 175 176/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ 177#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0 178#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2 179#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96 180 181/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ 182#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0 183#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2 184#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100 185 186/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ 187#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 188#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 189#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104 190 191/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ 192#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 193#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 194#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108 195 196/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ 197#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 198#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 199#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112 200 201/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ 202#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 203#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 204#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116 205 206/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ 207#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 208#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 209#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120 210 211/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ 212#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 213#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 214#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124 215 216/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ 217#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 218#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 219#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128 220 221/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ 222#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 223#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 224#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132 225 226/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ 227#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0 228#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8 229#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8 230#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8 231#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16 232#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8 233#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24 234#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8 235#define reg_iop_sw_cfg_rw_bus0_mask_offset 136 236 237/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ 238#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0 239#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1 240#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0 241#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1 242#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1 243#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1 244#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2 245#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1 246#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2 247#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3 248#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1 249#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3 250#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140 251 252/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ 253#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0 254#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8 255#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8 256#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8 257#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16 258#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8 259#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24 260#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8 261#define reg_iop_sw_cfg_rw_bus1_mask_offset 144 262 263/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ 264#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0 265#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1 266#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0 267#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1 268#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1 269#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1 270#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2 271#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1 272#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2 273#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3 274#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1 275#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3 276#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148 277 278/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ 279#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 280#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 281#define reg_iop_sw_cfg_rw_gio_mask_offset 152 282 283/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ 284#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 285#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 286#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156 287 288/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ 289#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0 290#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2 291#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2 292#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2 293#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4 294#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2 295#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6 296#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2 297#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8 298#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2 299#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10 300#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2 301#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12 302#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2 303#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14 304#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2 305#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16 306#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 307#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18 308#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 309#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20 310#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 311#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22 312#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 313#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24 314#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 315#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26 316#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 317#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28 318#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 319#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30 320#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 321#define reg_iop_sw_cfg_rw_pinmapping_offset 160 322 323/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ 324#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0 325#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3 326#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3 327#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3 328#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6 329#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3 330#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9 331#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3 332#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12 333#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3 334#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15 335#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3 336#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18 337#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3 338#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21 339#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3 340#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164 341 342/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ 343#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 344#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4 345#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4 346#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2 347#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6 348#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4 349#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10 350#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2 351#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12 352#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4 353#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16 354#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2 355#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18 356#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4 357#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22 358#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2 359#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168 360 361/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ 362#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 363#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4 364#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4 365#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2 366#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6 367#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4 368#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10 369#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2 370#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12 371#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4 372#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16 373#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2 374#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18 375#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4 376#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22 377#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2 378#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172 379 380/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ 381#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 382#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4 383#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4 384#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2 385#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6 386#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4 387#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10 388#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2 389#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12 390#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4 391#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16 392#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2 393#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18 394#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4 395#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22 396#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2 397#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176 398 399/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ 400#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 401#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4 402#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4 403#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2 404#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6 405#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4 406#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10 407#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2 408#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12 409#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4 410#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16 411#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2 412#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18 413#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4 414#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22 415#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2 416#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180 417 418/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ 419#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 420#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4 421#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4 422#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2 423#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6 424#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4 425#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10 426#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2 427#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12 428#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4 429#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16 430#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2 431#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18 432#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4 433#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22 434#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2 435#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184 436 437/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ 438#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 439#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4 440#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4 441#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2 442#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6 443#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4 444#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10 445#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2 446#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12 447#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4 448#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16 449#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2 450#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18 451#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4 452#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22 453#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2 454#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188 455 456/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ 457#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 458#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4 459#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4 460#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2 461#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6 462#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4 463#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10 464#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2 465#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12 466#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4 467#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16 468#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2 469#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18 470#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4 471#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22 472#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2 473#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192 474 475/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ 476#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 477#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4 478#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4 479#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2 480#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6 481#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4 482#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10 483#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2 484#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12 485#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4 486#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16 487#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2 488#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18 489#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4 490#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22 491#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2 492#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196 493 494/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ 495#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0 496#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2 497#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2 498#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2 499#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200 500 501/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ 502#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0 503#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2 504#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2 505#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2 506#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204 507 508/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ 509#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 510#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 511#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 512#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1 513#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3 514#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4 515#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1 516#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4 517#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5 518#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1 519#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5 520#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6 521#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1 522#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6 523#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7 524#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1 525#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7 526#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8 527#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1 528#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8 529#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9 530#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1 531#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9 532#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10 533#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1 534#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10 535#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208 536 537/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ 538#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 539#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 540#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 541#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1 542#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3 543#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4 544#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1 545#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4 546#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5 547#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1 548#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5 549#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6 550#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1 551#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6 552#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7 553#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1 554#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7 555#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8 556#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1 557#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8 558#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9 559#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1 560#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9 561#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10 562#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1 563#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10 564#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212 565 566/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ 567#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0 568#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3 569#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3 570#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1 571#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3 572#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4 573#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1 574#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4 575#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5 576#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1 577#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5 578#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6 579#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1 580#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6 581#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7 582#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1 583#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7 584#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8 585#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1 586#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8 587#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9 588#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1 589#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9 590#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10 591#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1 592#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10 593#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216 594 595/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ 596#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0 597#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3 598#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3 599#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1 600#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3 601#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4 602#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1 603#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4 604#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5 605#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1 606#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5 607#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6 608#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1 609#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6 610#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7 611#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1 612#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7 613#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8 614#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1 615#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8 616#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9 617#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1 618#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9 619#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10 620#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1 621#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10 622#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220 623 624/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ 625#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 626#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 627#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 628#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 629#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 630#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 631#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 632#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 633#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 634#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 635#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 636#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 637#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 638#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 639#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 640#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 641#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 642#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 643#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 644#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 645#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 646#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 647#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 648#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 649#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 650#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 651#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 652#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 653#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 654#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 655#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 656#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 657#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 658#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 659#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 660#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 661#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 662#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 663#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 664#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 665#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 666#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 667#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 668#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 669#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 670#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 671#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 672#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 673#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224 674 675/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ 676#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0 677#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1 678#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0 679#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1 680#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5 681#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6 682#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3 683#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9 684#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3 685#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12 686#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2 687#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14 688#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4 689#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18 690#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1 691#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18 692#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228 693 694/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ 695#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0 696#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1 697#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0 698#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1 699#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5 700#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6 701#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3 702#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9 703#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3 704#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12 705#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2 706#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14 707#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4 708#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18 709#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1 710#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18 711#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232 712 713/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ 714#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0 715#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3 716#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3 717#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3 718#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6 719#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3 720#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9 721#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2 722#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11 723#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3 724#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14 725#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3 726#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17 727#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2 728#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19 729#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3 730#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236 731 732 733/* Constants */ 734#define regk_iop_sw_cfg_a 0x00000001 735#define regk_iop_sw_cfg_b 0x00000002 736#define regk_iop_sw_cfg_bus0 0x00000000 737#define regk_iop_sw_cfg_bus0_rot16 0x00000004 738#define regk_iop_sw_cfg_bus0_rot24 0x00000006 739#define regk_iop_sw_cfg_bus0_rot8 0x00000002 740#define regk_iop_sw_cfg_bus1 0x00000001 741#define regk_iop_sw_cfg_bus1_rot16 0x00000005 742#define regk_iop_sw_cfg_bus1_rot24 0x00000007 743#define regk_iop_sw_cfg_bus1_rot8 0x00000003 744#define regk_iop_sw_cfg_clk12 0x00000000 745#define regk_iop_sw_cfg_cpu 0x00000000 746#define regk_iop_sw_cfg_dmc0 0x00000000 747#define regk_iop_sw_cfg_dmc1 0x00000001 748#define regk_iop_sw_cfg_gated_clk0 0x00000010 749#define regk_iop_sw_cfg_gated_clk1 0x00000011 750#define regk_iop_sw_cfg_gated_clk2 0x00000012 751#define regk_iop_sw_cfg_gated_clk3 0x00000013 752#define regk_iop_sw_cfg_gio0 0x00000004 753#define regk_iop_sw_cfg_gio1 0x00000001 754#define regk_iop_sw_cfg_gio2 0x00000005 755#define regk_iop_sw_cfg_gio3 0x00000002 756#define regk_iop_sw_cfg_gio4 0x00000006 757#define regk_iop_sw_cfg_gio5 0x00000003 758#define regk_iop_sw_cfg_gio6 0x00000007 759#define regk_iop_sw_cfg_gio7 0x00000004 760#define regk_iop_sw_cfg_gio_in0 0x00000000 761#define regk_iop_sw_cfg_gio_in1 0x00000001 762#define regk_iop_sw_cfg_gio_in10 0x00000002 763#define regk_iop_sw_cfg_gio_in11 0x00000003 764#define regk_iop_sw_cfg_gio_in14 0x00000004 765#define regk_iop_sw_cfg_gio_in15 0x00000005 766#define regk_iop_sw_cfg_gio_in18 0x00000002 767#define regk_iop_sw_cfg_gio_in19 0x00000003 768#define regk_iop_sw_cfg_gio_in20 0x00000004 769#define regk_iop_sw_cfg_gio_in21 0x00000005 770#define regk_iop_sw_cfg_gio_in26 0x00000006 771#define regk_iop_sw_cfg_gio_in27 0x00000007 772#define regk_iop_sw_cfg_gio_in28 0x00000006 773#define regk_iop_sw_cfg_gio_in29 0x00000007 774#define regk_iop_sw_cfg_gio_in4 0x00000000 775#define regk_iop_sw_cfg_gio_in5 0x00000001 776#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 777#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001 778#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002 779#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003 780#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002 781#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003 782#define regk_iop_sw_cfg_mpu 0x00000001 783#define regk_iop_sw_cfg_none 0x00000000 784#define regk_iop_sw_cfg_par0 0x00000000 785#define regk_iop_sw_cfg_par1 0x00000001 786#define regk_iop_sw_cfg_pdp_out0 0x00000002 787#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001 788#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005 789#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000 790#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004 791#define regk_iop_sw_cfg_pdp_out1 0x00000003 792#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003 793#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005 794#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002 795#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004 796#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000 797#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000 798#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000 799#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000 800#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 801#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000 802#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000 803#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000 804#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000 805#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000 806#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000 807#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000 808#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000 809#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000 810#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000 811#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000 812#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000 813#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000 814#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000 815#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 816#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 817#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 818#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 819#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 820#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 821#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 822#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 823#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 824#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 825#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000 826#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000 827#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555 828#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 829#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 830#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000 831#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000 832#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000 833#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000 834#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 835#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000 836#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000 837#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000 838#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000 839#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 840#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 841#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 842#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 843#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000 844#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000 845#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000 846#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000 847#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 848#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 849#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 850#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 851#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 852#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 853#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 854#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 855#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 856#define regk_iop_sw_cfg_sdp_out0 0x00000008 857#define regk_iop_sw_cfg_sdp_out1 0x00000009 858#define regk_iop_sw_cfg_size16 0x00000002 859#define regk_iop_sw_cfg_size24 0x00000003 860#define regk_iop_sw_cfg_size32 0x00000004 861#define regk_iop_sw_cfg_size8 0x00000001 862#define regk_iop_sw_cfg_spu0 0x00000002 863#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006 864#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006 865#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007 866#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007 867#define regk_iop_sw_cfg_spu0_g0 0x0000000e 868#define regk_iop_sw_cfg_spu0_g1 0x0000000e 869#define regk_iop_sw_cfg_spu0_g2 0x0000000e 870#define regk_iop_sw_cfg_spu0_g3 0x0000000e 871#define regk_iop_sw_cfg_spu0_g4 0x0000000e 872#define regk_iop_sw_cfg_spu0_g5 0x0000000e 873#define regk_iop_sw_cfg_spu0_g6 0x0000000e 874#define regk_iop_sw_cfg_spu0_g7 0x0000000e 875#define regk_iop_sw_cfg_spu0_gio0 0x00000000 876#define regk_iop_sw_cfg_spu0_gio1 0x00000001 877#define regk_iop_sw_cfg_spu0_gio2 0x00000000 878#define regk_iop_sw_cfg_spu0_gio5 0x00000005 879#define regk_iop_sw_cfg_spu0_gio6 0x00000006 880#define regk_iop_sw_cfg_spu0_gio7 0x00000007 881#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008 882#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009 883#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a 884#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b 885#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c 886#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d 887#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e 888#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f 889#define regk_iop_sw_cfg_spu0_gioout0 0x00000000 890#define regk_iop_sw_cfg_spu0_gioout1 0x00000000 891#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e 892#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e 893#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e 894#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e 895#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e 896#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e 897#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e 898#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e 899#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e 900#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e 901#define regk_iop_sw_cfg_spu0_gioout2 0x00000002 902#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e 903#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e 904#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e 905#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e 906#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e 907#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e 908#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e 909#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e 910#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e 911#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e 912#define regk_iop_sw_cfg_spu0_gioout3 0x00000002 913#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e 914#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e 915#define regk_iop_sw_cfg_spu0_gioout4 0x00000004 916#define regk_iop_sw_cfg_spu0_gioout5 0x00000004 917#define regk_iop_sw_cfg_spu0_gioout6 0x00000006 918#define regk_iop_sw_cfg_spu0_gioout7 0x00000006 919#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e 920#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e 921#define regk_iop_sw_cfg_spu1 0x00000003 922#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006 923#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006 924#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007 925#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007 926#define regk_iop_sw_cfg_spu1_g0 0x0000000f 927#define regk_iop_sw_cfg_spu1_g1 0x0000000f 928#define regk_iop_sw_cfg_spu1_g2 0x0000000f 929#define regk_iop_sw_cfg_spu1_g3 0x0000000f 930#define regk_iop_sw_cfg_spu1_g4 0x0000000f 931#define regk_iop_sw_cfg_spu1_g5 0x0000000f 932#define regk_iop_sw_cfg_spu1_g6 0x0000000f 933#define regk_iop_sw_cfg_spu1_g7 0x0000000f 934#define regk_iop_sw_cfg_spu1_gio0 0x00000002 935#define regk_iop_sw_cfg_spu1_gio1 0x00000003 936#define regk_iop_sw_cfg_spu1_gio2 0x00000002 937#define regk_iop_sw_cfg_spu1_gio5 0x00000005 938#define regk_iop_sw_cfg_spu1_gio6 0x00000006 939#define regk_iop_sw_cfg_spu1_gio7 0x00000007 940#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008 941#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009 942#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a 943#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b 944#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c 945#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d 946#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e 947#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f 948#define regk_iop_sw_cfg_spu1_gioout0 0x00000001 949#define regk_iop_sw_cfg_spu1_gioout1 0x00000001 950#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f 951#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f 952#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f 953#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f 954#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f 955#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f 956#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f 957#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f 958#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f 959#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f 960#define regk_iop_sw_cfg_spu1_gioout2 0x00000003 961#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f 962#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f 963#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f 964#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f 965#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f 966#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f 967#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f 968#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f 969#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f 970#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f 971#define regk_iop_sw_cfg_spu1_gioout3 0x00000003 972#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f 973#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f 974#define regk_iop_sw_cfg_spu1_gioout4 0x00000005 975#define regk_iop_sw_cfg_spu1_gioout5 0x00000005 976#define regk_iop_sw_cfg_spu1_gioout6 0x00000007 977#define regk_iop_sw_cfg_spu1_gioout7 0x00000007 978#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f 979#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f 980#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 981#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 982#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001 983#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 984#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003 985#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002 986#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003 987#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002 988#define regk_iop_sw_cfg_timer_grp0 0x00000000 989#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 990#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a 991#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a 992#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a 993#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a 994#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004 995#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004 996#define regk_iop_sw_cfg_timer_grp1 0x00000000 997#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 998#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b 999#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b 1000#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b 1001#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b 1002#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005 1003#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005 1004#define regk_iop_sw_cfg_timer_grp2 0x00000000 1005#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001 1006#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c 1007#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c 1008#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c 1009#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c 1010#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006 1011#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006 1012#define regk_iop_sw_cfg_timer_grp3 0x00000000 1013#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001 1014#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d 1015#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d 1016#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d 1017#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d 1018#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007 1019#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007 1020#define regk_iop_sw_cfg_trig0_0 0x00000000 1021#define regk_iop_sw_cfg_trig0_1 0x00000000 1022#define regk_iop_sw_cfg_trig0_2 0x00000000 1023#define regk_iop_sw_cfg_trig0_3 0x00000000 1024#define regk_iop_sw_cfg_trig1_0 0x00000000 1025#define regk_iop_sw_cfg_trig1_1 0x00000000 1026#define regk_iop_sw_cfg_trig1_2 0x00000000 1027#define regk_iop_sw_cfg_trig1_3 0x00000000 1028#define regk_iop_sw_cfg_trig2_0 0x00000000 1029#define regk_iop_sw_cfg_trig2_1 0x00000000 1030#define regk_iop_sw_cfg_trig2_2 0x00000000 1031#define regk_iop_sw_cfg_trig2_3 0x00000000 1032#define regk_iop_sw_cfg_trig3_0 0x00000000 1033#define regk_iop_sw_cfg_trig3_1 0x00000000 1034#define regk_iop_sw_cfg_trig3_2 0x00000000 1035#define regk_iop_sw_cfg_trig3_3 0x00000000 1036#define regk_iop_sw_cfg_trig4_0 0x00000001 1037#define regk_iop_sw_cfg_trig4_1 0x00000001 1038#define regk_iop_sw_cfg_trig4_2 0x00000001 1039#define regk_iop_sw_cfg_trig4_3 0x00000001 1040#define regk_iop_sw_cfg_trig5_0 0x00000001 1041#define regk_iop_sw_cfg_trig5_1 0x00000001 1042#define regk_iop_sw_cfg_trig5_2 0x00000001 1043#define regk_iop_sw_cfg_trig5_3 0x00000001 1044#define regk_iop_sw_cfg_trig6_0 0x00000001 1045#define regk_iop_sw_cfg_trig6_1 0x00000001 1046#define regk_iop_sw_cfg_trig6_2 0x00000001 1047#define regk_iop_sw_cfg_trig6_3 0x00000001 1048#define regk_iop_sw_cfg_trig7_0 0x00000001 1049#define regk_iop_sw_cfg_trig7_1 0x00000001 1050#define regk_iop_sw_cfg_trig7_2 0x00000001 1051#define regk_iop_sw_cfg_trig7_3 0x00000001 1052#endif /* __iop_sw_cfg_defs_asm_h */ 1053