1#ifndef _ASM_CRIS_ARCH_CACHE_H 2#define _ASM_CRIS_ARCH_CACHE_H 3 4#include <arch/hwregs/dma.h> 5 6/* A cache-line is 32 bytes. */ 7#define L1_CACHE_BYTES 32 8#define L1_CACHE_SHIFT 5 9 10#define __read_mostly __attribute__((__section__(".data.read_mostly"))) 11 12void flush_dma_list(dma_descr_data *descr); 13void flush_dma_descr(dma_descr_data *descr, int flush_buf); 14 15#define flush_dma_context(c) \ 16 flush_dma_list(phys_to_virt((c)->saved_data)); 17 18void cris_flush_cache_range(void *buf, unsigned long len); 19void cris_flush_cache(void); 20 21#endif /* _ASM_CRIS_ARCH_CACHE_H */ 22